commit	df63ac1818fc2659a0168a37f519e9a55e177fce	[log] [tgz]
author	zeeshanrafique23 <zeeshanrafique23@gmail.com>	Mon Jun 21 11:08:11 2021 +0500
committer	zeeshanrafique23 <zeeshanrafique23@gmail.com>	Mon Jun 21 11:08:11 2021 +0500
tree	debdec879285c80078ae8bafd1a94dae36281b82
parent	7f8fd807cd6b1de05a43b82c9f3b3039c25bc092 [diff]

updated GDS -wlvs-err

gds/azadi_soc_top_caravel.gds[Deleted - diff]
gds/azadi_soc_top_caravel.gds.gz[Added - diff]
gds/user_project_wrapper.gds[Deleted - diff]
gds/user_project_wrapper.gds.gz[Added - diff]

4 files changed

tree: debdec879285c80078ae8bafd1a94dae36281b82

.github/
def/
docs/
gds/
lef/
mag/
maglef/
openlane/
signoff/
spi/
verilog/
caravel
.gitignore
.gitmodules
info.yaml
LICENSE
Makefile
README.md

README.md

Caravel User Project

Azadi RISC-V SoC

Azadi is an SoC with 32-bit RISC-V uni-core “buraq”, buraq is in-order core with a 3-stage pipeline that implements the RV32IMFD instruction set architecture.