commit a368e76236301eedaf5e97915c7ca9c399c7b08d
author muhammadwaleed99 <muhammadwaleed99> Mon Jul 05 14:08:58 2021 +0500
committer muhammadwaleed99 <muhammadwaleed99> Mon Jul 05 14:08:58 2021 +0500
tree e6bee84000d78f554213d499080124cfd27efbf6
parent 204d8953e638b17899197ec2fd8947dca2330eed

updated README.md

README.md

diff --git a/README.md b/README.md
index f6af6a9..c0d0214 100644
--- a/README.md
+++ b/README.md
@@ -19,8 +19,8 @@
 
 [![License](https://img.shields.io/badge/License-Apache%202.0-blue.svg)](https://opensource.org/licenses/Apache-2.0) [![UPRJ_CI](https://github.com/efabless/caravel_project_example/actions/workflows/user_project_ci.yml/badge.svg)](https://github.com/efabless/caravel_project_example/actions/workflows/user_project_ci.yml) [![Caravel Build](https://github.com/efabless/caravel_project_example/actions/workflows/caravel_build.yml/badge.svg)](https://github.com/efabless/caravel_project_example/actions/workflows/caravel_build.yml)
 
-# Azadi RISC-V SoC
-Azadi is an SoC with a 32-bit RISC-V signal core extended version of [ibex](https://github.com/lowRISC/ibex) we named it "buraq", it is a 3-stage pipeline core that implements the RV32IMF instruction set architecture, a limited number of peripherals UART, SPI, GPIO, PWM, and timer. The parent repository of azadi-soc can be found [here](https://github.com/merledu/azadi).
+# Uqab RISC-V SoC
+Uqab is an SoC which hold 32-bit RISCV based processor and have peripherals (Pulse Width Modulation (PWM) ,Serial Peripheral Interface (SPI),General Purpose Input Output  (GPIO), and Timer)
 
 ## Azadi SoC DFFRAM: Flattened with user_project_wrapper
 ![azadi-gds](images/gds.png)