commit 3dc36666183ca81c214b47ea89554bb110c63017
author zeeshanrafique23 <zeeshanrafique23@gmail.com> Thu Jun 17 12:05:34 2021 +0500
committer zeeshanrafique23 <zeeshanrafique23@gmail.com> Thu Jun 17 12:05:34 2021 +0500
tree a08fb9f2f3e231a202a550d5a05d2c9a254f81ec
parent 7bb22506907a70615863eb7d74f5c18d294d9145

removed unused input from rstmgr

verilog/rtl/azadi_soc_top.v

diff --git a/verilog/rtl/azadi_soc_top.v b/verilog/rtl/azadi_soc_top.v
index c34f2b2..177099b 100644
--- a/verilog/rtl/azadi_soc_top.v
+++ b/verilog/rtl/azadi_soc_top.v
@@ -1420,13 +1420,11 @@
 	clk_i,
 	rst_ni,
 	prog_rst_ni,
-	ndmreset,
 	sys_rst_ni
 );
 	input clk_i;
 	input rst_ni;
 	input prog_rst_ni;
-	input wire ndmreset;
 	output reg sys_rst_ni;
 	reg [1:0] rst_fsm_cs;
 	reg [1:0] rst_fsm_ns;