Sign in
foss-eda-tools
/
third_party
/
shuttle
/
sky130
/
mpw-002
/
slot-018
/
3dc36666183ca81c214b47ea89554bb110c63017
commit
3dc36666183ca81c214b47ea89554bb110c63017
[
log
]
[
tgz
]
author
zeeshanrafique23 <zeeshanrafique23@gmail.com>
Thu Jun 17 12:05:34 2021 +0500
committer
zeeshanrafique23 <zeeshanrafique23@gmail.com>
Thu Jun 17 12:05:34 2021 +0500
tree
a08fb9f2f3e231a202a550d5a05d2c9a254f81ec
parent
7bb22506907a70615863eb7d74f5c18d294d9145
[
diff
]
removed unused input from rstmgr
verilog/rtl/azadi_soc_top.v
[
diff
]
1 file changed
tree: a08fb9f2f3e231a202a550d5a05d2c9a254f81ec
.github/
def/
docs/
gds/
lef/
mag/
maglef/
openlane/
signoff/
spi/
verilog/
caravel
.gitignore
.gitmodules
info.yaml
LICENSE
Makefile
README.md
README.md
Caravel User Project
:exclamation: Important Note
Please fill in your project documentation in this README.md file
Refer to
README
for this sample project documentation.