Merge branch 'main' of https://github.com/efabless/caravel_user_project into main
tree: 1f0c7f0542c460c3c222912a19e55cddd6c17089
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. images/
  6. lef/
  7. mag/
  8. maglef/
  9. openlane/
  10. signoff/
  11. spi/
  12. verilog/
  13. .gitignore
  14. .gitmodules
  15. info.yaml
  16. LICENSE
  17. Makefile
  18. README.md
README.md

Caravel User Project

License UPRJ_CI Caravel Build

Azadi RISC-V SoC

Azadi is an SoC with 32-bit RISC-V signal core extented version of ibex we named it as “buraq”, it is a 3-stage pipeline core which implements the RV32IMF instruction set architecture, limited number of peripherals UART, SPI, GPIO, PWM and timer. The parent repository of azadi-soc can be found here.

Azadi SoC DFFRAM: Flattened with user_project_wrapper

azadi-gds