commit 1eb755f98f285d95a3819d935d5c9441ffc3fc76
author zeeshanrafique23 <zeeshanrafique23@gmail.com> Wed Jun 16 01:14:52 2021 +0500
committer zeeshanrafique23 <zeeshanrafique23@gmail.com> Wed Jun 16 01:14:52 2021 +0500
tree 5fd58ac4f2927b03ccd8cd099e61f9b4dc3c6194
parent 86d3a80d3dbb057403b1a5dd59a8ee6af818e084

corrected the UART pins

verilog/rtl/azadi_soc_top_caravel.v

diff --git a/verilog/rtl/azadi_soc_top_caravel.v b/verilog/rtl/azadi_soc_top_caravel.v
index 1ef1f0e..686626d 100644
--- a/verilog/rtl/azadi_soc_top_caravel.v
+++ b/verilog/rtl/azadi_soc_top_caravel.v
@@ -108,12 +108,12 @@
   assign io_out[4]     =  sclk_o;
 
   // UART 
-  assign io_oeb[5]     =  1'b0;
-  assign io_out[5]     =  uart_tx;
-  
-  assign io_oeb[6]     =  1'b1;
-  assign uart_rx       =  io_in[6];
-  
+  assign io_oeb[5]     =  1'b1;
+  assign uart_rx       =  io_in[5];
+
+  assign io_oeb[6]     =  1'b0;
+  assign io_out[6]     =  uart_tx;
+    
   // Programming Button 
   assign io_oeb[7]     =  1'b1;
   assign prog          =  io_in[7];