Import from MPW#1 workspace
https://github.com/thesourcerer8/caravel-stdcelllib-stdcells/
diff --git a/cells/gds/AND2X1.gds b/cells/gds/AND2X1.gds
new file mode 100644
index 0000000..a3dd72f
--- /dev/null
+++ b/cells/gds/AND2X1.gds
Binary files differ
diff --git a/cells/gds/AND2X2.gds b/cells/gds/AND2X2.gds
new file mode 100644
index 0000000..5db1bd8
--- /dev/null
+++ b/cells/gds/AND2X2.gds
Binary files differ
diff --git a/cells/gds/AOI21X1.gds b/cells/gds/AOI21X1.gds
new file mode 100644
index 0000000..3aab362
--- /dev/null
+++ b/cells/gds/AOI21X1.gds
Binary files differ
diff --git a/cells/gds/AOI22X1.gds b/cells/gds/AOI22X1.gds
new file mode 100644
index 0000000..8783482
--- /dev/null
+++ b/cells/gds/AOI22X1.gds
Binary files differ
diff --git a/cells/gds/BUFX2.gds b/cells/gds/BUFX2.gds
new file mode 100644
index 0000000..e316621
--- /dev/null
+++ b/cells/gds/BUFX2.gds
Binary files differ
diff --git a/cells/gds/BUFX4.gds b/cells/gds/BUFX4.gds
new file mode 100644
index 0000000..ae3c08a
--- /dev/null
+++ b/cells/gds/BUFX4.gds
Binary files differ
diff --git a/cells/gds/CLKBUF1.gds b/cells/gds/CLKBUF1.gds
new file mode 100644
index 0000000..81e2bed
--- /dev/null
+++ b/cells/gds/CLKBUF1.gds
Binary files differ
diff --git a/cells/gds/HAX1.gds b/cells/gds/HAX1.gds
new file mode 100644
index 0000000..865ce83
--- /dev/null
+++ b/cells/gds/HAX1.gds
Binary files differ
diff --git a/cells/gds/INV.gds b/cells/gds/INV.gds
new file mode 100644
index 0000000..f438358
--- /dev/null
+++ b/cells/gds/INV.gds
Binary files differ
diff --git a/cells/gds/INVX1.gds b/cells/gds/INVX1.gds
new file mode 100644
index 0000000..9ee47af
--- /dev/null
+++ b/cells/gds/INVX1.gds
Binary files differ
diff --git a/cells/gds/INVX2.gds b/cells/gds/INVX2.gds
new file mode 100644
index 0000000..3216ca0
--- /dev/null
+++ b/cells/gds/INVX2.gds
Binary files differ
diff --git a/cells/gds/INVX4.gds b/cells/gds/INVX4.gds
new file mode 100644
index 0000000..ebf46b9
--- /dev/null
+++ b/cells/gds/INVX4.gds
Binary files differ
diff --git a/cells/gds/INVX8.gds b/cells/gds/INVX8.gds
new file mode 100644
index 0000000..875c561
--- /dev/null
+++ b/cells/gds/INVX8.gds
Binary files differ
diff --git a/cells/gds/LATCH.gds b/cells/gds/LATCH.gds
new file mode 100644
index 0000000..cf892a1
--- /dev/null
+++ b/cells/gds/LATCH.gds
Binary files differ
diff --git a/cells/lef/AND2X1.lef b/cells/lef/AND2X1.lef
new file mode 100644
index 0000000..2b2fbbc
--- /dev/null
+++ b/cells/lef/AND2X1.lef
@@ -0,0 +1,65 @@
+VERSION 5.7 ;
+ NOWIREEXTENSIONATPIN ON ;
+ DIVIDERCHAR "/" ;
+ BUSBITCHARS "[]" ;
+MACRO AND2X1
+ CLASS CORE ;
+ FOREIGN AND2X1 ;
+ ORIGIN 0.000 0.000 ;
+ SIZE 5.760 BY 3.330 ;
+ SYMMETRY X Y R90 ;
+ SITE unithd ;
+ PIN vdd
+ DIRECTION INOUT ;
+ USE POWER ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000 3.090 5.760 3.570 ;
+ END
+ END vdd
+ PIN gnd
+ DIRECTION INOUT ;
+ USE GROUND ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000 -0.240 5.760 0.240 ;
+ END
+ END gnd
+ PIN Y
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 4.660 2.150 4.950 2.440 ;
+ RECT 4.730 0.690 4.870 2.150 ;
+ RECT 4.660 0.400 4.950 0.690 ;
+ END
+ END Y
+ PIN A
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 1.300 1.750 1.590 2.040 ;
+ RECT 1.370 1.090 1.510 1.750 ;
+ RECT 1.300 0.800 1.590 1.090 ;
+ END
+ END A
+ PIN B
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 2.740 1.750 3.030 2.040 ;
+ RECT 2.810 1.090 2.950 1.750 ;
+ RECT 2.740 0.800 3.030 1.090 ;
+ END
+ END B
+END AND2X1
+END LIBRARY
+
diff --git a/cells/lef/AND2X2.lef b/cells/lef/AND2X2.lef
new file mode 100644
index 0000000..5c4c9e3
--- /dev/null
+++ b/cells/lef/AND2X2.lef
@@ -0,0 +1,65 @@
+VERSION 5.7 ;
+ NOWIREEXTENSIONATPIN ON ;
+ DIVIDERCHAR "/" ;
+ BUSBITCHARS "[]" ;
+MACRO AND2X2
+ CLASS CORE ;
+ FOREIGN AND2X2 ;
+ ORIGIN 0.000 0.000 ;
+ SIZE 5.760 BY 3.330 ;
+ SYMMETRY X Y R90 ;
+ SITE unithd ;
+ PIN vdd
+ DIRECTION INOUT ;
+ USE POWER ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000 3.090 5.760 3.570 ;
+ END
+ END vdd
+ PIN gnd
+ DIRECTION INOUT ;
+ USE GROUND ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000 -0.240 5.760 0.240 ;
+ END
+ END gnd
+ PIN Y
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 4.660 2.150 4.950 2.440 ;
+ RECT 4.730 0.690 4.870 2.150 ;
+ RECT 4.660 0.400 4.950 0.690 ;
+ END
+ END Y
+ PIN B
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 2.740 1.750 3.030 2.040 ;
+ RECT 2.810 1.090 2.950 1.750 ;
+ RECT 2.740 0.800 3.030 1.090 ;
+ END
+ END B
+ PIN A
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 1.300 1.750 1.590 2.040 ;
+ RECT 1.370 1.090 1.510 1.750 ;
+ RECT 1.300 0.800 1.590 1.090 ;
+ END
+ END A
+END AND2X2
+END LIBRARY
+
diff --git a/cells/lef/AOI21X1.lef b/cells/lef/AOI21X1.lef
new file mode 100644
index 0000000..2a364e5
--- /dev/null
+++ b/cells/lef/AOI21X1.lef
@@ -0,0 +1,80 @@
+VERSION 5.7 ;
+ NOWIREEXTENSIONATPIN ON ;
+ DIVIDERCHAR "/" ;
+ BUSBITCHARS "[]" ;
+MACRO AOI21X1
+ CLASS CORE ;
+ FOREIGN AOI21X1 ;
+ ORIGIN 0.000 0.000 ;
+ SIZE 5.760 BY 3.330 ;
+ SYMMETRY X Y R90 ;
+ SITE unithd ;
+ PIN vdd
+ DIRECTION INOUT ;
+ USE POWER ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000 3.090 5.760 3.570 ;
+ END
+ END vdd
+ PIN gnd
+ DIRECTION INOUT ;
+ USE GROUND ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000 -0.240 5.760 0.240 ;
+ END
+ END gnd
+ PIN Y
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 4.660 2.150 4.950 2.440 ;
+ RECT 4.730 0.690 4.870 2.150 ;
+ RECT 0.820 0.610 1.110 0.690 ;
+ RECT 4.660 0.610 4.950 0.690 ;
+ RECT 0.820 0.470 4.950 0.610 ;
+ RECT 0.820 0.400 1.110 0.470 ;
+ RECT 4.660 0.400 4.950 0.470 ;
+ END
+ END Y
+ PIN B
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 1.300 1.750 1.590 2.040 ;
+ RECT 1.370 1.090 1.510 1.750 ;
+ RECT 1.300 0.800 1.590 1.090 ;
+ END
+ END B
+ PIN A
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 2.740 1.750 3.030 2.040 ;
+ RECT 2.810 1.090 2.950 1.750 ;
+ RECT 2.740 0.800 3.030 1.090 ;
+ END
+ END A
+ PIN C
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 4.180 1.750 4.470 2.040 ;
+ RECT 4.250 1.090 4.390 1.750 ;
+ RECT 4.180 0.800 4.470 1.090 ;
+ END
+ END C
+END AOI21X1
+END LIBRARY
+
diff --git a/cells/lef/AOI22X1.lef b/cells/lef/AOI22X1.lef
new file mode 100644
index 0000000..d37cec6
--- /dev/null
+++ b/cells/lef/AOI22X1.lef
@@ -0,0 +1,91 @@
+VERSION 5.7 ;
+ NOWIREEXTENSIONATPIN ON ;
+ DIVIDERCHAR "/" ;
+ BUSBITCHARS "[]" ;
+MACRO AOI22X1
+ CLASS CORE ;
+ FOREIGN AOI22X1 ;
+ ORIGIN 0.000 0.000 ;
+ SIZE 7.200 BY 3.330 ;
+ SYMMETRY X Y R90 ;
+ SITE unithd ;
+ PIN vdd
+ DIRECTION INOUT ;
+ USE POWER ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000 3.090 7.200 3.570 ;
+ END
+ END vdd
+ PIN gnd
+ DIRECTION INOUT ;
+ USE GROUND ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000 -0.240 7.200 0.240 ;
+ END
+ END gnd
+ PIN Y
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 1.780 2.150 2.310 2.440 ;
+ RECT 0.820 0.610 1.110 0.690 ;
+ RECT 2.090 0.610 2.230 2.150 ;
+ RECT 6.100 0.610 6.390 0.690 ;
+ RECT 0.820 0.470 6.390 0.610 ;
+ RECT 0.820 0.400 1.110 0.470 ;
+ RECT 6.100 0.400 6.390 0.470 ;
+ END
+ END Y
+ PIN B
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 5.620 1.750 5.910 2.040 ;
+ RECT 5.690 1.090 5.830 1.750 ;
+ RECT 5.620 0.800 5.910 1.090 ;
+ END
+ END B
+ PIN C
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 2.740 1.750 3.030 2.040 ;
+ RECT 2.810 1.090 2.950 1.750 ;
+ RECT 2.740 0.800 3.030 1.090 ;
+ END
+ END C
+ PIN A
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 4.180 1.750 4.470 2.040 ;
+ RECT 4.250 1.090 4.390 1.750 ;
+ RECT 4.180 0.800 4.470 1.090 ;
+ END
+ END A
+ PIN D
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 1.300 1.750 1.590 2.040 ;
+ RECT 1.370 1.090 1.510 1.750 ;
+ RECT 1.300 0.800 1.590 1.090 ;
+ END
+ END D
+END AOI22X1
+END LIBRARY
+
diff --git a/cells/lef/BUFX2.lef b/cells/lef/BUFX2.lef
new file mode 100644
index 0000000..70f5d75
--- /dev/null
+++ b/cells/lef/BUFX2.lef
@@ -0,0 +1,52 @@
+VERSION 5.7 ;
+ NOWIREEXTENSIONATPIN ON ;
+ DIVIDERCHAR "/" ;
+ BUSBITCHARS "[]" ;
+MACRO BUFX2
+ CLASS CORE ;
+ FOREIGN BUFX2 ;
+ ORIGIN 0.000 0.000 ;
+ SIZE 4.320 BY 3.330 ;
+ SYMMETRY X Y R90 ;
+ SITE unithd ;
+ PIN vdd
+ DIRECTION INOUT ;
+ USE POWER ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000 3.090 4.320 3.570 ;
+ END
+ END vdd
+ PIN gnd
+ DIRECTION INOUT ;
+ USE GROUND ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000 -0.240 4.320 0.240 ;
+ END
+ END gnd
+ PIN Y
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 3.220 2.150 3.510 2.440 ;
+ RECT 3.290 0.690 3.430 2.150 ;
+ RECT 3.220 0.400 3.510 0.690 ;
+ END
+ END Y
+ PIN A
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 1.300 0.800 1.590 1.090 ;
+ END
+ END A
+END BUFX2
+END LIBRARY
+
diff --git a/cells/lef/BUFX4.lef b/cells/lef/BUFX4.lef
new file mode 100644
index 0000000..c61076d
--- /dev/null
+++ b/cells/lef/BUFX4.lef
@@ -0,0 +1,58 @@
+VERSION 5.7 ;
+ NOWIREEXTENSIONATPIN ON ;
+ DIVIDERCHAR "/" ;
+ BUSBITCHARS "[]" ;
+MACRO BUFX4
+ CLASS CORE ;
+ FOREIGN BUFX4 ;
+ ORIGIN 0.000 0.000 ;
+ SIZE 5.760 BY 3.330 ;
+ SYMMETRY X Y R90 ;
+ SITE unithd ;
+ PIN vdd
+ DIRECTION INOUT ;
+ USE POWER ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000 3.090 5.760 3.570 ;
+ END
+ END vdd
+ PIN gnd
+ DIRECTION INOUT ;
+ USE GROUND ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000 -0.240 5.760 0.240 ;
+ END
+ END gnd
+ PIN Y
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 3.220 2.370 3.510 2.440 ;
+ RECT 3.700 2.370 3.990 2.440 ;
+ RECT 3.220 2.230 4.870 2.370 ;
+ RECT 3.220 2.150 3.510 2.230 ;
+ RECT 3.700 2.150 3.990 2.230 ;
+ RECT 3.700 0.610 3.990 0.690 ;
+ RECT 4.730 0.610 4.870 2.230 ;
+ RECT 3.700 0.470 4.870 0.610 ;
+ RECT 3.700 0.400 3.990 0.470 ;
+ END
+ END Y
+ PIN A
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 1.300 1.750 1.590 2.040 ;
+ END
+ END A
+END BUFX4
+END LIBRARY
+
diff --git a/cells/lef/CLKBUF1.lef b/cells/lef/CLKBUF1.lef
new file mode 100644
index 0000000..6ebaa05
--- /dev/null
+++ b/cells/lef/CLKBUF1.lef
@@ -0,0 +1,63 @@
+VERSION 5.7 ;
+ NOWIREEXTENSIONATPIN ON ;
+ DIVIDERCHAR "/" ;
+ BUSBITCHARS "[]" ;
+MACRO CLKBUF1
+ CLASS CORE ;
+ FOREIGN CLKBUF1 ;
+ ORIGIN 0.000 0.000 ;
+ SIZE 12.960 BY 3.330 ;
+ SYMMETRY X Y R90 ;
+ SITE unithd ;
+ PIN vdd
+ DIRECTION INOUT ;
+ USE POWER ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000 3.090 12.960 3.570 ;
+ END
+ END vdd
+ PIN gnd
+ DIRECTION INOUT ;
+ USE GROUND ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000 -0.240 12.960 0.240 ;
+ END
+ END gnd
+ PIN Y
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 10.660 2.370 11.190 2.440 ;
+ RECT 10.660 2.230 12.070 2.370 ;
+ RECT 10.660 2.150 11.190 2.230 ;
+ RECT 11.930 0.750 12.070 2.230 ;
+ RECT 10.900 0.610 11.190 0.690 ;
+ RECT 11.690 0.610 12.070 0.750 ;
+ RECT 10.900 0.470 11.830 0.610 ;
+ RECT 10.900 0.400 11.190 0.470 ;
+ END
+ END Y
+ PIN A
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 1.370 2.630 2.950 2.770 ;
+ RECT 1.370 2.040 1.510 2.630 ;
+ RECT 2.810 2.040 2.950 2.630 ;
+ RECT 1.300 1.750 1.590 2.040 ;
+ RECT 2.740 1.750 3.030 2.040 ;
+ RECT 1.370 1.090 1.510 1.750 ;
+ RECT 1.300 0.800 1.590 1.090 ;
+ END
+ END A
+END CLKBUF1
+END LIBRARY
+
diff --git a/cells/lef/HAX1.lef b/cells/lef/HAX1.lef
new file mode 100644
index 0000000..31e9d20
--- /dev/null
+++ b/cells/lef/HAX1.lef
@@ -0,0 +1,89 @@
+VERSION 5.7 ;
+ NOWIREEXTENSIONATPIN ON ;
+ DIVIDERCHAR "/" ;
+ BUSBITCHARS "[]" ;
+MACRO HAX1
+ CLASS CORE ;
+ FOREIGN HAX1 ;
+ ORIGIN 0.000 0.000 ;
+ SIZE 15.840 BY 3.330 ;
+ SYMMETRY X Y R90 ;
+ SITE unithd ;
+ PIN vdd
+ DIRECTION INOUT ;
+ USE POWER ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000 3.090 15.840 3.570 ;
+ END
+ END vdd
+ PIN gnd
+ DIRECTION INOUT ;
+ USE GROUND ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000 -0.240 15.840 0.240 ;
+ END
+ END gnd
+ PIN YS
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 14.740 2.150 15.030 2.440 ;
+ RECT 14.810 0.690 14.950 2.150 ;
+ RECT 14.740 0.400 15.030 0.690 ;
+ END
+ END YS
+ PIN YC
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 1.780 2.370 2.070 2.440 ;
+ RECT 0.890 2.230 2.070 2.370 ;
+ RECT 0.890 0.610 1.030 2.230 ;
+ RECT 1.780 2.150 2.070 2.230 ;
+ RECT 1.780 0.610 2.070 0.690 ;
+ RECT 0.890 0.470 2.070 0.610 ;
+ RECT 1.780 0.400 2.070 0.470 ;
+ END
+ END YC
+ PIN B
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 4.180 1.750 4.470 2.040 ;
+ RECT 4.250 1.090 4.390 1.750 ;
+ RECT 4.180 0.800 4.470 1.090 ;
+ RECT 4.250 0.610 4.390 0.800 ;
+ RECT 8.980 0.610 9.270 0.820 ;
+ RECT 4.250 0.530 9.270 0.610 ;
+ RECT 4.250 0.470 9.190 0.530 ;
+ END
+ END B
+ PIN A
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 5.620 1.750 5.910 2.040 ;
+ RECT 11.380 1.750 11.670 2.040 ;
+ RECT 5.690 1.150 5.830 1.750 ;
+ RECT 11.450 1.150 11.590 1.750 ;
+ RECT 5.690 1.090 11.590 1.150 ;
+ RECT 5.620 1.010 11.670 1.090 ;
+ RECT 5.620 0.800 5.910 1.010 ;
+ RECT 11.380 0.800 11.670 1.010 ;
+ END
+ END A
+END HAX1
+END LIBRARY
+
diff --git a/cells/lef/INV.lef b/cells/lef/INV.lef
new file mode 100644
index 0000000..0784f3a
--- /dev/null
+++ b/cells/lef/INV.lef
@@ -0,0 +1,54 @@
+VERSION 5.7 ;
+ NOWIREEXTENSIONATPIN ON ;
+ DIVIDERCHAR "/" ;
+ BUSBITCHARS "[]" ;
+MACRO INV
+ CLASS CORE ;
+ FOREIGN INV ;
+ ORIGIN 0.000 0.000 ;
+ SIZE 2.880 BY 3.330 ;
+ SYMMETRY X Y R90 ;
+ SITE unithd ;
+ PIN vdd
+ DIRECTION INOUT ;
+ USE POWER ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000 3.090 2.880 3.570 ;
+ END
+ END vdd
+ PIN gnd
+ DIRECTION INOUT ;
+ USE GROUND ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000 -0.240 2.880 0.240 ;
+ END
+ END gnd
+ PIN Y
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 0.580 2.150 0.870 2.440 ;
+ RECT 0.650 0.690 0.790 2.150 ;
+ RECT 0.580 0.400 0.870 0.690 ;
+ END
+ END Y
+ PIN A
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 1.300 1.750 1.590 2.040 ;
+ RECT 1.370 1.090 1.510 1.750 ;
+ RECT 1.300 0.800 1.590 1.090 ;
+ END
+ END A
+END INV
+END LIBRARY
+
diff --git a/cells/lef/INVX1.lef b/cells/lef/INVX1.lef
new file mode 100644
index 0000000..47b48fb
--- /dev/null
+++ b/cells/lef/INVX1.lef
@@ -0,0 +1,54 @@
+VERSION 5.7 ;
+ NOWIREEXTENSIONATPIN ON ;
+ DIVIDERCHAR "/" ;
+ BUSBITCHARS "[]" ;
+MACRO INVX1
+ CLASS CORE ;
+ FOREIGN INVX1 ;
+ ORIGIN 0.000 0.000 ;
+ SIZE 2.880 BY 3.330 ;
+ SYMMETRY X Y R90 ;
+ SITE unithd ;
+ PIN vdd
+ DIRECTION INOUT ;
+ USE POWER ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000 3.090 2.880 3.570 ;
+ END
+ END vdd
+ PIN gnd
+ DIRECTION INOUT ;
+ USE GROUND ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000 -0.240 2.880 0.240 ;
+ END
+ END gnd
+ PIN Y
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 1.780 2.150 2.070 2.440 ;
+ RECT 1.850 0.690 1.990 2.150 ;
+ RECT 1.780 0.400 2.070 0.690 ;
+ END
+ END Y
+ PIN A
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 1.300 1.750 1.590 2.040 ;
+ RECT 1.370 1.090 1.510 1.750 ;
+ RECT 1.300 0.800 1.590 1.090 ;
+ END
+ END A
+END INVX1
+END LIBRARY
+
diff --git a/cells/lef/INVX2.lef b/cells/lef/INVX2.lef
new file mode 100644
index 0000000..ef6aee3
--- /dev/null
+++ b/cells/lef/INVX2.lef
@@ -0,0 +1,54 @@
+VERSION 5.7 ;
+ NOWIREEXTENSIONATPIN ON ;
+ DIVIDERCHAR "/" ;
+ BUSBITCHARS "[]" ;
+MACRO INVX2
+ CLASS CORE ;
+ FOREIGN INVX2 ;
+ ORIGIN 0.000 0.000 ;
+ SIZE 2.880 BY 3.330 ;
+ SYMMETRY X Y R90 ;
+ SITE unithd ;
+ PIN vdd
+ DIRECTION INOUT ;
+ USE POWER ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000 3.090 2.880 3.570 ;
+ END
+ END vdd
+ PIN gnd
+ DIRECTION INOUT ;
+ USE GROUND ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000 -0.240 2.880 0.240 ;
+ END
+ END gnd
+ PIN Y
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 0.580 2.150 0.870 2.440 ;
+ RECT 0.650 0.690 0.790 2.150 ;
+ RECT 0.580 0.400 0.870 0.690 ;
+ END
+ END Y
+ PIN A
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 1.300 1.750 1.590 2.040 ;
+ RECT 1.370 1.090 1.510 1.750 ;
+ RECT 1.300 0.800 1.590 1.090 ;
+ END
+ END A
+END INVX2
+END LIBRARY
+
diff --git a/cells/lef/INVX4.lef b/cells/lef/INVX4.lef
new file mode 100644
index 0000000..8588178
--- /dev/null
+++ b/cells/lef/INVX4.lef
@@ -0,0 +1,66 @@
+VERSION 5.7 ;
+ NOWIREEXTENSIONATPIN ON ;
+ DIVIDERCHAR "/" ;
+ BUSBITCHARS "[]" ;
+MACRO INVX4
+ CLASS CORE ;
+ FOREIGN INVX4 ;
+ ORIGIN 0.000 0.000 ;
+ SIZE 4.320 BY 3.330 ;
+ SYMMETRY X Y R90 ;
+ SITE unithd ;
+ PIN vdd
+ DIRECTION INOUT ;
+ USE POWER ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000 3.090 4.320 3.570 ;
+ END
+ END vdd
+ PIN gnd
+ DIRECTION INOUT ;
+ USE GROUND ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000 -0.240 4.320 0.240 ;
+ END
+ END gnd
+ PIN Y
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 0.580 2.370 0.870 2.440 ;
+ RECT 3.220 2.370 3.510 2.440 ;
+ RECT 0.580 2.230 3.510 2.370 ;
+ RECT 0.580 2.150 0.870 2.230 ;
+ RECT 3.220 2.150 3.510 2.230 ;
+ RECT 0.650 0.690 0.790 2.150 ;
+ RECT 3.290 0.690 3.430 2.150 ;
+ RECT 0.580 0.400 0.870 0.690 ;
+ RECT 3.220 0.400 3.510 0.690 ;
+ END
+ END Y
+ PIN A
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 1.300 1.960 1.590 2.040 ;
+ RECT 2.740 1.960 3.030 2.040 ;
+ RECT 1.300 1.820 3.030 1.960 ;
+ RECT 1.300 1.750 1.590 1.820 ;
+ RECT 2.740 1.750 3.030 1.820 ;
+ RECT 1.370 1.090 1.510 1.750 ;
+ RECT 2.810 1.090 2.950 1.750 ;
+ RECT 1.300 0.800 1.590 1.090 ;
+ RECT 2.740 0.800 3.030 1.090 ;
+ END
+ END A
+END INVX4
+END LIBRARY
+
diff --git a/cells/lef/INVX8.lef b/cells/lef/INVX8.lef
new file mode 100644
index 0000000..e3c5d0d
--- /dev/null
+++ b/cells/lef/INVX8.lef
@@ -0,0 +1,82 @@
+VERSION 5.7 ;
+ NOWIREEXTENSIONATPIN ON ;
+ DIVIDERCHAR "/" ;
+ BUSBITCHARS "[]" ;
+MACRO INVX8
+ CLASS CORE ;
+ FOREIGN INVX8 ;
+ ORIGIN 0.000 0.000 ;
+ SIZE 7.200 BY 3.330 ;
+ SYMMETRY X Y R90 ;
+ SITE unithd ;
+ PIN vdd
+ DIRECTION INOUT ;
+ USE POWER ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000 3.090 7.200 3.570 ;
+ END
+ END vdd
+ PIN gnd
+ DIRECTION INOUT ;
+ USE GROUND ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000 -0.240 7.200 0.240 ;
+ END
+ END gnd
+ PIN Y
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 0.820 2.370 1.110 2.440 ;
+ RECT 3.220 2.370 3.510 2.440 ;
+ RECT 3.700 2.370 3.990 2.440 ;
+ RECT 6.100 2.370 6.390 2.440 ;
+ RECT 0.820 2.230 6.390 2.370 ;
+ RECT 0.820 2.150 1.110 2.230 ;
+ RECT 3.220 2.150 3.510 2.230 ;
+ RECT 3.700 2.150 3.990 2.230 ;
+ RECT 6.100 2.150 6.390 2.230 ;
+ RECT 0.890 0.690 1.030 2.150 ;
+ RECT 6.170 0.690 6.310 2.150 ;
+ RECT 0.820 0.610 1.110 0.690 ;
+ RECT 3.220 0.610 3.750 0.690 ;
+ RECT 0.820 0.470 3.750 0.610 ;
+ RECT 0.820 0.400 1.110 0.470 ;
+ RECT 3.220 0.400 3.750 0.470 ;
+ RECT 6.100 0.400 6.390 0.690 ;
+ END
+ END Y
+ PIN A
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 1.300 1.750 1.590 2.040 ;
+ RECT 2.740 1.750 3.030 2.040 ;
+ RECT 4.180 1.750 4.470 2.040 ;
+ RECT 5.620 1.750 5.910 2.040 ;
+ RECT 1.370 1.090 1.510 1.750 ;
+ RECT 2.810 1.090 2.950 1.750 ;
+ RECT 4.250 1.090 4.390 1.750 ;
+ RECT 5.690 1.090 5.830 1.750 ;
+ RECT 1.300 1.020 1.590 1.090 ;
+ RECT 2.740 1.020 3.030 1.090 ;
+ RECT 4.180 1.020 4.470 1.090 ;
+ RECT 5.620 1.020 5.910 1.090 ;
+ RECT 1.300 0.880 5.910 1.020 ;
+ RECT 1.300 0.800 1.590 0.880 ;
+ RECT 2.740 0.800 3.030 0.880 ;
+ RECT 4.180 0.800 4.470 0.880 ;
+ RECT 5.620 0.800 5.910 0.880 ;
+ END
+ END A
+END INVX8
+END LIBRARY
+
diff --git a/cells/lef/LATCH.lef b/cells/lef/LATCH.lef
new file mode 100644
index 0000000..55afbba
--- /dev/null
+++ b/cells/lef/LATCH.lef
@@ -0,0 +1,69 @@
+VERSION 5.7 ;
+ NOWIREEXTENSIONATPIN ON ;
+ DIVIDERCHAR "/" ;
+ BUSBITCHARS "[]" ;
+MACRO LATCH
+ CLASS CORE ;
+ FOREIGN LATCH ;
+ ORIGIN 0.000 0.000 ;
+ SIZE 10.080 BY 3.330 ;
+ SYMMETRY X Y R90 ;
+ SITE unithd ;
+ PIN vdd
+ DIRECTION INOUT ;
+ USE POWER ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000 3.090 10.080 3.570 ;
+ END
+ END vdd
+ PIN gnd
+ DIRECTION INOUT ;
+ USE GROUND ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000 -0.240 10.080 0.240 ;
+ END
+ END gnd
+ PIN Q
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 8.980 2.370 9.270 2.440 ;
+ RECT 7.130 2.230 9.270 2.370 ;
+ RECT 7.130 2.040 7.270 2.230 ;
+ RECT 8.980 2.150 9.270 2.230 ;
+ RECT 7.060 1.750 7.350 2.040 ;
+ RECT 9.050 0.690 9.190 2.150 ;
+ RECT 8.980 0.400 9.270 0.690 ;
+ END
+ END Q
+ PIN D
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 2.740 1.210 3.030 1.500 ;
+ END
+ END D
+ PIN CLK
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 1.300 1.020 1.590 1.090 ;
+ RECT 4.180 1.020 4.470 1.090 ;
+ RECT 1.300 0.880 4.470 1.020 ;
+ RECT 1.300 0.800 1.590 0.880 ;
+ RECT 4.180 0.800 4.470 0.880 ;
+ END
+ END CLK
+END LATCH
+END LIBRARY
+
diff --git a/cells/lef/fixup.pl b/cells/lef/fixup.pl
new file mode 100644
index 0000000..ae9f1be
--- /dev/null
+++ b/cells/lef/fixup.pl
@@ -0,0 +1,63 @@
+#!/usr/bin/perl -w
+
+foreach my $lef (<orig/*.lef>)
+{
+ $lef=~s/^orig\///;
+ my $mag="../mag/$lef"; $mag=~s/\.lef$/\.mag/;
+ my $cell=$lef; $cell=~s/\.lef//;
+ print "$lef\n";
+ open LEFIN,"<orig/$lef";
+ open LEFOUT,">$lef";
+ our $pin="";
+ while(<LEFIN>)
+ {
+ $pin=$1 if(m/PIN (\w+)/);
+ s/SYMMETRY X Y R90/SITE unithd/;
+ s/SITE CORE/SYMMETRY X Y R90/;
+ #s/SITE unithd.*//;
+ s/metal2/met1/;
+ s/VDD/vdd/;
+ s/GND/gnd/;
+ s/USE SIGNAL/USE POWER/ if($pin eq "VDD");
+ s/USE SIGNAL/USE GROUND/ if($pin eq "GND");
+
+ print LEFOUT $_;
+ #print $_;
+ if(m/FOREIGN/)
+ {
+ if(open(MAG,"<$mag"))
+ {
+ while(<MAG>)
+ {
+ if(m/rect 0 0 (\d+) (\d+)/)
+ {
+ my $h=$1;
+ my $w=$2;
+ my $factor=0.01;
+ print "$lef -> ".($1*$factor)." ".($2*$factor)."\n";
+ print LEFOUT " SIZE ".($1*$factor)." BY ".($2*$factor)." ;\n";
+ }
+ if(m/string FIXED_BBOX 0 0 (\d+) (\d+)/)
+ {
+ my $h=$1;
+ my $w=$2;
+ my $factor=0.01;
+ print "$lef -> ".($1*$factor)." ".($2*$factor)."\n";
+ print LEFOUT " SIZE ".($1*$factor)." BY ".($2*$factor)." ;\n";
+ }
+
+ }
+ close MAG;
+ }
+ }
+ }
+ close LEFOUT;
+ close LEFIN;
+
+ open MAGIC,"|magic -dnull -noconsole -T sky130A";
+ print MAGIC "lef read $lef\n";
+ print MAGIC "load $cell\n";
+ print MAGIC "lef write $lef\n";
+ print MAGIC "quit\n";
+ close MAGIC;
+}
diff --git a/cells/lef/orig/AND2X1.lef b/cells/lef/orig/AND2X1.lef
new file mode 100644
index 0000000..388c359
--- /dev/null
+++ b/cells/lef/orig/AND2X1.lef
@@ -0,0 +1,69 @@
+MACRO AND2X1
+ CLASS CORE ;
+ FOREIGN AND2X1 0 0 ;
+ ORIGIN 0 0 ;
+ SYMMETRY X Y R90 ;
+ SITE CORE ;
+ PIN VDD
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 0.00000000 3.09000000 5.76000000 3.57000000 ;
+ END
+ END VDD
+
+ PIN GND
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 0.00000000 -0.24000000 5.76000000 0.24000000 ;
+ END
+ END GND
+
+ PIN Y
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 4.65500000 0.39500000 4.94500000 0.68500000 ;
+ RECT 4.73000000 0.68500000 4.87000000 2.15000000 ;
+ RECT 4.65500000 2.15000000 4.94500000 2.44000000 ;
+ END
+ END Y
+
+ PIN A
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 1.29500000 0.80000000 1.58500000 1.09000000 ;
+ RECT 1.37000000 1.09000000 1.51000000 1.74500000 ;
+ RECT 1.29500000 1.74500000 1.58500000 2.03500000 ;
+ END
+ END A
+
+ PIN B
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 2.73500000 0.80000000 3.02500000 1.09000000 ;
+ RECT 2.81000000 1.09000000 2.95000000 1.74500000 ;
+ RECT 2.73500000 1.74500000 3.02500000 2.03500000 ;
+ END
+ END B
+
+
+END AND2X1
diff --git a/cells/lef/orig/AND2X2.lef b/cells/lef/orig/AND2X2.lef
new file mode 100644
index 0000000..50a86fc
--- /dev/null
+++ b/cells/lef/orig/AND2X2.lef
@@ -0,0 +1,69 @@
+MACRO AND2X2
+ CLASS CORE ;
+ FOREIGN AND2X2 0 0 ;
+ ORIGIN 0 0 ;
+ SYMMETRY X Y R90 ;
+ SITE CORE ;
+ PIN VDD
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 0.00000000 3.09000000 5.76000000 3.57000000 ;
+ END
+ END VDD
+
+ PIN GND
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 0.00000000 -0.24000000 5.76000000 0.24000000 ;
+ END
+ END GND
+
+ PIN Y
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 4.65500000 0.39500000 4.94500000 0.68500000 ;
+ RECT 4.73000000 0.68500000 4.87000000 2.15000000 ;
+ RECT 4.65500000 2.15000000 4.94500000 2.44000000 ;
+ END
+ END Y
+
+ PIN B
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 2.73500000 0.80000000 3.02500000 1.09000000 ;
+ RECT 2.81000000 1.09000000 2.95000000 1.74500000 ;
+ RECT 2.73500000 1.74500000 3.02500000 2.03500000 ;
+ END
+ END B
+
+ PIN A
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 1.29500000 0.80000000 1.58500000 1.09000000 ;
+ RECT 1.37000000 1.09000000 1.51000000 1.74500000 ;
+ RECT 1.29500000 1.74500000 1.58500000 2.03500000 ;
+ END
+ END A
+
+
+END AND2X2
diff --git a/cells/lef/orig/AOI21X1.lef b/cells/lef/orig/AOI21X1.lef
new file mode 100644
index 0000000..48b73d2
--- /dev/null
+++ b/cells/lef/orig/AOI21X1.lef
@@ -0,0 +1,86 @@
+MACRO AOI21X1
+ CLASS CORE ;
+ FOREIGN AOI21X1 0 0 ;
+ ORIGIN 0 0 ;
+ SYMMETRY X Y R90 ;
+ SITE CORE ;
+ PIN VDD
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 0.00000000 3.09000000 5.76000000 3.57000000 ;
+ END
+ END VDD
+
+ PIN GND
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 0.00000000 -0.24000000 5.76000000 0.24000000 ;
+ END
+ END GND
+
+ PIN Y
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 0.81500000 0.39500000 1.10500000 0.47000000 ;
+ RECT 4.65500000 0.39500000 4.94500000 0.47000000 ;
+ RECT 0.81500000 0.47000000 4.94500000 0.61000000 ;
+ RECT 0.81500000 0.61000000 1.10500000 0.68500000 ;
+ RECT 4.65500000 0.61000000 4.94500000 0.68500000 ;
+ RECT 4.73000000 0.68500000 4.87000000 2.15000000 ;
+ RECT 4.65500000 2.15000000 4.94500000 2.44000000 ;
+ END
+ END Y
+
+ PIN B
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 1.29500000 0.80000000 1.58500000 1.09000000 ;
+ RECT 1.37000000 1.09000000 1.51000000 1.74500000 ;
+ RECT 1.29500000 1.74500000 1.58500000 2.03500000 ;
+ END
+ END B
+
+ PIN A
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 2.73500000 0.80000000 3.02500000 1.09000000 ;
+ RECT 2.81000000 1.09000000 2.95000000 1.74500000 ;
+ RECT 2.73500000 1.74500000 3.02500000 2.03500000 ;
+ END
+ END A
+
+ PIN C
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 4.17500000 0.80000000 4.46500000 1.09000000 ;
+ RECT 4.25000000 1.09000000 4.39000000 1.74500000 ;
+ RECT 4.17500000 1.74500000 4.46500000 2.03500000 ;
+ END
+ END C
+
+
+END AOI21X1
diff --git a/cells/lef/orig/AOI22X1.lef b/cells/lef/orig/AOI22X1.lef
new file mode 100644
index 0000000..a357ec9
--- /dev/null
+++ b/cells/lef/orig/AOI22X1.lef
@@ -0,0 +1,99 @@
+MACRO AOI22X1
+ CLASS CORE ;
+ FOREIGN AOI22X1 0 0 ;
+ ORIGIN 0 0 ;
+ SYMMETRY X Y R90 ;
+ SITE CORE ;
+ PIN VDD
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 0.00000000 3.09000000 7.20000000 3.57000000 ;
+ END
+ END VDD
+
+ PIN GND
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 0.00000000 -0.24000000 7.20000000 0.24000000 ;
+ END
+ END GND
+
+ PIN Y
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 0.81500000 0.39500000 1.10500000 0.47000000 ;
+ RECT 6.09500000 0.39500000 6.38500000 0.47000000 ;
+ RECT 0.81500000 0.47000000 6.38500000 0.61000000 ;
+ RECT 0.81500000 0.61000000 1.10500000 0.68500000 ;
+ RECT 6.09500000 0.61000000 6.38500000 0.68500000 ;
+ RECT 2.09000000 0.61000000 2.23000000 2.15000000 ;
+ RECT 1.77500000 2.15000000 2.30500000 2.44000000 ;
+ END
+ END Y
+
+ PIN B
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 5.61500000 0.80000000 5.90500000 1.09000000 ;
+ RECT 5.69000000 1.09000000 5.83000000 1.74500000 ;
+ RECT 5.61500000 1.74500000 5.90500000 2.03500000 ;
+ END
+ END B
+
+ PIN C
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 2.73500000 0.80000000 3.02500000 1.09000000 ;
+ RECT 2.81000000 1.09000000 2.95000000 1.74500000 ;
+ RECT 2.73500000 1.74500000 3.02500000 2.03500000 ;
+ END
+ END C
+
+ PIN A
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 4.17500000 0.80000000 4.46500000 1.09000000 ;
+ RECT 4.25000000 1.09000000 4.39000000 1.74500000 ;
+ RECT 4.17500000 1.74500000 4.46500000 2.03500000 ;
+ END
+ END A
+
+ PIN D
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 1.29500000 0.80000000 1.58500000 1.09000000 ;
+ RECT 1.37000000 1.09000000 1.51000000 1.74500000 ;
+ RECT 1.29500000 1.74500000 1.58500000 2.03500000 ;
+ END
+ END D
+
+
+END AOI22X1
diff --git a/cells/lef/orig/BUFX2.lef b/cells/lef/orig/BUFX2.lef
new file mode 100644
index 0000000..14c37e0
--- /dev/null
+++ b/cells/lef/orig/BUFX2.lef
@@ -0,0 +1,54 @@
+MACRO BUFX2
+ CLASS CORE ;
+ FOREIGN BUFX2 0 0 ;
+ ORIGIN 0 0 ;
+ SYMMETRY X Y R90 ;
+ SITE CORE ;
+ PIN VDD
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 0.00000000 3.09000000 4.32000000 3.57000000 ;
+ END
+ END VDD
+
+ PIN GND
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 0.00000000 -0.24000000 4.32000000 0.24000000 ;
+ END
+ END GND
+
+ PIN Y
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 3.21500000 0.39500000 3.50500000 0.68500000 ;
+ RECT 3.29000000 0.68500000 3.43000000 2.15000000 ;
+ RECT 3.21500000 2.15000000 3.50500000 2.44000000 ;
+ END
+ END Y
+
+ PIN A
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 1.29500000 0.80000000 1.58500000 1.09000000 ;
+ END
+ END A
+
+
+END BUFX2
diff --git a/cells/lef/orig/BUFX4.lef b/cells/lef/orig/BUFX4.lef
new file mode 100644
index 0000000..2080399
--- /dev/null
+++ b/cells/lef/orig/BUFX4.lef
@@ -0,0 +1,60 @@
+MACRO BUFX4
+ CLASS CORE ;
+ FOREIGN BUFX4 0 0 ;
+ ORIGIN 0 0 ;
+ SYMMETRY X Y R90 ;
+ SITE CORE ;
+ PIN VDD
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 0.00000000 3.09000000 5.76000000 3.57000000 ;
+ END
+ END VDD
+
+ PIN GND
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 0.00000000 -0.24000000 5.76000000 0.24000000 ;
+ END
+ END GND
+
+ PIN Y
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 3.69500000 0.39500000 3.98500000 0.47000000 ;
+ RECT 3.69500000 0.47000000 4.87000000 0.61000000 ;
+ RECT 3.69500000 0.61000000 3.98500000 0.68500000 ;
+ RECT 3.21500000 2.15000000 3.50500000 2.22500000 ;
+ RECT 3.69500000 2.15000000 3.98500000 2.22500000 ;
+ RECT 4.73000000 0.61000000 4.87000000 2.22500000 ;
+ RECT 3.21500000 2.22500000 4.87000000 2.36500000 ;
+ RECT 3.21500000 2.36500000 3.50500000 2.44000000 ;
+ RECT 3.69500000 2.36500000 3.98500000 2.44000000 ;
+ END
+ END Y
+
+ PIN A
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 1.29500000 1.74500000 1.58500000 2.03500000 ;
+ END
+ END A
+
+
+END BUFX4
diff --git a/cells/lef/orig/CLKBUF1.lef b/cells/lef/orig/CLKBUF1.lef
new file mode 100644
index 0000000..7e92c30
--- /dev/null
+++ b/cells/lef/orig/CLKBUF1.lef
@@ -0,0 +1,66 @@
+MACRO CLKBUF1
+ CLASS CORE ;
+ FOREIGN CLKBUF1 0 0 ;
+ ORIGIN 0 0 ;
+ SYMMETRY X Y R90 ;
+ SITE CORE ;
+ PIN VDD
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 0.00000000 3.09000000 12.96000000 3.57000000 ;
+ END
+ END VDD
+
+ PIN GND
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 0.00000000 -0.24000000 12.96000000 0.24000000 ;
+ END
+ END GND
+
+ PIN Y
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 10.89500000 0.39500000 11.18500000 0.47000000 ;
+ RECT 10.89500000 0.47000000 11.83000000 0.60500000 ;
+ RECT 10.89500000 0.60500000 12.07000000 0.61000000 ;
+ RECT 10.89500000 0.61000000 11.18500000 0.68500000 ;
+ RECT 11.69000000 0.61000000 12.07000000 0.74500000 ;
+ RECT 10.65500000 2.15000000 11.18500000 2.22500000 ;
+ RECT 11.93000000 0.74500000 12.07000000 2.22500000 ;
+ RECT 10.65500000 2.22500000 12.07000000 2.36500000 ;
+ RECT 10.65500000 2.36500000 11.18500000 2.44000000 ;
+ END
+ END Y
+
+ PIN A
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 1.29500000 0.80000000 1.58500000 1.09000000 ;
+ RECT 1.37000000 1.09000000 1.51000000 1.74500000 ;
+ RECT 1.29500000 1.74500000 1.58500000 2.03500000 ;
+ RECT 2.73500000 1.74500000 3.02500000 2.03500000 ;
+ RECT 1.37000000 2.03500000 1.51000000 2.63000000 ;
+ RECT 2.81000000 2.03500000 2.95000000 2.63000000 ;
+ RECT 1.37000000 2.63000000 2.95000000 2.77000000 ;
+ END
+ END A
+
+
+END CLKBUF1
diff --git a/cells/lef/orig/HAX1.lef b/cells/lef/orig/HAX1.lef
new file mode 100644
index 0000000..19db246
--- /dev/null
+++ b/cells/lef/orig/HAX1.lef
@@ -0,0 +1,95 @@
+MACRO HAX1
+ CLASS CORE ;
+ FOREIGN HAX1 0 0 ;
+ ORIGIN 0 0 ;
+ SYMMETRY X Y R90 ;
+ SITE CORE ;
+ PIN VDD
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 0.00000000 3.09000000 15.84000000 3.57000000 ;
+ END
+ END VDD
+
+ PIN GND
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 0.00000000 -0.24000000 15.84000000 0.24000000 ;
+ END
+ END GND
+
+ PIN YS
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 14.73500000 0.39500000 15.02500000 0.68500000 ;
+ RECT 14.81000000 0.68500000 14.95000000 2.15000000 ;
+ RECT 14.73500000 2.15000000 15.02500000 2.44000000 ;
+ END
+ END YS
+
+ PIN YC
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 1.77500000 0.39500000 2.06500000 0.47000000 ;
+ RECT 0.89000000 0.47000000 2.06500000 0.61000000 ;
+ RECT 1.77500000 0.61000000 2.06500000 0.68500000 ;
+ RECT 0.89000000 0.61000000 1.03000000 2.22500000 ;
+ RECT 1.77500000 2.15000000 2.06500000 2.22500000 ;
+ RECT 0.89000000 2.22500000 2.06500000 2.36500000 ;
+ RECT 1.77500000 2.36500000 2.06500000 2.44000000 ;
+ END
+ END YC
+
+ PIN B
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 4.25000000 0.47000000 9.19000000 0.53000000 ;
+ RECT 4.25000000 0.53000000 9.26500000 0.61000000 ;
+ RECT 4.25000000 0.61000000 4.39000000 0.80000000 ;
+ RECT 8.97500000 0.61000000 9.26500000 0.82000000 ;
+ RECT 4.17500000 0.80000000 4.46500000 1.09000000 ;
+ RECT 4.25000000 1.09000000 4.39000000 1.74500000 ;
+ RECT 4.17500000 1.74500000 4.46500000 2.03500000 ;
+ END
+ END B
+
+ PIN A
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 5.61500000 0.80000000 5.90500000 1.01000000 ;
+ RECT 11.37500000 0.80000000 11.66500000 1.01000000 ;
+ RECT 5.61500000 1.01000000 11.66500000 1.09000000 ;
+ RECT 5.69000000 1.09000000 11.59000000 1.15000000 ;
+ RECT 5.69000000 1.15000000 5.83000000 1.74500000 ;
+ RECT 11.45000000 1.15000000 11.59000000 1.74500000 ;
+ RECT 5.61500000 1.74500000 5.90500000 2.03500000 ;
+ RECT 11.37500000 1.74500000 11.66500000 2.03500000 ;
+ END
+ END A
+
+
+END HAX1
diff --git a/cells/lef/orig/INV.lef b/cells/lef/orig/INV.lef
new file mode 100644
index 0000000..d1049fe
--- /dev/null
+++ b/cells/lef/orig/INV.lef
@@ -0,0 +1,56 @@
+MACRO INV
+ CLASS CORE ;
+ FOREIGN INV 0 0 ;
+ ORIGIN 0 0 ;
+ SYMMETRY X Y R90 ;
+ SITE CORE ;
+ PIN VDD
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 0.00000000 3.09000000 2.88000000 3.57000000 ;
+ END
+ END VDD
+
+ PIN GND
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 0.00000000 -0.24000000 2.88000000 0.24000000 ;
+ END
+ END GND
+
+ PIN Y
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 0.57500000 0.39500000 0.86500000 0.68500000 ;
+ RECT 0.65000000 0.68500000 0.79000000 2.15000000 ;
+ RECT 0.57500000 2.15000000 0.86500000 2.44000000 ;
+ END
+ END Y
+
+ PIN A
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 1.29500000 0.80000000 1.58500000 1.09000000 ;
+ RECT 1.37000000 1.09000000 1.51000000 1.74500000 ;
+ RECT 1.29500000 1.74500000 1.58500000 2.03500000 ;
+ END
+ END A
+
+
+END INV
diff --git a/cells/lef/orig/INVX1.lef b/cells/lef/orig/INVX1.lef
new file mode 100644
index 0000000..1088e65
--- /dev/null
+++ b/cells/lef/orig/INVX1.lef
@@ -0,0 +1,56 @@
+MACRO INVX1
+ CLASS CORE ;
+ FOREIGN INVX1 0 0 ;
+ ORIGIN 0 0 ;
+ SYMMETRY X Y R90 ;
+ SITE CORE ;
+ PIN VDD
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 0.00000000 3.09000000 2.88000000 3.57000000 ;
+ END
+ END VDD
+
+ PIN GND
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 0.00000000 -0.24000000 2.88000000 0.24000000 ;
+ END
+ END GND
+
+ PIN Y
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 1.77500000 0.39500000 2.06500000 0.68500000 ;
+ RECT 1.85000000 0.68500000 1.99000000 2.15000000 ;
+ RECT 1.77500000 2.15000000 2.06500000 2.44000000 ;
+ END
+ END Y
+
+ PIN A
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 1.29500000 0.80000000 1.58500000 1.09000000 ;
+ RECT 1.37000000 1.09000000 1.51000000 1.74500000 ;
+ RECT 1.29500000 1.74500000 1.58500000 2.03500000 ;
+ END
+ END A
+
+
+END INVX1
diff --git a/cells/lef/orig/INVX2.lef b/cells/lef/orig/INVX2.lef
new file mode 100644
index 0000000..52223d1
--- /dev/null
+++ b/cells/lef/orig/INVX2.lef
@@ -0,0 +1,56 @@
+MACRO INVX2
+ CLASS CORE ;
+ FOREIGN INVX2 0 0 ;
+ ORIGIN 0 0 ;
+ SYMMETRY X Y R90 ;
+ SITE CORE ;
+ PIN VDD
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 0.00000000 3.09000000 2.88000000 3.57000000 ;
+ END
+ END VDD
+
+ PIN GND
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 0.00000000 -0.24000000 2.88000000 0.24000000 ;
+ END
+ END GND
+
+ PIN Y
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 0.57500000 0.39500000 0.86500000 0.68500000 ;
+ RECT 0.65000000 0.68500000 0.79000000 2.15000000 ;
+ RECT 0.57500000 2.15000000 0.86500000 2.44000000 ;
+ END
+ END Y
+
+ PIN A
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 1.29500000 0.80000000 1.58500000 1.09000000 ;
+ RECT 1.37000000 1.09000000 1.51000000 1.74500000 ;
+ RECT 1.29500000 1.74500000 1.58500000 2.03500000 ;
+ END
+ END A
+
+
+END INVX2
diff --git a/cells/lef/orig/INVX4.lef b/cells/lef/orig/INVX4.lef
new file mode 100644
index 0000000..d1077c8
--- /dev/null
+++ b/cells/lef/orig/INVX4.lef
@@ -0,0 +1,68 @@
+MACRO INVX4
+ CLASS CORE ;
+ FOREIGN INVX4 0 0 ;
+ ORIGIN 0 0 ;
+ SYMMETRY X Y R90 ;
+ SITE CORE ;
+ PIN VDD
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 0.00000000 3.09000000 4.32000000 3.57000000 ;
+ END
+ END VDD
+
+ PIN GND
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 0.00000000 -0.24000000 4.32000000 0.24000000 ;
+ END
+ END GND
+
+ PIN Y
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 0.57500000 0.39500000 0.86500000 0.68500000 ;
+ RECT 3.21500000 0.39500000 3.50500000 0.68500000 ;
+ RECT 0.65000000 0.68500000 0.79000000 2.15000000 ;
+ RECT 3.29000000 0.68500000 3.43000000 2.15000000 ;
+ RECT 0.57500000 2.15000000 0.86500000 2.22500000 ;
+ RECT 3.21500000 2.15000000 3.50500000 2.22500000 ;
+ RECT 0.57500000 2.22500000 3.50500000 2.36500000 ;
+ RECT 0.57500000 2.36500000 0.86500000 2.44000000 ;
+ RECT 3.21500000 2.36500000 3.50500000 2.44000000 ;
+ END
+ END Y
+
+ PIN A
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 1.29500000 0.80000000 1.58500000 1.09000000 ;
+ RECT 2.73500000 0.80000000 3.02500000 1.09000000 ;
+ RECT 1.37000000 1.09000000 1.51000000 1.74500000 ;
+ RECT 2.81000000 1.09000000 2.95000000 1.74500000 ;
+ RECT 1.29500000 1.74500000 1.58500000 1.82000000 ;
+ RECT 2.73500000 1.74500000 3.02500000 1.82000000 ;
+ RECT 1.29500000 1.82000000 3.02500000 1.96000000 ;
+ RECT 1.29500000 1.96000000 1.58500000 2.03500000 ;
+ RECT 2.73500000 1.96000000 3.02500000 2.03500000 ;
+ END
+ END A
+
+
+END INVX4
diff --git a/cells/lef/orig/INVX8.lef b/cells/lef/orig/INVX8.lef
new file mode 100644
index 0000000..98c78c1
--- /dev/null
+++ b/cells/lef/orig/INVX8.lef
@@ -0,0 +1,84 @@
+MACRO INVX8
+ CLASS CORE ;
+ FOREIGN INVX8 0 0 ;
+ ORIGIN 0 0 ;
+ SYMMETRY X Y R90 ;
+ SITE CORE ;
+ PIN VDD
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 0.00000000 3.09000000 7.20000000 3.57000000 ;
+ END
+ END VDD
+
+ PIN GND
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 0.00000000 -0.24000000 7.20000000 0.24000000 ;
+ END
+ END GND
+
+ PIN Y
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 0.81500000 0.39500000 1.10500000 0.47000000 ;
+ RECT 3.21500000 0.39500000 3.74500000 0.47000000 ;
+ RECT 0.81500000 0.47000000 3.74500000 0.61000000 ;
+ RECT 0.81500000 0.61000000 1.10500000 0.68500000 ;
+ RECT 3.21500000 0.61000000 3.74500000 0.68500000 ;
+ RECT 6.09500000 0.39500000 6.38500000 0.68500000 ;
+ RECT 0.89000000 0.68500000 1.03000000 2.15000000 ;
+ RECT 6.17000000 0.68500000 6.31000000 2.15000000 ;
+ RECT 0.81500000 2.15000000 1.10500000 2.22500000 ;
+ RECT 3.21500000 2.15000000 3.50500000 2.22500000 ;
+ RECT 3.69500000 2.15000000 3.98500000 2.22500000 ;
+ RECT 6.09500000 2.15000000 6.38500000 2.22500000 ;
+ RECT 0.81500000 2.22500000 6.38500000 2.36500000 ;
+ RECT 0.81500000 2.36500000 1.10500000 2.44000000 ;
+ RECT 3.21500000 2.36500000 3.50500000 2.44000000 ;
+ RECT 3.69500000 2.36500000 3.98500000 2.44000000 ;
+ RECT 6.09500000 2.36500000 6.38500000 2.44000000 ;
+ END
+ END Y
+
+ PIN A
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 1.29500000 0.80000000 1.58500000 0.87500000 ;
+ RECT 2.73500000 0.80000000 3.02500000 0.87500000 ;
+ RECT 4.17500000 0.80000000 4.46500000 0.87500000 ;
+ RECT 5.61500000 0.80000000 5.90500000 0.87500000 ;
+ RECT 1.29500000 0.87500000 5.90500000 1.01500000 ;
+ RECT 1.29500000 1.01500000 1.58500000 1.09000000 ;
+ RECT 2.73500000 1.01500000 3.02500000 1.09000000 ;
+ RECT 4.17500000 1.01500000 4.46500000 1.09000000 ;
+ RECT 5.61500000 1.01500000 5.90500000 1.09000000 ;
+ RECT 1.37000000 1.09000000 1.51000000 1.74500000 ;
+ RECT 2.81000000 1.09000000 2.95000000 1.74500000 ;
+ RECT 4.25000000 1.09000000 4.39000000 1.74500000 ;
+ RECT 5.69000000 1.09000000 5.83000000 1.74500000 ;
+ RECT 1.29500000 1.74500000 1.58500000 2.03500000 ;
+ RECT 2.73500000 1.74500000 3.02500000 2.03500000 ;
+ RECT 4.17500000 1.74500000 4.46500000 2.03500000 ;
+ RECT 5.61500000 1.74500000 5.90500000 2.03500000 ;
+ END
+ END A
+
+
+END INVX8
diff --git a/cells/lef/orig/LATCH.lef b/cells/lef/orig/LATCH.lef
new file mode 100644
index 0000000..a278e3d
--- /dev/null
+++ b/cells/lef/orig/LATCH.lef
@@ -0,0 +1,73 @@
+MACRO LATCH
+ CLASS CORE ;
+ FOREIGN LATCH 0 0 ;
+ ORIGIN 0 0 ;
+ SYMMETRY X Y R90 ;
+ SITE CORE ;
+ PIN VDD
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 0.00000000 3.09000000 10.08000000 3.57000000 ;
+ END
+ END VDD
+
+ PIN GND
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 0.00000000 -0.24000000 10.08000000 0.24000000 ;
+ END
+ END GND
+
+ PIN Q
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 8.97500000 0.39500000 9.26500000 0.68500000 ;
+ RECT 7.05500000 1.74500000 7.34500000 2.03500000 ;
+ RECT 9.05000000 0.68500000 9.19000000 2.15000000 ;
+ RECT 7.13000000 2.03500000 7.27000000 2.22500000 ;
+ RECT 8.97500000 2.15000000 9.26500000 2.22500000 ;
+ RECT 7.13000000 2.22500000 9.26500000 2.36500000 ;
+ RECT 8.97500000 2.36500000 9.26500000 2.44000000 ;
+ END
+ END Q
+
+ PIN D
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 2.73500000 1.20500000 3.02500000 1.49500000 ;
+ END
+ END D
+
+ PIN CLK
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 1.29500000 0.80000000 1.58500000 0.87500000 ;
+ RECT 4.17500000 0.80000000 4.46500000 0.87500000 ;
+ RECT 1.29500000 0.87500000 4.46500000 1.01500000 ;
+ RECT 1.29500000 1.01500000 1.58500000 1.09000000 ;
+ RECT 4.17500000 1.01500000 4.46500000 1.09000000 ;
+ END
+ END CLK
+
+
+END LATCH
diff --git a/cells/lib/AND2X1.lib b/cells/lib/AND2X1.lib
new file mode 100644
index 0000000..551d7c1
--- /dev/null
+++ b/cells/lib/AND2X1.lib
@@ -0,0 +1,329 @@
+library (ls05_stdcells) {
+ capacitive_load_unit (1.0, pf);
+ current_unit: "1uA";
+ default_operating_conditions: typical;
+ delay_model: table_lookup;
+ in_place_swap_mode: match_footprint;
+ input_threshold_pct_fall: 50.0;
+ input_threshold_pct_rise: 50.0;
+ leakage_power_unit: "1nW";
+ nom_process: 1.0;
+ nom_temperature: 25.0;
+ nom_voltage: 5.0;
+ output_threshold_pct_fall: 50.0;
+ output_threshold_pct_rise: 50.0;
+ pulling_resistance_unit: "1kohm";
+ slew_lower_threshold_pct_fall: 20.0;
+ slew_lower_threshold_pct_rise: 20.0;
+ slew_upper_threshold_pct_fall: 80.0;
+ slew_upper_threshold_pct_rise: 80.0;
+ time_unit: "1ns";
+ voltage_unit: "1V";
+ operating_conditions (typical) {
+ process: 1.0;
+ temperature: 25.0;
+ voltage: 5.0;
+ }
+ lu_table_template (delay_template_5x1) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: input_net_transition;
+ }
+ lu_table_template (delay_template_5x5) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_net_transition;
+ }
+ lu_table_template (delay_template_5x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_net_transition;
+ }
+ lu_table_template (delay_template_6x1) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: input_net_transition;
+ }
+ lu_table_template (delay_template_6x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_net_transition;
+ }
+ power_lut_template (energy_template_5x5) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_transition_time;
+ }
+ power_lut_template (energy_template_5x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_transition_time;
+ }
+ power_lut_template (energy_template_6x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_transition_time;
+ }
+ lu_table_template (hold_template_3x5) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (hold_template_3x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ power_lut_template (passive_energy_template_5x1) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: input_transition_time;
+ }
+ power_lut_template (passive_energy_template_6x1) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: input_transition_time;
+ }
+ lu_table_template (recovery_template_3x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (recovery_template_6x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (removal_template_3x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (setup_template_3x5) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (setup_template_3x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ cell (AND2X1) {
+ area: 219456.0;
+ cell_leakage_power: 0.1173;
+ pin (B) {
+ capacitance: 0.006376640566539888;
+ direction: input;
+ fall_capacitance: 0.007817866144461614;
+ rise_capacitance: 0.004935414988618162;
+ }
+ pin (A) {
+ capacitance: 0.004934912141017381;
+ direction: input;
+ fall_capacitance: 0.005718976233108118;
+ rise_capacitance: 0.004150848048926644;
+ }
+ pin (Y) {
+ direction: output;
+ function: "(A & B)";
+ timing () {
+ related_pin: "B";
+ timing_sense: positive_unate;
+ cell_rise (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "-0.002948, 0.031940, 0.041541, 0.057971, 0.167270", \
+ "0.046740, 0.066340, 0.080659, 0.100026, 0.234969", \
+ "0.087186, 0.100322, 0.115691, 0.131365, 0.287516", \
+ "0.172387, 0.177799, 0.194182, 0.207143, 0.391362", \
+ "0.875090, 0.868452, 0.882814, 0.885407, 1.014582"
+ );
+ }
+ cell_fall (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.018337, 0.021491, 0.024061, 0.022400, -0.034178", \
+ "0.057356, 0.058976, 0.061060, 0.061598, 0.018699", \
+ "0.101068, 0.100276, 0.099697, 0.099202, 0.056903", \
+ "0.189356, 0.187013, 0.183889, 0.178499, 0.123050", \
+ "0.904340, 0.900488, 0.894961, 0.882939, 0.736675"
+ );
+ }
+ rise_transition (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.023782, 0.069362, 0.036426, 0.060782, 0.451813", \
+ "0.082213, 0.120065, 0.087665, 0.099865, 0.447412", \
+ "0.148581, 0.153464, 0.150834, 0.158504, 0.456107", \
+ "0.288739, 0.289793, 0.288655, 0.291280, 0.521942", \
+ "1.420537, 1.420621, 1.420499, 1.420615, 1.490972"
+ );
+ }
+ fall_transition (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.020393, 0.034829, 0.056096, 0.100019, 0.517345", \
+ "0.095190, 0.099481, 0.112772, 0.142410, 0.561271", \
+ "0.177215, 0.179045, 0.186734, 0.209104, 0.606400", \
+ "0.348536, 0.348577, 0.350362, 0.361641, 0.706589", \
+ "1.724982, 1.724975, 1.726148, 1.725949, 1.797117"
+ );
+ }
+ }
+ timing () {
+ related_pin: "A";
+ timing_sense: positive_unate;
+ cell_rise (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "-0.003054, 0.030756, 0.036895, 0.053450, 0.189178", \
+ "0.048196, 0.064408, 0.074956, 0.091763, 0.252273", \
+ "0.087882, 0.098714, 0.108728, 0.124797, 0.301834", \
+ "0.172911, 0.177390, 0.184992, 0.194729, 0.394941", \
+ "0.874950, 0.870127, 0.872743, 0.868968, 0.975510"
+ );
+ }
+ cell_fall (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.015977, 0.018578, 0.018625, 0.016540, -0.078601", \
+ "0.056110, 0.056571, 0.057910, 0.059432, -0.014766", \
+ "0.100103, 0.098361, 0.096720, 0.097022, 0.031993", \
+ "0.188179, 0.185369, 0.181269, 0.175611, 0.117769", \
+ "0.903173, 0.899107, 0.892661, 0.880044, 0.755676"
+ );
+ }
+ rise_transition (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.026432, 0.041227, 0.045227, 0.082731, 0.591445", \
+ "0.081271, 0.098565, 0.094743, 0.114263, 0.587890", \
+ "0.150173, 0.152420, 0.156118, 0.171333, 0.591808", \
+ "0.288387, 0.289298, 0.289941, 0.296010, 0.641073", \
+ "1.420770, 1.420848, 1.420544, 1.420583, 1.523188"
+ );
+ }
+ fall_transition (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.017097, 0.032096, 0.052471, 0.097966, 0.610977", \
+ "0.094380, 0.097484, 0.111245, 0.144180, 0.624946", \
+ "0.178566, 0.178965, 0.185471, 0.210040, 0.674274", \
+ "0.348822, 0.348770, 0.350494, 0.361953, 0.778001", \
+ "1.726209, 1.725209, 1.724995, 1.725568, 1.841959"
+ );
+ }
+ }
+ }
+ }
+}
\ No newline at end of file
diff --git a/cells/lib/AND2X2.lib b/cells/lib/AND2X2.lib
new file mode 100644
index 0000000..612665a
--- /dev/null
+++ b/cells/lib/AND2X2.lib
@@ -0,0 +1,329 @@
+library (ls05_stdcells) {
+ capacitive_load_unit (1.0, pf);
+ current_unit: "1uA";
+ default_operating_conditions: typical;
+ delay_model: table_lookup;
+ in_place_swap_mode: match_footprint;
+ input_threshold_pct_fall: 50.0;
+ input_threshold_pct_rise: 50.0;
+ leakage_power_unit: "1nW";
+ nom_process: 1.0;
+ nom_temperature: 25.0;
+ nom_voltage: 5.0;
+ output_threshold_pct_fall: 50.0;
+ output_threshold_pct_rise: 50.0;
+ pulling_resistance_unit: "1kohm";
+ slew_lower_threshold_pct_fall: 20.0;
+ slew_lower_threshold_pct_rise: 20.0;
+ slew_upper_threshold_pct_fall: 80.0;
+ slew_upper_threshold_pct_rise: 80.0;
+ time_unit: "1ns";
+ voltage_unit: "1V";
+ operating_conditions (typical) {
+ process: 1.0;
+ temperature: 25.0;
+ voltage: 5.0;
+ }
+ lu_table_template (delay_template_5x1) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: input_net_transition;
+ }
+ lu_table_template (delay_template_5x5) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_net_transition;
+ }
+ lu_table_template (delay_template_5x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_net_transition;
+ }
+ lu_table_template (delay_template_6x1) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: input_net_transition;
+ }
+ lu_table_template (delay_template_6x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_net_transition;
+ }
+ power_lut_template (energy_template_5x5) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_transition_time;
+ }
+ power_lut_template (energy_template_5x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_transition_time;
+ }
+ power_lut_template (energy_template_6x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_transition_time;
+ }
+ lu_table_template (hold_template_3x5) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (hold_template_3x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ power_lut_template (passive_energy_template_5x1) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: input_transition_time;
+ }
+ power_lut_template (passive_energy_template_6x1) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: input_transition_time;
+ }
+ lu_table_template (recovery_template_3x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (recovery_template_6x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (removal_template_3x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (setup_template_3x5) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (setup_template_3x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ cell (AND2X2) {
+ area: 219456.0;
+ cell_leakage_power: 0.1173;
+ pin (B) {
+ capacitance: 0.006376640566539888;
+ direction: input;
+ fall_capacitance: 0.007817866144461614;
+ rise_capacitance: 0.004935414988618162;
+ }
+ pin (A) {
+ capacitance: 0.004934912141017381;
+ direction: input;
+ fall_capacitance: 0.005718976233108118;
+ rise_capacitance: 0.004150848048926644;
+ }
+ pin (Y) {
+ direction: output;
+ function: "(A & B)";
+ timing () {
+ related_pin: "B";
+ timing_sense: positive_unate;
+ cell_rise (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "-0.002948, 0.031940, 0.041541, 0.057971, 0.167270", \
+ "0.046740, 0.066340, 0.080659, 0.100026, 0.234969", \
+ "0.087186, 0.100322, 0.115691, 0.131365, 0.287516", \
+ "0.172387, 0.177799, 0.194182, 0.207143, 0.391362", \
+ "0.875090, 0.868452, 0.882814, 0.885407, 1.014582"
+ );
+ }
+ cell_fall (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.018337, 0.021491, 0.024061, 0.022400, -0.034178", \
+ "0.057356, 0.058976, 0.061060, 0.061598, 0.018699", \
+ "0.101068, 0.100276, 0.099697, 0.099202, 0.056903", \
+ "0.189356, 0.187013, 0.183889, 0.178499, 0.123050", \
+ "0.904340, 0.900488, 0.894961, 0.882939, 0.736675"
+ );
+ }
+ rise_transition (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.023782, 0.069362, 0.036426, 0.060782, 0.451813", \
+ "0.082213, 0.120065, 0.087665, 0.099865, 0.447412", \
+ "0.148581, 0.153464, 0.150834, 0.158504, 0.456107", \
+ "0.288739, 0.289793, 0.288655, 0.291280, 0.521942", \
+ "1.420537, 1.420621, 1.420499, 1.420615, 1.490972"
+ );
+ }
+ fall_transition (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.020393, 0.034829, 0.056096, 0.100019, 0.517345", \
+ "0.095190, 0.099481, 0.112772, 0.142410, 0.561271", \
+ "0.177215, 0.179045, 0.186734, 0.209104, 0.606400", \
+ "0.348536, 0.348577, 0.350362, 0.361641, 0.706589", \
+ "1.724982, 1.724975, 1.726148, 1.725949, 1.797117"
+ );
+ }
+ }
+ timing () {
+ related_pin: "A";
+ timing_sense: positive_unate;
+ cell_rise (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "-0.003054, 0.030756, 0.036895, 0.053450, 0.189178", \
+ "0.048196, 0.064408, 0.074956, 0.091763, 0.252273", \
+ "0.087882, 0.098714, 0.108728, 0.124797, 0.301834", \
+ "0.172911, 0.177390, 0.184992, 0.194729, 0.394941", \
+ "0.874950, 0.870127, 0.872743, 0.868968, 0.975510"
+ );
+ }
+ cell_fall (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.015977, 0.018578, 0.018625, 0.016540, -0.078601", \
+ "0.056110, 0.056571, 0.057910, 0.059432, -0.014766", \
+ "0.100103, 0.098361, 0.096720, 0.097022, 0.031993", \
+ "0.188179, 0.185369, 0.181269, 0.175611, 0.117769", \
+ "0.903173, 0.899107, 0.892661, 0.880044, 0.755676"
+ );
+ }
+ rise_transition (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.026432, 0.041227, 0.045227, 0.082731, 0.591445", \
+ "0.081271, 0.098565, 0.094743, 0.114263, 0.587890", \
+ "0.150173, 0.152420, 0.156118, 0.171333, 0.591808", \
+ "0.288387, 0.289298, 0.289941, 0.296010, 0.641073", \
+ "1.420770, 1.420848, 1.420544, 1.420583, 1.523188"
+ );
+ }
+ fall_transition (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.017097, 0.032096, 0.052471, 0.097966, 0.610977", \
+ "0.094380, 0.097484, 0.111245, 0.144180, 0.624946", \
+ "0.178566, 0.178965, 0.185471, 0.210040, 0.674274", \
+ "0.348822, 0.348770, 0.350494, 0.361953, 0.778001", \
+ "1.726209, 1.725209, 1.724995, 1.725568, 1.841959"
+ );
+ }
+ }
+ }
+ }
+}
\ No newline at end of file
diff --git a/cells/lib/AOI21X1.lib b/cells/lib/AOI21X1.lib
new file mode 100644
index 0000000..bef30a7
--- /dev/null
+++ b/cells/lib/AOI21X1.lib
@@ -0,0 +1,399 @@
+library (ls05_stdcells) {
+ capacitive_load_unit (1.0, pf);
+ current_unit: "1uA";
+ default_operating_conditions: typical;
+ delay_model: table_lookup;
+ in_place_swap_mode: match_footprint;
+ input_threshold_pct_fall: 50.0;
+ input_threshold_pct_rise: 50.0;
+ leakage_power_unit: "1nW";
+ nom_process: 1.0;
+ nom_temperature: 25.0;
+ nom_voltage: 5.0;
+ output_threshold_pct_fall: 50.0;
+ output_threshold_pct_rise: 50.0;
+ pulling_resistance_unit: "1kohm";
+ slew_lower_threshold_pct_fall: 20.0;
+ slew_lower_threshold_pct_rise: 20.0;
+ slew_upper_threshold_pct_fall: 80.0;
+ slew_upper_threshold_pct_rise: 80.0;
+ time_unit: "1ns";
+ voltage_unit: "1V";
+ operating_conditions (typical) {
+ process: 1.0;
+ temperature: 25.0;
+ voltage: 5.0;
+ }
+ lu_table_template (delay_template_5x1) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: input_net_transition;
+ }
+ lu_table_template (delay_template_5x5) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_net_transition;
+ }
+ lu_table_template (delay_template_5x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_net_transition;
+ }
+ lu_table_template (delay_template_6x1) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: input_net_transition;
+ }
+ lu_table_template (delay_template_6x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_net_transition;
+ }
+ power_lut_template (energy_template_5x5) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_transition_time;
+ }
+ power_lut_template (energy_template_5x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_transition_time;
+ }
+ power_lut_template (energy_template_6x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_transition_time;
+ }
+ lu_table_template (hold_template_3x5) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (hold_template_3x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ power_lut_template (passive_energy_template_5x1) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: input_transition_time;
+ }
+ power_lut_template (passive_energy_template_6x1) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: input_transition_time;
+ }
+ lu_table_template (recovery_template_3x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (recovery_template_6x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (removal_template_3x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (setup_template_3x5) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (setup_template_3x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ cell (AOI21X1) {
+ area: 219456.0;
+ cell_leakage_power: 0.1173;
+ pin (C) {
+ capacitance: 0.006189667947317773;
+ direction: input;
+ fall_capacitance: 0.00608282711442158;
+ rise_capacitance: 0.006296508780213967;
+ }
+ pin (B) {
+ capacitance: 0.004946001600705809;
+ direction: input;
+ fall_capacitance: 0.005741143923488236;
+ rise_capacitance: 0.004150859277923382;
+ }
+ pin (A) {
+ capacitance: 0.0063768651510662175;
+ direction: input;
+ fall_capacitance: 0.007818310946312182;
+ rise_capacitance: 0.0049354193558202525;
+ }
+ pin (Y) {
+ direction: output;
+ function: "((A & !B & !C + B & !A & !C + !A & !B & !C))";
+ timing () {
+ related_pin: "C";
+ timing_sense: negative_unate;
+ cell_rise (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.012884, 0.013814, 0.016718, 0.021870, 0.028833", \
+ "0.086107, 0.080864, 0.082497, 0.093433, 0.172718", \
+ "0.157907, 0.150075, 0.149039, 0.154342, 0.270928", \
+ "0.301166, 0.291665, 0.287163, 0.285601, 0.427419", \
+ "1.448480, 1.437527, 1.428051, 1.413899, 1.417674"
+ );
+ }
+ cell_fall (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.005708, 0.008603, 0.010605, 0.008342, 0.014912", \
+ "0.046767, 0.047758, 0.052811, 0.059897, 0.111616", \
+ "0.091313, 0.089826, 0.091015, 0.099539, 0.178409", \
+ "0.180111, 0.176982, 0.175277, 0.175888, 0.287227", \
+ "0.895506, 0.891449, 0.886851, 0.878783, 0.902515"
+ );
+ }
+ rise_transition (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.012972, 0.024876, 0.045576, 0.092382, 0.730301", \
+ "0.117670, 0.118582, 0.124112, 0.144342, 0.702744", \
+ "0.221586, 0.221908, 0.222072, 0.232193, 0.694310", \
+ "0.430244, 0.430091, 0.430239, 0.430802, 0.761045", \
+ "2.104719, 2.104806, 2.104636, 2.104737, 2.138480"
+ );
+ }
+ fall_transition (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.013144, 0.040328, 0.065020, 0.111186, 0.739334", \
+ "0.095171, 0.101388, 0.116357, 0.159575, 0.811404", \
+ "0.180158, 0.181007, 0.191810, 0.223783, 0.880144", \
+ "0.350588, 0.350580, 0.354001, 0.371311, 0.983014", \
+ "1.727889, 1.727581, 1.728170, 1.727705, 1.982896"
+ );
+ }
+ }
+ timing () {
+ related_pin: "B";
+ timing_sense: negative_unate;
+ cell_rise (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.015335, 0.016982, 0.017673, 0.018219, -0.069608", \
+ "0.094019, 0.093932, 0.095770, 0.102779, 0.105301", \
+ "0.171502, 0.171151, 0.171863, 0.175258, 0.222703", \
+ "0.326268, 0.325524, 0.325280, 0.326346, 0.409421", \
+ "1.565887, 1.565044, 1.563580, 1.561246, 1.585994"
+ );
+ }
+ cell_fall (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.013287, 0.024880, 0.031685, 0.037498, 0.167659", \
+ "0.107124, 0.105845, 0.107193, 0.117896, 0.299712", \
+ "0.201357, 0.197038, 0.194436, 0.196480, 0.391707", \
+ "0.390085, 0.383995, 0.377751, 0.370715, 0.543155", \
+ "1.901754, 1.893671, 1.883505, 1.864991, 1.785557"
+ );
+ }
+ rise_transition (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.013701, 0.021239, 0.037128, 0.074532, 0.517052", \
+ "0.124145, 0.126554, 0.127481, 0.138597, 0.502699", \
+ "0.236289, 0.237521, 0.237587, 0.239899, 0.557716", \
+ "0.461681, 0.461011, 0.461333, 0.461741, 0.666948", \
+ "2.263739, 2.263875, 2.263871, 2.263837, 2.266936"
+ );
+ }
+ fall_transition (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.030160, 0.038814, 0.058225, 0.102917, 0.553894", \
+ "0.158458, 0.157631, 0.161617, 0.182586, 0.706485", \
+ "0.287898, 0.286716, 0.287445, 0.295747, 0.780606", \
+ "0.548485, 0.548526, 0.548522, 0.548250, 0.902420", \
+ "2.640741, 2.640742, 2.640727, 2.640745, 2.647561"
+ );
+ }
+ }
+ timing () {
+ related_pin: "A";
+ timing_sense: negative_unate;
+ cell_rise (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.018081, 0.020472, 0.022446, 0.023825, -0.023691", \
+ "0.096239, 0.096537, 0.098721, 0.106326, 0.139254", \
+ "0.173813, 0.173358, 0.174228, 0.178403, 0.251687", \
+ "0.328514, 0.327676, 0.327494, 0.329061, 0.431351", \
+ "1.568114, 1.567133, 1.565660, 1.563413, 1.593357"
+ );
+ }
+ cell_fall (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.011083, 0.026784, 0.035062, 0.040835, 0.137110", \
+ "0.106329, 0.111405, 0.118093, 0.132531, 0.298206", \
+ "0.200961, 0.203504, 0.207727, 0.219147, 0.408186", \
+ "0.389721, 0.390740, 0.393162, 0.400718, 0.586451", \
+ "1.901421, 1.900917, 1.900632, 1.901495, 1.980436"
+ );
+ }
+ rise_transition (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.017574, 0.025241, 0.039240, 0.074436, 0.320255", \
+ "0.130209, 0.130934, 0.131571, 0.144964, 0.452202", \
+ "0.240805, 0.242496, 0.242369, 0.244406, 0.548288", \
+ "0.466498, 0.466251, 0.466522, 0.466774, 0.675363", \
+ "2.268774, 2.268830, 2.268824, 2.268768, 2.271727"
+ );
+ }
+ fall_transition (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.029014, 0.034924, 0.042010, 0.073728, 0.327469", \
+ "0.158673, 0.158762, 0.158147, 0.170170, 0.467645", \
+ "0.287787, 0.287911, 0.287075, 0.288882, 0.551159", \
+ "0.548458, 0.548226, 0.548509, 0.548657, 0.704977", \
+ "2.640715, 2.640671, 2.640748, 2.640738, 2.640639"
+ );
+ }
+ }
+ }
+ }
+}
\ No newline at end of file
diff --git a/cells/lib/AOI22X1.lib b/cells/lib/AOI22X1.lib
new file mode 100644
index 0000000..12ed5fc
--- /dev/null
+++ b/cells/lib/AOI22X1.lib
@@ -0,0 +1,469 @@
+library (ls05_stdcells) {
+ capacitive_load_unit (1.0, pf);
+ current_unit: "1uA";
+ default_operating_conditions: typical;
+ delay_model: table_lookup;
+ in_place_swap_mode: match_footprint;
+ input_threshold_pct_fall: 50.0;
+ input_threshold_pct_rise: 50.0;
+ leakage_power_unit: "1nW";
+ nom_process: 1.0;
+ nom_temperature: 25.0;
+ nom_voltage: 5.0;
+ output_threshold_pct_fall: 50.0;
+ output_threshold_pct_rise: 50.0;
+ pulling_resistance_unit: "1kohm";
+ slew_lower_threshold_pct_fall: 20.0;
+ slew_lower_threshold_pct_rise: 20.0;
+ slew_upper_threshold_pct_fall: 80.0;
+ slew_upper_threshold_pct_rise: 80.0;
+ time_unit: "1ns";
+ voltage_unit: "1V";
+ operating_conditions (typical) {
+ process: 1.0;
+ temperature: 25.0;
+ voltage: 5.0;
+ }
+ lu_table_template (delay_template_5x1) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: input_net_transition;
+ }
+ lu_table_template (delay_template_5x5) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_net_transition;
+ }
+ lu_table_template (delay_template_5x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_net_transition;
+ }
+ lu_table_template (delay_template_6x1) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: input_net_transition;
+ }
+ lu_table_template (delay_template_6x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_net_transition;
+ }
+ power_lut_template (energy_template_5x5) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_transition_time;
+ }
+ power_lut_template (energy_template_5x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_transition_time;
+ }
+ power_lut_template (energy_template_6x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_transition_time;
+ }
+ lu_table_template (hold_template_3x5) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (hold_template_3x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ power_lut_template (passive_energy_template_5x1) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: input_transition_time;
+ }
+ power_lut_template (passive_energy_template_6x1) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: input_transition_time;
+ }
+ lu_table_template (recovery_template_3x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (recovery_template_6x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (removal_template_3x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (setup_template_3x5) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (setup_template_3x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ cell (AOI22X1) {
+ area: 274320.0;
+ cell_leakage_power: 0.1173;
+ pin (D) {
+ capacitance: 0.0020974613531819556;
+ direction: input;
+ fall_capacitance: 4.4104117800871274e-05;
+ rise_capacitance: 0.004150818588563039;
+ }
+ pin (C) {
+ capacitance: 0.004812606268016478;
+ direction: input;
+ fall_capacitance: 0.004689865191387634;
+ rise_capacitance: 0.0049353473446453215;
+ }
+ pin (B) {
+ capacitance: 0.004946165373579888;
+ direction: input;
+ fall_capacitance: 0.005741463237564304;
+ rise_capacitance: 0.0041508675095954725;
+ }
+ pin (A) {
+ capacitance: 0.006371776083769734;
+ direction: input;
+ fall_capacitance: 0.007808127096433607;
+ rise_capacitance: 0.004935425071105862;
+ }
+ pin (Y) {
+ direction: output;
+ function: "(!(A & B & C & D + A & B & C & !D + A & B & D & !C + A & C & D & !B + B & C & D & !A + A & B & !C & !D + C & D & !A & !B))";
+ timing () {
+ related_pin: "D";
+ timing_sense: negative_unate;
+ cell_rise (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.016935, 0.014883, 0.015703, 0.012454, -0.033501", \
+ "0.090542, 0.082772, 0.082614, 0.090524, 0.114504", \
+ "0.162325, 0.152911, 0.149501, 0.151692, 0.215638", \
+ "0.305626, 0.294845, 0.288283, 0.283584, 0.379358", \
+ "1.452827, 1.441115, 1.430562, 1.414232, 1.385088"
+ );
+ }
+ cell_fall (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.011131, 0.018803, 0.024733, 0.032496, 0.108096", \
+ "0.102250, 0.099676, 0.101552, 0.112143, 0.253101", \
+ "0.196075, 0.190340, 0.188422, 0.190760, 0.352663", \
+ "0.384766, 0.377069, 0.371270, 0.364996, 0.516099", \
+ "1.896343, 1.886398, 1.876274, 1.858129, 1.777799"
+ );
+ }
+ rise_transition (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.016765, 0.027275, 0.049942, 0.091821, 0.629255", \
+ "0.121167, 0.122670, 0.127043, 0.150833, 0.656506", \
+ "0.224824, 0.225478, 0.225444, 0.237122, 0.716205", \
+ "0.433527, 0.433720, 0.433798, 0.434581, 0.814040", \
+ "2.108310, 2.108361, 2.108226, 2.108327, 2.151506"
+ );
+ }
+ fall_transition (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.019540, 0.037485, 0.048144, 0.090862, 0.624895", \
+ "0.148113, 0.148658, 0.152486, 0.173373, 0.676277", \
+ "0.277916, 0.277395, 0.278530, 0.285802, 0.738740", \
+ "0.538822, 0.539108, 0.538745, 0.539142, 0.865875", \
+ "2.631103, 2.631167, 2.631060, 2.631158, 2.638378"
+ );
+ }
+ }
+ timing () {
+ related_pin: "C";
+ timing_sense: negative_unate;
+ cell_rise (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.020369, 0.018428, 0.021368, 0.020061, 0.016757", \
+ "0.092490, 0.085158, 0.085310, 0.094546, 0.156465", \
+ "0.164627, 0.154984, 0.151976, 0.154901, 0.251955", \
+ "0.307751, 0.296984, 0.290533, 0.286397, 0.406843", \
+ "1.454952, 1.443103, 1.432571, 1.416364, 1.394708"
+ );
+ }
+ cell_fall (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.010498, 0.021560, 0.028514, 0.037495, 0.082368", \
+ "0.101825, 0.105130, 0.112161, 0.127308, 0.261185", \
+ "0.195561, 0.196794, 0.201635, 0.213814, 0.379961", \
+ "0.384369, 0.383935, 0.386589, 0.394605, 0.568320", \
+ "1.895945, 1.893647, 1.893375, 1.894401, 1.975233"
+ );
+ }
+ rise_transition (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.021236, 0.031459, 0.054625, 0.095131, 0.470508", \
+ "0.126934, 0.126375, 0.131675, 0.156729, 0.627474", \
+ "0.229762, 0.229630, 0.230077, 0.241674, 0.716118", \
+ "0.438091, 0.438482, 0.438252, 0.439405, 0.825499", \
+ "2.112964, 2.112929, 2.112863, 2.112978, 2.155164"
+ );
+ }
+ fall_transition (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.021627, 0.035591, 0.035070, 0.070098, 0.433450", \
+ "0.147776, 0.149177, 0.150009, 0.161817, 0.458917", \
+ "0.277709, 0.277366, 0.277596, 0.280531, 0.527096", \
+ "0.539065, 0.539093, 0.539109, 0.538946, 0.684263", \
+ "2.631099, 2.631149, 2.631170, 2.631100, 2.631114"
+ );
+ }
+ }
+ timing () {
+ related_pin: "B";
+ timing_sense: negative_unate;
+ cell_rise (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.019809, 0.021467, 0.022993, 0.023258, -0.058701", \
+ "0.092131, 0.092348, 0.095145, 0.101841, 0.098557", \
+ "0.164877, 0.164124, 0.165065, 0.169626, 0.210368", \
+ "0.308029, 0.307392, 0.307470, 0.309169, 0.390164", \
+ "1.457169, 1.456286, 1.455144, 1.453124, 1.488193"
+ );
+ }
+ cell_fall (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.013313, 0.029532, 0.038717, 0.047945, 0.188158", \
+ "0.107990, 0.110195, 0.113203, 0.124738, 0.313534", \
+ "0.202371, 0.200606, 0.199392, 0.203099, 0.404174", \
+ "0.391167, 0.386925, 0.382011, 0.376561, 0.554823", \
+ "1.902931, 1.895987, 1.886227, 1.868549, 1.797821"
+ );
+ }
+ rise_transition (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.019429, 0.026568, 0.042468, 0.080756, 0.516753", \
+ "0.124108, 0.123505, 0.123820, 0.139390, 0.517896", \
+ "0.226304, 0.226453, 0.226121, 0.229413, 0.571103", \
+ "0.432605, 0.432992, 0.433334, 0.433130, 0.669772", \
+ "2.096546, 2.096500, 2.096504, 2.096401, 2.104903"
+ );
+ }
+ fall_transition (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.036963, 0.064663, 0.063261, 0.104268, 0.557323", \
+ "0.169060, 0.168178, 0.170874, 0.190953, 0.690517", \
+ "0.298594, 0.298892, 0.298450, 0.305039, 0.761400", \
+ "0.559542, 0.559072, 0.559520, 0.559454, 0.890958", \
+ "2.651812, 2.651739, 2.651820, 2.651765, 2.658183"
+ );
+ }
+ }
+ timing () {
+ related_pin: "A";
+ timing_sense: negative_unate;
+ cell_rise (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.022678, 0.024602, 0.027657, 0.027746, -0.014253", \
+ "0.094425, 0.094825, 0.097714, 0.105256, 0.133288", \
+ "0.166876, 0.166299, 0.167299, 0.172465, 0.239654", \
+ "0.310022, 0.309359, 0.309537, 0.311595, 0.412132", \
+ "1.459221, 1.458255, 1.457052, 1.455130, 1.495355"
+ );
+ }
+ cell_fall (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.010762, 0.031615, 0.042726, 0.054379, 0.162255", \
+ "0.107178, 0.114877, 0.123673, 0.140333, 0.314762", \
+ "0.201740, 0.206695, 0.212432, 0.225560, 0.423426", \
+ "0.390675, 0.393589, 0.396909, 0.405745, 0.599731", \
+ "1.902538, 1.903226, 1.903241, 1.904537, 1.991568"
+ );
+ }
+ rise_transition (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.023953, 0.030647, 0.045679, 0.081384, 0.352989", \
+ "0.128243, 0.127626, 0.127724, 0.144629, 0.476733", \
+ "0.230700, 0.231079, 0.230551, 0.233540, 0.563234", \
+ "0.437513, 0.437483, 0.437930, 0.437603, 0.677229", \
+ "2.101139, 2.101103, 2.101049, 2.100995, 2.109091"
+ );
+ }
+ fall_transition (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.035078, 0.066496, 0.049387, 0.080483, 0.340869", \
+ "0.168775, 0.168226, 0.168846, 0.179604, 0.463584", \
+ "0.298761, 0.298598, 0.298932, 0.300297, 0.541365", \
+ "0.559293, 0.559471, 0.559155, 0.559533, 0.704149", \
+ "2.651791, 2.651807, 2.651756, 2.651826, 2.651827"
+ );
+ }
+ }
+ }
+ }
+}
\ No newline at end of file
diff --git a/cells/lib/BUFX2.lib b/cells/lib/BUFX2.lib
new file mode 100644
index 0000000..c31a500
--- /dev/null
+++ b/cells/lib/BUFX2.lib
@@ -0,0 +1,259 @@
+library (ls05_stdcells) {
+ capacitive_load_unit (1.0, pf);
+ current_unit: "1uA";
+ default_operating_conditions: typical;
+ delay_model: table_lookup;
+ in_place_swap_mode: match_footprint;
+ input_threshold_pct_fall: 50.0;
+ input_threshold_pct_rise: 50.0;
+ leakage_power_unit: "1nW";
+ nom_process: 1.0;
+ nom_temperature: 25.0;
+ nom_voltage: 5.0;
+ output_threshold_pct_fall: 50.0;
+ output_threshold_pct_rise: 50.0;
+ pulling_resistance_unit: "1kohm";
+ slew_lower_threshold_pct_fall: 20.0;
+ slew_lower_threshold_pct_rise: 20.0;
+ slew_upper_threshold_pct_fall: 80.0;
+ slew_upper_threshold_pct_rise: 80.0;
+ time_unit: "1ns";
+ voltage_unit: "1V";
+ operating_conditions (typical) {
+ process: 1.0;
+ temperature: 25.0;
+ voltage: 5.0;
+ }
+ lu_table_template (delay_template_5x1) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: input_net_transition;
+ }
+ lu_table_template (delay_template_5x5) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_net_transition;
+ }
+ lu_table_template (delay_template_5x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_net_transition;
+ }
+ lu_table_template (delay_template_6x1) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: input_net_transition;
+ }
+ lu_table_template (delay_template_6x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_net_transition;
+ }
+ power_lut_template (energy_template_5x5) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_transition_time;
+ }
+ power_lut_template (energy_template_5x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_transition_time;
+ }
+ power_lut_template (energy_template_6x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_transition_time;
+ }
+ lu_table_template (hold_template_3x5) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (hold_template_3x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ power_lut_template (passive_energy_template_5x1) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: input_transition_time;
+ }
+ power_lut_template (passive_energy_template_6x1) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: input_transition_time;
+ }
+ lu_table_template (recovery_template_3x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (recovery_template_6x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (removal_template_3x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (setup_template_3x5) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (setup_template_3x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ cell (BUFX2) {
+ area: 164592.0;
+ cell_leakage_power: 0.1173;
+ pin (A) {
+ capacitance: 0.007524621021778557;
+ direction: input;
+ fall_capacitance: 0.00885894979294924;
+ rise_capacitance: 0.006190292250607873;
+ }
+ pin (Y) {
+ direction: output;
+ function: "(A)";
+ timing () {
+ related_pin: "A";
+ timing_sense: positive_unate;
+ cell_rise (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "-0.003161, 0.017829, 0.022268, 0.021768, 0.079308", \
+ "0.045055, 0.050063, 0.057136, 0.070246, 0.151768", \
+ "0.086221, 0.085910, 0.089124, 0.100838, 0.199664", \
+ "0.172654, 0.166239, 0.164336, 0.168034, 0.284850", \
+ "0.876097, 0.863347, 0.851849, 0.832547, 0.852986"
+ );
+ }
+ cell_fall (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.014482, 0.017268, 0.019923, 0.023667, -0.011126", \
+ "0.054563, 0.055999, 0.060204, 0.069455, 0.072439", \
+ "0.098790, 0.098063, 0.098828, 0.107532, 0.136737", \
+ "0.187149, 0.184801, 0.183271, 0.184852, 0.249296", \
+ "0.902112, 0.898842, 0.894592, 0.887713, 0.887222"
+ );
+ }
+ rise_transition (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.021141, 0.053260, 0.060446, 0.114111, 0.839043", \
+ "0.078233, 0.096018, 0.107000, 0.143602, 0.829526", \
+ "0.148965, 0.150631, 0.162142, 0.191631, 0.827817", \
+ "0.288402, 0.288541, 0.290092, 0.306795, 0.865517", \
+ "1.420305, 1.420150, 1.420683, 1.420175, 1.615594"
+ );
+ }
+ fall_transition (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.015821, 0.030737, 0.052343, 0.106785, 0.838213", \
+ "0.092115, 0.097031, 0.110737, 0.149525, 0.839377", \
+ "0.177675, 0.179318, 0.186569, 0.215056, 0.850611", \
+ "0.349011, 0.348267, 0.350542, 0.364446, 0.905444", \
+ "1.725400, 1.725176, 1.725220, 1.725574, 1.913061"
+ );
+ }
+ }
+ }
+ }
+}
\ No newline at end of file
diff --git a/cells/lib/BUFX4.lib b/cells/lib/BUFX4.lib
new file mode 100644
index 0000000..89862e0
--- /dev/null
+++ b/cells/lib/BUFX4.lib
@@ -0,0 +1,259 @@
+library (ls05_stdcells) {
+ capacitive_load_unit (1.0, pf);
+ current_unit: "1uA";
+ default_operating_conditions: typical;
+ delay_model: table_lookup;
+ in_place_swap_mode: match_footprint;
+ input_threshold_pct_fall: 50.0;
+ input_threshold_pct_rise: 50.0;
+ leakage_power_unit: "1nW";
+ nom_process: 1.0;
+ nom_temperature: 25.0;
+ nom_voltage: 5.0;
+ output_threshold_pct_fall: 50.0;
+ output_threshold_pct_rise: 50.0;
+ pulling_resistance_unit: "1kohm";
+ slew_lower_threshold_pct_fall: 20.0;
+ slew_lower_threshold_pct_rise: 20.0;
+ slew_upper_threshold_pct_fall: 80.0;
+ slew_upper_threshold_pct_rise: 80.0;
+ time_unit: "1ns";
+ voltage_unit: "1V";
+ operating_conditions (typical) {
+ process: 1.0;
+ temperature: 25.0;
+ voltage: 5.0;
+ }
+ lu_table_template (delay_template_5x1) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: input_net_transition;
+ }
+ lu_table_template (delay_template_5x5) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_net_transition;
+ }
+ lu_table_template (delay_template_5x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_net_transition;
+ }
+ lu_table_template (delay_template_6x1) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: input_net_transition;
+ }
+ lu_table_template (delay_template_6x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_net_transition;
+ }
+ power_lut_template (energy_template_5x5) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_transition_time;
+ }
+ power_lut_template (energy_template_5x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_transition_time;
+ }
+ power_lut_template (energy_template_6x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_transition_time;
+ }
+ lu_table_template (hold_template_3x5) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (hold_template_3x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ power_lut_template (passive_energy_template_5x1) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: input_transition_time;
+ }
+ power_lut_template (passive_energy_template_6x1) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: input_transition_time;
+ }
+ lu_table_template (recovery_template_3x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (recovery_template_6x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (removal_template_3x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (setup_template_3x5) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (setup_template_3x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ cell (BUFX4) {
+ area: 219456.0;
+ cell_leakage_power: 0.1173;
+ pin (A) {
+ capacitance: 0.007514333929026605;
+ direction: input;
+ fall_capacitance: 0.008837539393571521;
+ rise_capacitance: 0.006191128464481691;
+ }
+ pin (Y) {
+ direction: output;
+ function: "(A)";
+ timing () {
+ related_pin: "A";
+ timing_sense: positive_unate;
+ cell_rise (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "-0.003332, 0.021337, 0.029037, 0.036252, 0.091507", \
+ "0.026238, 0.039009, 0.047800, 0.055261, 0.134399", \
+ "0.045194, 0.053749, 0.061884, 0.072100, 0.164091", \
+ "0.086136, 0.087693, 0.092336, 0.105084, 0.211761", \
+ "0.435031, 0.421027, 0.413172, 0.405020, 0.529945"
+ );
+ }
+ cell_fall (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.019917, 0.023446, 0.028145, 0.031913, 0.009760", \
+ "0.039765, 0.042820, 0.048616, 0.054117, 0.051193", \
+ "0.059723, 0.061229, 0.065465, 0.075300, 0.085196", \
+ "0.102990, 0.102455, 0.103727, 0.112733, 0.147808", \
+ "0.457776, 0.455343, 0.452374, 0.448140, 0.530074"
+ );
+ }
+ rise_transition (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.022555, 0.060932, 0.100046, 0.120529, 0.838717", \
+ "0.048081, 0.083216, 0.116400, 0.133925, 0.836505", \
+ "0.079669, 0.106770, 0.139757, 0.152647, 0.829964", \
+ "0.149638, 0.158594, 0.172524, 0.201707, 0.830249", \
+ "0.712717, 0.712642, 0.712987, 0.713842, 1.090806"
+ );
+ }
+ fall_transition (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.022354, 0.035611, 0.057295, 0.109654, 0.837625", \
+ "0.053183, 0.062016, 0.081775, 0.123534, 0.838808", \
+ "0.097215, 0.099197, 0.113296, 0.150874, 0.837898", \
+ "0.178609, 0.180128, 0.185695, 0.216266, 0.850702", \
+ "0.864323, 0.864161, 0.864217, 0.865032, 1.209812"
+ );
+ }
+ }
+ }
+ }
+}
\ No newline at end of file
diff --git a/cells/lib/CLKBUF1.lib b/cells/lib/CLKBUF1.lib
new file mode 100644
index 0000000..52c66ce
--- /dev/null
+++ b/cells/lib/CLKBUF1.lib
@@ -0,0 +1,259 @@
+library (ls05_stdcells) {
+ capacitive_load_unit (1.0, pf);
+ current_unit: "1uA";
+ default_operating_conditions: typical;
+ delay_model: table_lookup;
+ in_place_swap_mode: match_footprint;
+ input_threshold_pct_fall: 50.0;
+ input_threshold_pct_rise: 50.0;
+ leakage_power_unit: "1nW";
+ nom_process: 1.0;
+ nom_temperature: 25.0;
+ nom_voltage: 5.0;
+ output_threshold_pct_fall: 50.0;
+ output_threshold_pct_rise: 50.0;
+ pulling_resistance_unit: "1kohm";
+ slew_lower_threshold_pct_fall: 20.0;
+ slew_lower_threshold_pct_rise: 20.0;
+ slew_upper_threshold_pct_fall: 80.0;
+ slew_upper_threshold_pct_rise: 80.0;
+ time_unit: "1ns";
+ voltage_unit: "1V";
+ operating_conditions (typical) {
+ process: 1.0;
+ temperature: 25.0;
+ voltage: 5.0;
+ }
+ lu_table_template (delay_template_5x1) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: input_net_transition;
+ }
+ lu_table_template (delay_template_5x5) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_net_transition;
+ }
+ lu_table_template (delay_template_5x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_net_transition;
+ }
+ lu_table_template (delay_template_6x1) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: input_net_transition;
+ }
+ lu_table_template (delay_template_6x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_net_transition;
+ }
+ power_lut_template (energy_template_5x5) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_transition_time;
+ }
+ power_lut_template (energy_template_5x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_transition_time;
+ }
+ power_lut_template (energy_template_6x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_transition_time;
+ }
+ lu_table_template (hold_template_3x5) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (hold_template_3x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ power_lut_template (passive_energy_template_5x1) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: input_transition_time;
+ }
+ power_lut_template (passive_energy_template_6x1) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: input_transition_time;
+ }
+ lu_table_template (recovery_template_3x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (recovery_template_6x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (removal_template_3x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (setup_template_3x5) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (setup_template_3x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ cell (CLKBUF1) {
+ area: 493776.0;
+ cell_leakage_power: 0.1173;
+ pin (A) {
+ capacitance: 0.013425801072809228;
+ direction: input;
+ fall_capacitance: 0.014473574566389579;
+ rise_capacitance: 0.01237802757922888;
+ }
+ pin (Y) {
+ direction: output;
+ function: "(A)";
+ timing () {
+ related_pin: "A";
+ timing_sense: positive_unate;
+ cell_rise (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "-0.003460, 0.039164, 0.046896, 0.050449, 0.120253", \
+ "0.039198, 0.055206, 0.064662, 0.077056, 0.156283", \
+ "0.055272, 0.068058, 0.076746, 0.094215, 0.181108", \
+ "0.092867, 0.100270, 0.106720, 0.122551, 0.218136", \
+ "0.435146, 0.428670, 0.424456, 0.422460, 0.537852"
+ );
+ }
+ cell_fall (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.032184, 0.039672, 0.044147, 0.047413, 0.021510", \
+ "0.050419, 0.056995, 0.062609, 0.075229, 0.055087", \
+ "0.068541, 0.073865, 0.078930, 0.093698, 0.083981", \
+ "0.108988, 0.112336, 0.115801, 0.127951, 0.133757", \
+ "0.460979, 0.460184, 0.458832, 0.460220, 0.520187"
+ );
+ }
+ rise_transition (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.038133, 0.073651, 0.108037, 0.109667, 0.728970", \
+ "0.059918, 0.097402, 0.131852, 0.121421, 0.731671", \
+ "0.090369, 0.121037, 0.155826, 0.147609, 0.732523", \
+ "0.151770, 0.167602, 0.178904, 0.194858, 0.737833", \
+ "0.712055, 0.712016, 0.712316, 0.712828, 0.976108"
+ );
+ }
+ fall_transition (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.041321, 0.069345, 0.055441, 0.094793, 0.734070", \
+ "0.070699, 0.097312, 0.082033, 0.118518, 0.740459", \
+ "0.104261, 0.111495, 0.116574, 0.147708, 0.740016", \
+ "0.178901, 0.182855, 0.190726, 0.213201, 0.744041", \
+ "0.862866, 0.864337, 0.864426, 0.865268, 1.090174"
+ );
+ }
+ }
+ }
+ }
+}
\ No newline at end of file
diff --git a/cells/lib/HAX1.lib b/cells/lib/HAX1.lib
new file mode 100644
index 0000000..dd796a5
--- /dev/null
+++ b/cells/lib/HAX1.lib
@@ -0,0 +1,461 @@
+library (ls05_stdcells) {
+ capacitive_load_unit (1.0, pf);
+ current_unit: "1uA";
+ default_operating_conditions: typical;
+ delay_model: table_lookup;
+ in_place_swap_mode: match_footprint;
+ input_threshold_pct_fall: 50.0;
+ input_threshold_pct_rise: 50.0;
+ leakage_power_unit: "1nW";
+ nom_process: 1.0;
+ nom_temperature: 25.0;
+ nom_voltage: 5.0;
+ output_threshold_pct_fall: 50.0;
+ output_threshold_pct_rise: 50.0;
+ pulling_resistance_unit: "1kohm";
+ slew_lower_threshold_pct_fall: 20.0;
+ slew_lower_threshold_pct_rise: 20.0;
+ slew_upper_threshold_pct_fall: 80.0;
+ slew_upper_threshold_pct_rise: 80.0;
+ time_unit: "1ns";
+ voltage_unit: "1V";
+ operating_conditions (typical) {
+ process: 1.0;
+ temperature: 25.0;
+ voltage: 5.0;
+ }
+ lu_table_template (delay_template_5x1) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: input_net_transition;
+ }
+ lu_table_template (delay_template_5x5) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_net_transition;
+ }
+ lu_table_template (delay_template_5x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_net_transition;
+ }
+ lu_table_template (delay_template_6x1) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: input_net_transition;
+ }
+ lu_table_template (delay_template_6x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_net_transition;
+ }
+ power_lut_template (energy_template_5x5) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_transition_time;
+ }
+ power_lut_template (energy_template_5x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_transition_time;
+ }
+ power_lut_template (energy_template_6x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_transition_time;
+ }
+ lu_table_template (hold_template_3x5) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (hold_template_3x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ power_lut_template (passive_energy_template_5x1) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: input_transition_time;
+ }
+ power_lut_template (passive_energy_template_6x1) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: input_transition_time;
+ }
+ lu_table_template (recovery_template_3x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (recovery_template_6x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (removal_template_3x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (setup_template_3x5) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (setup_template_3x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ cell (HAX1) {
+ area: 603504.0;
+ cell_leakage_power: 0.1173;
+ pin (B) {
+ capacitance: 0.009565996302413171;
+ direction: input;
+ fall_capacitance: 0.008432988155991751;
+ rise_capacitance: 0.010699004448834593;
+ }
+ pin (A) {
+ capacitance: 0.012290968093010312;
+ direction: input;
+ fall_capacitance: 0.013216336710577052;
+ rise_capacitance: 0.01136559947544357;
+ }
+ pin (YS) {
+ direction: output;
+ function: "(!(A & B + !A & !B))";
+ timing () {
+ related_pin: "B";
+ timing_sense: non_unate;
+ cell_rise (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.004033, 0.032150, 0.044845, 0.050474, 0.051335", \
+ "0.055892, 0.068037, 0.080785, 0.093045, 0.114132", \
+ "0.094044, 0.101015, 0.112537, 0.126712, 0.158920", \
+ "0.175648, 0.176204, 0.184990, 0.197179, 0.244777", \
+ "0.873435, 0.863339, 0.864298, 0.866078, 0.855109"
+ );
+ }
+ cell_fall (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.017244, 0.032461, 0.048132, 0.062118, 0.137542", \
+ "0.058835, 0.069633, 0.084719, 0.104232, 0.192012", \
+ "0.100970, 0.106394, 0.118870, 0.138651, 0.235211", \
+ "0.187793, 0.189005, 0.197350, 0.213800, 0.316894", \
+ "0.902163, 0.898308, 0.900032, 0.906364, 0.948955"
+ );
+ }
+ rise_transition (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.040974, 0.074951, 0.060349, 0.076555, 0.409013", \
+ "0.091957, 0.122622, 0.111250, 0.115255, 0.415747", \
+ "0.154170, 0.166605, 0.165996, 0.172579, 0.465956", \
+ "0.289870, 0.292343, 0.293138, 0.299508, 0.559512", \
+ "1.420665, 1.420862, 1.420515, 1.421028, 1.493654"
+ );
+ }
+ fall_transition (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.028737, 0.067929, 0.109033, 0.090482, 0.482822", \
+ "0.100377, 0.125774, 0.164469, 0.180526, 0.509483", \
+ "0.180975, 0.197032, 0.211922, 0.221778, 0.555289", \
+ "0.348738, 0.353197, 0.357789, 0.370377, 0.658930", \
+ "1.725367, 1.725946, 1.725663, 1.725932, 1.793771"
+ );
+ }
+ }
+ timing () {
+ related_pin: "A";
+ timing_sense: non_unate;
+ cell_rise (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "-0.002915, 0.042398, 0.052176, 0.055423, 0.107987", \
+ "0.062544, 0.079393, 0.088727, 0.101216, 0.163975", \
+ "0.098867, 0.112677, 0.121587, 0.133731, 0.204781", \
+ "0.178683, 0.187584, 0.195187, 0.205349, 0.275393", \
+ "0.873877, 0.874214, 0.876238, 0.875094, 0.864245"
+ );
+ }
+ cell_fall (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.018517, 0.033815, 0.052985, 0.063145, 0.108475", \
+ "0.059426, 0.069693, 0.089732, 0.106611, 0.160828", \
+ "0.101430, 0.106262, 0.124529, 0.143828, 0.205452", \
+ "0.188322, 0.188871, 0.203005, 0.222224, 0.292784", \
+ "0.902655, 0.898231, 0.905344, 0.918863, 0.964905"
+ );
+ }
+ rise_transition (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.048575, 0.056963, 0.055452, 0.077660, 0.348951", \
+ "0.097387, 0.109829, 0.107257, 0.116455, 0.374171", \
+ "0.157790, 0.160813, 0.162764, 0.173185, 0.415244", \
+ "0.289541, 0.291335, 0.292385, 0.299387, 0.509268", \
+ "1.420940, 1.420534, 1.420747, 1.420655, 1.464278"
+ );
+ }
+ fall_transition (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.029875, 0.067731, 0.077584, 0.067492, 0.350562", \
+ "0.099533, 0.125664, 0.168623, 0.123478, 0.376209", \
+ "0.180545, 0.196321, 0.205234, 0.198481, 0.424205", \
+ "0.348869, 0.353115, 0.356059, 0.358578, 0.546504", \
+ "1.725470, 1.725570, 1.725963, 1.725775, 1.781596"
+ );
+ }
+ }
+ }
+ pin (YC) {
+ direction: output;
+ function: "(A & B)";
+ timing () {
+ related_pin: "B";
+ timing_sense: positive_unate;
+ cell_rise (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "-0.002932, 0.031845, 0.046203, 0.059680, 0.206545", \
+ "0.049948, 0.068231, 0.085039, 0.104520, 0.274220", \
+ "0.089788, 0.101410, 0.117157, 0.136354, 0.323085", \
+ "0.173455, 0.176265, 0.188945, 0.205397, 0.412891", \
+ "0.873808, 0.861079, 0.865149, 0.869380, 0.984923"
+ );
+ }
+ cell_fall (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.020712, 0.024396, 0.025178, 0.022025, -0.060067", \
+ "0.060435, 0.061372, 0.064388, 0.066859, 0.006598", \
+ "0.103540, 0.102168, 0.102489, 0.103050, 0.053408", \
+ "0.191891, 0.188927, 0.186482, 0.180921, 0.136742", \
+ "0.906360, 0.902330, 0.897105, 0.883862, 0.767023"
+ );
+ }
+ rise_transition (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.029065, 0.076707, 0.058814, 0.085996, 0.589693", \
+ "0.084308, 0.124052, 0.114916, 0.121842, 0.582858", \
+ "0.150913, 0.169854, 0.170202, 0.177980, 0.592114", \
+ "0.289080, 0.293361, 0.294671, 0.299955, 0.642962", \
+ "1.420626, 1.420601, 1.420595, 1.420438, 1.521560"
+ );
+ }
+ fall_transition (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.023168, 0.037493, 0.061782, 0.104667, 0.614021", \
+ "0.093949, 0.101336, 0.115157, 0.147186, 0.632991", \
+ "0.178031, 0.179618, 0.188053, 0.212969, 0.683615", \
+ "0.349299, 0.349430, 0.351228, 0.362707, 0.786505", \
+ "1.724877, 1.725713, 1.726013, 1.726067, 1.845083"
+ );
+ }
+ }
+ timing () {
+ related_pin: "A";
+ timing_sense: positive_unate;
+ cell_rise (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "-0.002877, 0.029610, 0.051114, 0.071379, 0.191002", \
+ "0.048630, 0.065299, 0.090272, 0.109498, 0.261067", \
+ "0.088953, 0.098443, 0.122749, 0.144721, 0.312452", \
+ "0.173170, 0.173273, 0.195093, 0.217717, 0.411821", \
+ "0.874061, 0.858051, 0.871543, 0.889533, 1.026567"
+ );
+ }
+ cell_fall (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.022256, 0.026455, 0.029553, 0.031901, -0.015917", \
+ "0.062541, 0.063639, 0.067746, 0.071999, 0.041159", \
+ "0.104940, 0.104109, 0.105543, 0.107246, 0.080735", \
+ "0.192752, 0.190680, 0.189057, 0.184951, 0.147242", \
+ "0.907257, 0.903593, 0.899162, 0.887044, 0.752494"
+ );
+ }
+ rise_transition (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.026048, 0.073817, 0.050978, 0.065940, 0.443696", \
+ "0.083033, 0.121825, 0.103425, 0.102000, 0.436305", \
+ "0.150571, 0.172361, 0.163617, 0.164690, 0.449813", \
+ "0.288981, 0.293984, 0.293415, 0.294741, 0.517577", \
+ "1.420646, 1.420437, 1.420500, 1.420898, 1.486892"
+ );
+ }
+ fall_transition (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.025591, 0.040492, 0.065936, 0.108105, 0.550325", \
+ "0.095286, 0.101971, 0.117506, 0.150589, 0.584408", \
+ "0.179426, 0.180898, 0.189227, 0.214201, 0.625356", \
+ "0.348855, 0.349403, 0.351841, 0.363528, 0.724101", \
+ "1.724988, 1.724959, 1.726109, 1.725779, 1.806215"
+ );
+ }
+ }
+ }
+ }
+}
\ No newline at end of file
diff --git a/cells/lib/INV.lib b/cells/lib/INV.lib
new file mode 100644
index 0000000..246f6c2
--- /dev/null
+++ b/cells/lib/INV.lib
@@ -0,0 +1,259 @@
+library (ls05_stdcells) {
+ capacitive_load_unit (1.0, pf);
+ current_unit: "1uA";
+ default_operating_conditions: typical;
+ delay_model: table_lookup;
+ in_place_swap_mode: match_footprint;
+ input_threshold_pct_fall: 50.0;
+ input_threshold_pct_rise: 50.0;
+ leakage_power_unit: "1nW";
+ nom_process: 1.0;
+ nom_temperature: 25.0;
+ nom_voltage: 5.0;
+ output_threshold_pct_fall: 50.0;
+ output_threshold_pct_rise: 50.0;
+ pulling_resistance_unit: "1kohm";
+ slew_lower_threshold_pct_fall: 20.0;
+ slew_lower_threshold_pct_rise: 20.0;
+ slew_upper_threshold_pct_fall: 80.0;
+ slew_upper_threshold_pct_rise: 80.0;
+ time_unit: "1ns";
+ voltage_unit: "1V";
+ operating_conditions (typical) {
+ process: 1.0;
+ temperature: 25.0;
+ voltage: 5.0;
+ }
+ lu_table_template (delay_template_5x1) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: input_net_transition;
+ }
+ lu_table_template (delay_template_5x5) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_net_transition;
+ }
+ lu_table_template (delay_template_5x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_net_transition;
+ }
+ lu_table_template (delay_template_6x1) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: input_net_transition;
+ }
+ lu_table_template (delay_template_6x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_net_transition;
+ }
+ power_lut_template (energy_template_5x5) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_transition_time;
+ }
+ power_lut_template (energy_template_5x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_transition_time;
+ }
+ power_lut_template (energy_template_6x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_transition_time;
+ }
+ lu_table_template (hold_template_3x5) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (hold_template_3x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ power_lut_template (passive_energy_template_5x1) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: input_transition_time;
+ }
+ power_lut_template (passive_energy_template_6x1) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: input_transition_time;
+ }
+ lu_table_template (recovery_template_3x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (recovery_template_6x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (removal_template_3x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (setup_template_3x5) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (setup_template_3x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ cell (INV) {
+ area: 109728.0;
+ cell_leakage_power: 0.1173;
+ pin (A) {
+ capacitance: 0.007547126607243736;
+ direction: input;
+ fall_capacitance: 0.008904762554228705;
+ rise_capacitance: 0.0061894906602587675;
+ }
+ pin (Y) {
+ direction: output;
+ function: "(!A)";
+ timing () {
+ related_pin: "A";
+ timing_sense: negative_unate;
+ cell_rise (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.005045, 0.004666, 0.003429, -0.000859, -0.065505", \
+ "0.044989, 0.042725, 0.047543, 0.051692, 0.040256", \
+ "0.088909, 0.082182, 0.082392, 0.089237, 0.111465", \
+ "0.176860, 0.166922, 0.160768, 0.159204, 0.223911", \
+ "0.881893, 0.869050, 0.853857, 0.827782, 0.824694"
+ );
+ }
+ cell_fall (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.005563, 0.008612, 0.012339, 0.017358, 0.087849", \
+ "0.046446, 0.047702, 0.053516, 0.064252, 0.179451", \
+ "0.090922, 0.089928, 0.091895, 0.103197, 0.242872", \
+ "0.179772, 0.177219, 0.176091, 0.179128, 0.343479", \
+ "0.895275, 0.891758, 0.887322, 0.880070, 0.928854"
+ );
+ }
+ rise_transition (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.008037, 0.028704, 0.054668, 0.109521, 0.869966", \
+ "0.076055, 0.081921, 0.097573, 0.140257, 0.863906", \
+ "0.147843, 0.149496, 0.158979, 0.188238, 0.862306", \
+ "0.288563, 0.287255, 0.290237, 0.307382, 0.902900", \
+ "1.419778, 1.420153, 1.419732, 1.419717, 1.673889"
+ );
+ }
+ fall_transition (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.008767, 0.031084, 0.058052, 0.115960, 0.868417", \
+ "0.090912, 0.096720, 0.111536, 0.155787, 0.875627", \
+ "0.176967, 0.177851, 0.188412, 0.219917, 0.899333", \
+ "0.347603, 0.347624, 0.351003, 0.368838, 0.971602", \
+ "1.725267, 1.725008, 1.725609, 1.725893, 1.975591"
+ );
+ }
+ }
+ }
+ }
+}
\ No newline at end of file
diff --git a/cells/lib/INVX1.lib b/cells/lib/INVX1.lib
new file mode 100644
index 0000000..e52416f
--- /dev/null
+++ b/cells/lib/INVX1.lib
@@ -0,0 +1,259 @@
+library (ls05_stdcells) {
+ capacitive_load_unit (1.0, pf);
+ current_unit: "1uA";
+ default_operating_conditions: typical;
+ delay_model: table_lookup;
+ in_place_swap_mode: match_footprint;
+ input_threshold_pct_fall: 50.0;
+ input_threshold_pct_rise: 50.0;
+ leakage_power_unit: "1nW";
+ nom_process: 1.0;
+ nom_temperature: 25.0;
+ nom_voltage: 5.0;
+ output_threshold_pct_fall: 50.0;
+ output_threshold_pct_rise: 50.0;
+ pulling_resistance_unit: "1kohm";
+ slew_lower_threshold_pct_fall: 20.0;
+ slew_lower_threshold_pct_rise: 20.0;
+ slew_upper_threshold_pct_fall: 80.0;
+ slew_upper_threshold_pct_rise: 80.0;
+ time_unit: "1ns";
+ voltage_unit: "1V";
+ operating_conditions (typical) {
+ process: 1.0;
+ temperature: 25.0;
+ voltage: 5.0;
+ }
+ lu_table_template (delay_template_5x1) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: input_net_transition;
+ }
+ lu_table_template (delay_template_5x5) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_net_transition;
+ }
+ lu_table_template (delay_template_5x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_net_transition;
+ }
+ lu_table_template (delay_template_6x1) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: input_net_transition;
+ }
+ lu_table_template (delay_template_6x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_net_transition;
+ }
+ power_lut_template (energy_template_5x5) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_transition_time;
+ }
+ power_lut_template (energy_template_5x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_transition_time;
+ }
+ power_lut_template (energy_template_6x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_transition_time;
+ }
+ lu_table_template (hold_template_3x5) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (hold_template_3x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ power_lut_template (passive_energy_template_5x1) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: input_transition_time;
+ }
+ power_lut_template (passive_energy_template_6x1) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: input_transition_time;
+ }
+ lu_table_template (recovery_template_3x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (recovery_template_6x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (removal_template_3x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (setup_template_3x5) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (setup_template_3x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ cell (INVX1) {
+ area: 109728.0;
+ cell_leakage_power: 0.1173;
+ pin (A) {
+ capacitance: 0.007547126607243736;
+ direction: input;
+ fall_capacitance: 0.008904762554228705;
+ rise_capacitance: 0.0061894906602587675;
+ }
+ pin (Y) {
+ direction: output;
+ function: "(!A)";
+ timing () {
+ related_pin: "A";
+ timing_sense: negative_unate;
+ cell_rise (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.005045, 0.004666, 0.003429, -0.000859, -0.065505", \
+ "0.044989, 0.042725, 0.047543, 0.051692, 0.040256", \
+ "0.088909, 0.082182, 0.082392, 0.089237, 0.111465", \
+ "0.176860, 0.166922, 0.160768, 0.159204, 0.223911", \
+ "0.881893, 0.869050, 0.853857, 0.827782, 0.824694"
+ );
+ }
+ cell_fall (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.005563, 0.008612, 0.012339, 0.017358, 0.087849", \
+ "0.046446, 0.047702, 0.053516, 0.064252, 0.179451", \
+ "0.090922, 0.089928, 0.091895, 0.103197, 0.242872", \
+ "0.179772, 0.177219, 0.176091, 0.179128, 0.343479", \
+ "0.895275, 0.891758, 0.887322, 0.880070, 0.928854"
+ );
+ }
+ rise_transition (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.008037, 0.028704, 0.054668, 0.109521, 0.869966", \
+ "0.076055, 0.081921, 0.097573, 0.140257, 0.863906", \
+ "0.147843, 0.149496, 0.158979, 0.188238, 0.862306", \
+ "0.288563, 0.287255, 0.290237, 0.307382, 0.902900", \
+ "1.419778, 1.420153, 1.419732, 1.419717, 1.673889"
+ );
+ }
+ fall_transition (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.008767, 0.031084, 0.058052, 0.115960, 0.868417", \
+ "0.090912, 0.096720, 0.111536, 0.155787, 0.875627", \
+ "0.176967, 0.177851, 0.188412, 0.219917, 0.899333", \
+ "0.347603, 0.347624, 0.351003, 0.368838, 0.971602", \
+ "1.725267, 1.725008, 1.725609, 1.725893, 1.975591"
+ );
+ }
+ }
+ }
+ }
+}
\ No newline at end of file
diff --git a/cells/lib/INVX2.lib b/cells/lib/INVX2.lib
new file mode 100644
index 0000000..c8b1fd4
--- /dev/null
+++ b/cells/lib/INVX2.lib
@@ -0,0 +1,259 @@
+library (ls05_stdcells) {
+ capacitive_load_unit (1.0, pf);
+ current_unit: "1uA";
+ default_operating_conditions: typical;
+ delay_model: table_lookup;
+ in_place_swap_mode: match_footprint;
+ input_threshold_pct_fall: 50.0;
+ input_threshold_pct_rise: 50.0;
+ leakage_power_unit: "1nW";
+ nom_process: 1.0;
+ nom_temperature: 25.0;
+ nom_voltage: 5.0;
+ output_threshold_pct_fall: 50.0;
+ output_threshold_pct_rise: 50.0;
+ pulling_resistance_unit: "1kohm";
+ slew_lower_threshold_pct_fall: 20.0;
+ slew_lower_threshold_pct_rise: 20.0;
+ slew_upper_threshold_pct_fall: 80.0;
+ slew_upper_threshold_pct_rise: 80.0;
+ time_unit: "1ns";
+ voltage_unit: "1V";
+ operating_conditions (typical) {
+ process: 1.0;
+ temperature: 25.0;
+ voltage: 5.0;
+ }
+ lu_table_template (delay_template_5x1) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: input_net_transition;
+ }
+ lu_table_template (delay_template_5x5) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_net_transition;
+ }
+ lu_table_template (delay_template_5x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_net_transition;
+ }
+ lu_table_template (delay_template_6x1) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: input_net_transition;
+ }
+ lu_table_template (delay_template_6x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_net_transition;
+ }
+ power_lut_template (energy_template_5x5) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_transition_time;
+ }
+ power_lut_template (energy_template_5x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_transition_time;
+ }
+ power_lut_template (energy_template_6x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_transition_time;
+ }
+ lu_table_template (hold_template_3x5) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (hold_template_3x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ power_lut_template (passive_energy_template_5x1) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: input_transition_time;
+ }
+ power_lut_template (passive_energy_template_6x1) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: input_transition_time;
+ }
+ lu_table_template (recovery_template_3x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (recovery_template_6x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (removal_template_3x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (setup_template_3x5) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (setup_template_3x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ cell (INVX2) {
+ area: 109728.0;
+ cell_leakage_power: 0.1173;
+ pin (A) {
+ capacitance: 0.007547126607243736;
+ direction: input;
+ fall_capacitance: 0.008904762554228705;
+ rise_capacitance: 0.0061894906602587675;
+ }
+ pin (Y) {
+ direction: output;
+ function: "(!A)";
+ timing () {
+ related_pin: "A";
+ timing_sense: negative_unate;
+ cell_rise (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.005045, 0.004666, 0.003429, -0.000859, -0.065505", \
+ "0.044989, 0.042725, 0.047543, 0.051692, 0.040256", \
+ "0.088909, 0.082182, 0.082392, 0.089237, 0.111465", \
+ "0.176860, 0.166922, 0.160768, 0.159204, 0.223911", \
+ "0.881893, 0.869050, 0.853857, 0.827782, 0.824694"
+ );
+ }
+ cell_fall (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.005563, 0.008612, 0.012339, 0.017358, 0.087849", \
+ "0.046446, 0.047702, 0.053516, 0.064252, 0.179451", \
+ "0.090922, 0.089928, 0.091895, 0.103197, 0.242872", \
+ "0.179772, 0.177219, 0.176091, 0.179128, 0.343479", \
+ "0.895275, 0.891758, 0.887322, 0.880070, 0.928854"
+ );
+ }
+ rise_transition (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.008037, 0.028704, 0.054668, 0.109521, 0.869966", \
+ "0.076055, 0.081921, 0.097573, 0.140257, 0.863906", \
+ "0.147843, 0.149496, 0.158979, 0.188238, 0.862306", \
+ "0.288563, 0.287255, 0.290237, 0.307382, 0.902900", \
+ "1.419778, 1.420153, 1.419732, 1.419717, 1.673889"
+ );
+ }
+ fall_transition (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.008767, 0.031084, 0.058052, 0.115960, 0.868417", \
+ "0.090912, 0.096720, 0.111536, 0.155787, 0.875627", \
+ "0.176967, 0.177851, 0.188412, 0.219917, 0.899333", \
+ "0.347603, 0.347624, 0.351003, 0.368838, 0.971602", \
+ "1.725267, 1.725008, 1.725609, 1.725893, 1.975591"
+ );
+ }
+ }
+ }
+ }
+}
\ No newline at end of file
diff --git a/cells/lib/INVX4.lib b/cells/lib/INVX4.lib
new file mode 100644
index 0000000..7de56db
--- /dev/null
+++ b/cells/lib/INVX4.lib
@@ -0,0 +1,259 @@
+library (ls05_stdcells) {
+ capacitive_load_unit (1.0, pf);
+ current_unit: "1uA";
+ default_operating_conditions: typical;
+ delay_model: table_lookup;
+ in_place_swap_mode: match_footprint;
+ input_threshold_pct_fall: 50.0;
+ input_threshold_pct_rise: 50.0;
+ leakage_power_unit: "1nW";
+ nom_process: 1.0;
+ nom_temperature: 25.0;
+ nom_voltage: 5.0;
+ output_threshold_pct_fall: 50.0;
+ output_threshold_pct_rise: 50.0;
+ pulling_resistance_unit: "1kohm";
+ slew_lower_threshold_pct_fall: 20.0;
+ slew_lower_threshold_pct_rise: 20.0;
+ slew_upper_threshold_pct_fall: 80.0;
+ slew_upper_threshold_pct_rise: 80.0;
+ time_unit: "1ns";
+ voltage_unit: "1V";
+ operating_conditions (typical) {
+ process: 1.0;
+ temperature: 25.0;
+ voltage: 5.0;
+ }
+ lu_table_template (delay_template_5x1) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: input_net_transition;
+ }
+ lu_table_template (delay_template_5x5) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_net_transition;
+ }
+ lu_table_template (delay_template_5x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_net_transition;
+ }
+ lu_table_template (delay_template_6x1) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: input_net_transition;
+ }
+ lu_table_template (delay_template_6x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_net_transition;
+ }
+ power_lut_template (energy_template_5x5) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_transition_time;
+ }
+ power_lut_template (energy_template_5x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_transition_time;
+ }
+ power_lut_template (energy_template_6x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_transition_time;
+ }
+ lu_table_template (hold_template_3x5) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (hold_template_3x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ power_lut_template (passive_energy_template_5x1) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: input_transition_time;
+ }
+ power_lut_template (passive_energy_template_6x1) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: input_transition_time;
+ }
+ lu_table_template (recovery_template_3x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (recovery_template_6x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (removal_template_3x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (setup_template_3x5) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (setup_template_3x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ cell (INVX4) {
+ area: 164592.0;
+ cell_leakage_power: 0.1173;
+ pin (A) {
+ capacitance: 0.013438478664617209;
+ direction: input;
+ fall_capacitance: 0.014499779614899311;
+ rise_capacitance: 0.012377177714335106;
+ }
+ pin (Y) {
+ direction: output;
+ function: "(!A)";
+ timing () {
+ related_pin: "A";
+ timing_sense: negative_unate;
+ cell_rise (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.004836, 0.004170, 0.002946, -0.001907, -0.066292", \
+ "0.023946, 0.025031, 0.028842, 0.029915, -0.004484", \
+ "0.044976, 0.042290, 0.047609, 0.052305, 0.040052", \
+ "0.088868, 0.082479, 0.082214, 0.089172, 0.111518", \
+ "0.440751, 0.428400, 0.415953, 0.398459, 0.482872"
+ );
+ }
+ cell_fall (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.005423, 0.008336, 0.011970, 0.017170, 0.086980", \
+ "0.025140, 0.028622, 0.035186, 0.044099, 0.141159", \
+ "0.046446, 0.047702, 0.053516, 0.064252, 0.179451", \
+ "0.090922, 0.089928, 0.091895, 0.103197, 0.242872", \
+ "0.447493, 0.444138, 0.440746, 0.435821, 0.578747"
+ );
+ }
+ rise_transition (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.007775, 0.028100, 0.055227, 0.108927, 0.869985", \
+ "0.039255, 0.049723, 0.072334, 0.124573, 0.866617", \
+ "0.075493, 0.083261, 0.096610, 0.140261, 0.863292", \
+ "0.146557, 0.148054, 0.158526, 0.188166, 0.862332", \
+ "0.712012, 0.711126, 0.711929, 0.712879, 1.131106"
+ );
+ }
+ fall_transition (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.008278, 0.030935, 0.057869, 0.115738, 0.868418", \
+ "0.047073, 0.058001, 0.079823, 0.131936, 0.871905", \
+ "0.090912, 0.096720, 0.111536, 0.155787, 0.875627", \
+ "0.176967, 0.177851, 0.188412, 0.219917, 0.899333", \
+ "0.863260, 0.862553, 0.864134, 0.865563, 1.291606"
+ );
+ }
+ }
+ }
+ }
+}
\ No newline at end of file
diff --git a/cells/lib/INVX8.lib b/cells/lib/INVX8.lib
new file mode 100644
index 0000000..fb74746
--- /dev/null
+++ b/cells/lib/INVX8.lib
@@ -0,0 +1,259 @@
+library (ls05_stdcells) {
+ capacitive_load_unit (1.0, pf);
+ current_unit: "1uA";
+ default_operating_conditions: typical;
+ delay_model: table_lookup;
+ in_place_swap_mode: match_footprint;
+ input_threshold_pct_fall: 50.0;
+ input_threshold_pct_rise: 50.0;
+ leakage_power_unit: "1nW";
+ nom_process: 1.0;
+ nom_temperature: 25.0;
+ nom_voltage: 5.0;
+ output_threshold_pct_fall: 50.0;
+ output_threshold_pct_rise: 50.0;
+ pulling_resistance_unit: "1kohm";
+ slew_lower_threshold_pct_fall: 20.0;
+ slew_lower_threshold_pct_rise: 20.0;
+ slew_upper_threshold_pct_fall: 80.0;
+ slew_upper_threshold_pct_rise: 80.0;
+ time_unit: "1ns";
+ voltage_unit: "1V";
+ operating_conditions (typical) {
+ process: 1.0;
+ temperature: 25.0;
+ voltage: 5.0;
+ }
+ lu_table_template (delay_template_5x1) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: input_net_transition;
+ }
+ lu_table_template (delay_template_5x5) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_net_transition;
+ }
+ lu_table_template (delay_template_5x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_net_transition;
+ }
+ lu_table_template (delay_template_6x1) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: input_net_transition;
+ }
+ lu_table_template (delay_template_6x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_net_transition;
+ }
+ power_lut_template (energy_template_5x5) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_transition_time;
+ }
+ power_lut_template (energy_template_5x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_transition_time;
+ }
+ power_lut_template (energy_template_6x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: total_output_net_capacitance;
+ variable_2: input_transition_time;
+ }
+ lu_table_template (hold_template_3x5) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (hold_template_3x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ power_lut_template (passive_energy_template_5x1) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: input_transition_time;
+ }
+ power_lut_template (passive_energy_template_6x1) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: input_transition_time;
+ }
+ lu_table_template (recovery_template_3x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (recovery_template_6x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (removal_template_3x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (setup_template_3x5) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ lu_table_template (setup_template_3x6) {
+ index_1 (
+ "1000.0, 1001.0, 1002.0"
+ );
+ index_2 (
+ "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
+ );
+ variable_1: related_pin_transition;
+ variable_2: constrained_pin_transition;
+ }
+ cell (INVX8) {
+ area: 274320.0;
+ cell_leakage_power: 0.1173;
+ pin (A) {
+ capacitance: 0.0252218232768479;
+ direction: input;
+ fall_capacitance: 0.02568994035979349;
+ rise_capacitance: 0.024753706193902308;
+ }
+ pin (Y) {
+ direction: output;
+ function: "(!A)";
+ timing () {
+ related_pin: "A";
+ timing_sense: negative_unate;
+ cell_rise (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.004711, 0.004036, 0.002690, -0.002338, -0.066683", \
+ "0.013476, 0.015921, 0.017776, 0.016979, -0.030765", \
+ "0.023708, 0.025226, 0.028773, 0.029840, -0.004496", \
+ "0.044997, 0.042811, 0.047615, 0.051364, 0.040057", \
+ "0.220573, 0.210103, 0.201918, 0.196471, 0.273011"
+ );
+ }
+ cell_fall (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.005356, 0.008195, 0.011786, 0.017076, 0.086545", \
+ "0.014445, 0.019292, 0.024680, 0.028468, 0.116656", \
+ "0.025140, 0.028622, 0.035186, 0.044099, 0.141159", \
+ "0.046446, 0.047702, 0.053516, 0.064252, 0.179451", \
+ "0.224189, 0.221188, 0.219510, 0.220049, 0.387314"
+ );
+ }
+ rise_transition (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.007647, 0.027974, 0.055611, 0.108999, 0.869977", \
+ "0.022594, 0.037470, 0.063051, 0.115180, 0.867738", \
+ "0.039486, 0.049806, 0.072127, 0.121312, 0.866717", \
+ "0.076785, 0.082234, 0.096608, 0.138992, 0.863329", \
+ "0.358088, 0.358712, 0.359243, 0.372101, 0.930596"
+ );
+ }
+ fall_transition (delay_template_5x5) {
+ index_1 (
+ "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
+ );
+ index_2 (
+ "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
+ );
+ values (
+ "0.008160, 0.030855, 0.057683, 0.115626, 0.868400", \
+ "0.027538, 0.041822, 0.066894, 0.123555, 0.870026", \
+ "0.047073, 0.058001, 0.079823, 0.131936, 0.871905", \
+ "0.090912, 0.096720, 0.111536, 0.155787, 0.875627", \
+ "0.433842, 0.432463, 0.434875, 0.448234, 1.015267"
+ );
+ }
+ }
+ }
+ }
+}
\ No newline at end of file
diff --git a/cells/lib/libresilicon.lib b/cells/lib/libresilicon.lib
new file mode 100644
index 0000000..27a2e79
--- /dev/null
+++ b/cells/lib/libresilicon.lib
@@ -0,0 +1 @@
+library (ls05_stdcells) { capacitive_load_unit (1.0, pf); current_unit: "1uA"; default_operating_conditions: typical; delay_model: table_lookup; in_place_swap_mode: match_footprint; input_threshold_pct_fall: 50.0; input_threshold_pct_rise: 50.0; leakage_power_unit: "1nW"; nom_process: 1.0; nom_temperature: 25.0; nom_voltage: 5.0; output_threshold_pct_fall: 50.0; output_threshold_pct_rise: 50.0; pulling_resistance_unit: "1kohm"; slew_lower_threshold_pct_fall: 20.0; slew_lower_threshold_pct_rise: 20.0; slew_upper_threshold_pct_fall: 80.0; slew_upper_threshold_pct_rise: 80.0; time_unit: "1ns"; voltage_unit: "1V"; operating_conditions (typical) { process: 1.0; temperature: 25.0; voltage: 5.0; } lu_table_template (delay_template_5x1) { index_1 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0" ); variable_1: input_net_transition; } lu_table_template (delay_template_5x5) { index_1 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0" ); index_2 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0" ); variable_1: total_output_net_capacitance; variable_2: input_net_transition; } lu_table_template (delay_template_5x6) { index_1 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0" ); index_2 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0" ); variable_1: total_output_net_capacitance; variable_2: input_net_transition; } lu_table_template (delay_template_6x1) { index_1 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0" ); variable_1: input_net_transition; } lu_table_template (delay_template_6x6) { index_1 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0" ); index_2 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0" ); variable_1: total_output_net_capacitance; variable_2: input_net_transition; } power_lut_template (energy_template_5x5) { index_1 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0" ); index_2 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0" ); variable_1: total_output_net_capacitance; variable_2: input_transition_time; } power_lut_template (energy_template_5x6) { index_1 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0" ); index_2 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0" ); variable_1: total_output_net_capacitance; variable_2: input_transition_time; } power_lut_template (energy_template_6x6) { index_1 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0" ); index_2 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0" ); variable_1: total_output_net_capacitance; variable_2: input_transition_time; } lu_table_template (hold_template_3x5) { index_1 ( "1000.0, 1001.0, 1002.0" ); index_2 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0" ); variable_1: related_pin_transition; variable_2: constrained_pin_transition; } lu_table_template (hold_template_3x6) { index_1 ( "1000.0, 1001.0, 1002.0" ); index_2 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0" ); variable_1: related_pin_transition; variable_2: constrained_pin_transition; } power_lut_template (passive_energy_template_5x1) { index_1 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0" ); variable_1: input_transition_time; } power_lut_template (passive_energy_template_6x1) { index_1 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0" ); variable_1: input_transition_time; } lu_table_template (recovery_template_3x6) { index_1 ( "1000.0, 1001.0, 1002.0" ); index_2 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0" ); variable_1: related_pin_transition; variable_2: constrained_pin_transition; } lu_table_template (recovery_template_6x6) { index_1 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0" ); index_2 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0" ); variable_1: related_pin_transition; variable_2: constrained_pin_transition; } lu_table_template (removal_template_3x6) { index_1 ( "1000.0, 1001.0, 1002.0" ); index_2 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0" ); variable_1: related_pin_transition; variable_2: constrained_pin_transition; } lu_table_template (setup_template_3x5) { index_1 ( "1000.0, 1001.0, 1002.0" ); index_2 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0" ); variable_1: related_pin_transition; variable_2: constrained_pin_transition; } lu_table_template (setup_template_3x6) { index_1 ( "1000.0, 1001.0, 1002.0" ); index_2 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0" ); variable_1: related_pin_transition; variable_2: constrained_pin_transition; } cell (INVX1) { pg_pin (vdd) { voltage_name : "vdd"; pg_type : "primary_power"; } pg_pin (gnd) { voltage_name : "gnd"; pg_type : "primary_ground"; } area: 109728.0; cell_leakage_power: 0.1173; pin (A) { capacitance: 0.007547126607243736; direction: input; fall_capacitance: 0.008904762554228705; rise_capacitance: 0.0061894906602587675; } pin (Y) { direction: output; function: "(!A)"; timing () { related_pin: "A"; timing_sense: negative_unate; cell_rise (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.005045, 0.004666, 0.003429, -0.000859, -0.065505", "0.044989, 0.042725, 0.047543, 0.051692, 0.040256", "0.088909, 0.082182, 0.082392, 0.089237, 0.111465", "0.176860, 0.166922, 0.160768, 0.159204, 0.223911", "0.881893, 0.869050, 0.853857, 0.827782, 0.824694" ); } cell_fall (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.005563, 0.008612, 0.012339, 0.017358, 0.087849", "0.046446, 0.047702, 0.053516, 0.064252, 0.179451", "0.090922, 0.089928, 0.091895, 0.103197, 0.242872", "0.179772, 0.177219, 0.176091, 0.179128, 0.343479", "0.895275, 0.891758, 0.887322, 0.880070, 0.928854" ); } rise_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.008037, 0.028704, 0.054668, 0.109521, 0.869966", "0.076055, 0.081921, 0.097573, 0.140257, 0.863906", "0.147843, 0.149496, 0.158979, 0.188238, 0.862306", "0.288563, 0.287255, 0.290237, 0.307382, 0.902900", "1.419778, 1.420153, 1.419732, 1.419717, 1.673889" ); } fall_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.008767, 0.031084, 0.058052, 0.115960, 0.868417", "0.090912, 0.096720, 0.111536, 0.155787, 0.875627", "0.176967, 0.177851, 0.188412, 0.219917, 0.899333", "0.347603, 0.347624, 0.351003, 0.368838, 0.971602", "1.725267, 1.725008, 1.725609, 1.725893, 1.975591" ); } } } }}
\ No newline at end of file
diff --git a/cells/lib/removenl.pl b/cells/lib/removenl.pl
new file mode 100644
index 0000000..7c69822
--- /dev/null
+++ b/cells/lib/removenl.pl
@@ -0,0 +1,15 @@
+#!/usr/bin/perl -w
+
+open IN,"<libresilicon.lib";
+undef $/;
+my $content=<IN>;
+$content=~s/area/pg_pin (vdd) { voltage_name : "vdd"; pg_type : "primary_power"; } pg_pin (gnd) { voltage_name : "gnd"; pg_type : "primary_ground"; } area/g;
+
+#$content=~s/"\s*\n/"/gs;
+#$content=~s/;\s*\n/;/gs;
+$content=~s/\n//gs;
+$content=~s/\\//gs;
+
+
+
+print $content;
diff --git a/cells/mag/AND2X1.mag b/cells/mag/AND2X1.mag
new file mode 100644
index 0000000..31270cf
--- /dev/null
+++ b/cells/mag/AND2X1.mag
@@ -0,0 +1,156 @@
+magic
+# Generated by librecell
+tech sky130A
+timestamp 1621171374
+<< nwell >>
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+<< viali >>
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+<< nplus >>
+<< pplus >>
+<< labels >>
+rlabel met1 0 309 576 357 0 VDD
+port 1 se
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+rlabel met1 274 175 303 204 0 B
+port 11 se
+<< end >>
diff --git a/cells/mag/AND2X2.mag b/cells/mag/AND2X2.mag
new file mode 100644
index 0000000..8e5ff77
--- /dev/null
+++ b/cells/mag/AND2X2.mag
@@ -0,0 +1,158 @@
+magic
+# Generated by librecell
+tech sky130A
+timestamp 1621171631
+<< nwell >>
+rect 0 179 576 333
+rect 27 333 550 340
+<< viali >>
+rect 328 19 345 36
+rect 376 19 393 36
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+rect 184 221 201 238
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+<< met1 >>
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+<< nplus >>
+<< pplus >>
+<< labels >>
+rlabel met1 0 309 576 357 0 VDD
+port 1 se
+rlabel met1 0 -24 576 24 0 GND
+port 2 se
+rlabel met1 466 40 495 69 0 Y
+port 3 se
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+port 4 se
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+port 5 se
+rlabel met1 274 80 303 109 0 B
+port 6 se
+rlabel met1 281 109 295 175 0 B
+port 7 se
+rlabel met1 274 175 303 204 0 B
+port 8 se
+rlabel met1 130 80 159 109 0 A
+port 9 se
+rlabel met1 137 109 151 175 0 A
+port 10 se
+rlabel met1 130 175 159 204 0 A
+port 11 se
+<< end >>
diff --git a/cells/mag/AOI21X1.mag b/cells/mag/AOI21X1.mag
new file mode 100644
index 0000000..a7e24e6
--- /dev/null
+++ b/cells/mag/AOI21X1.mag
@@ -0,0 +1,182 @@
+magic
+# Generated by librecell
+tech sky130A
+timestamp 1621171877
+<< nwell >>
+rect 0 179 576 333
+rect 27 333 550 340
+<< viali >>
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+rect 88 46 105 63
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+<< properties >>
+string FIXED_BBOX 0 0 576 333
+<< li1 >>
+rect 200 11 257 44
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+<< met1 >>
+<< li1 >>
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+<< pplus >>
+<< labels >>
+rlabel met1 0 309 576 357 0 VDD
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+rlabel met1 82 40 111 47 0 Y
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+rlabel met1 466 40 495 47 0 Y
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+<< end >>
diff --git a/cells/mag/AOI22X1.mag b/cells/mag/AOI22X1.mag
new file mode 100644
index 0000000..7758a0b
--- /dev/null
+++ b/cells/mag/AOI22X1.mag
@@ -0,0 +1,210 @@
+magic
+# Generated by librecell
+tech sky130A
+timestamp 1621172355
+<< nwell >>
+rect 0 179 720 333
+rect 27 333 694 340
+<< viali >>
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+<< li1 >>
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+<< met1 >>
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+<< nplus >>
+<< pplus >>
+<< labels >>
+rlabel met1 0 309 720 357 0 VDD
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+<< end >>
diff --git a/cells/mag/BUFX2.mag b/cells/mag/BUFX2.mag
new file mode 100644
index 0000000..dfde1c5
--- /dev/null
+++ b/cells/mag/BUFX2.mag
@@ -0,0 +1,111 @@
+magic
+# Generated by librecell
+tech sky130A
+timestamp 1621173095
+<< nwell >>
+rect 0 179 432 333
+rect 27 333 406 340
+<< viali >>
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+<< li1 >>
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+<< met1 >>
+<< li1 >>
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+<< polycont >>
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+<< labels >>
+rlabel met1 0 309 432 357 0 VDD
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+<< end >>
diff --git a/cells/mag/BUFX4.mag b/cells/mag/BUFX4.mag
new file mode 100644
index 0000000..9fb70c5
--- /dev/null
+++ b/cells/mag/BUFX4.mag
@@ -0,0 +1,174 @@
+magic
+# Generated by librecell
+tech sky130A
+timestamp 1621173301
+<< nwell >>
+rect 0 179 576 333
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+<< viali >>
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+<< end >>
diff --git a/cells/mag/CLKBUF1.mag b/cells/mag/CLKBUF1.mag
new file mode 100644
index 0000000..277d143
--- /dev/null
+++ b/cells/mag/CLKBUF1.mag
@@ -0,0 +1,370 @@
+magic
+# Generated by librecell
+tech sky130A
+timestamp 1621174286
+<< nwell >>
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+<< viali >>
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+<< ndiffusion >>
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+<< pdiffusion >>
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+<< polycont >>
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+<< pdiffc >>
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+<< end >>
diff --git a/cells/mag/HAX1.mag b/cells/mag/HAX1.mag
new file mode 100644
index 0000000..1d38158
--- /dev/null
+++ b/cells/mag/HAX1.mag
@@ -0,0 +1,359 @@
+magic
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+tech sky130A
+timestamp 1621175334
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+<< end >>
diff --git a/cells/mag/INV.mag b/cells/mag/INV.mag
new file mode 100644
index 0000000..dea8d67
--- /dev/null
+++ b/cells/mag/INV.mag
@@ -0,0 +1,88 @@
+magic
+# Generated by librecell
+tech sky130A
+timestamp 1621175710
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+<< end >>
diff --git a/cells/mag/INVX1.mag b/cells/mag/INVX1.mag
new file mode 100644
index 0000000..1c42d38
--- /dev/null
+++ b/cells/mag/INVX1.mag
@@ -0,0 +1,88 @@
+magic
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+tech sky130A
+timestamp 1620330136
+<< nwell >>
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+<< viali >>
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+<< end >>
diff --git a/cells/mag/INVX2.mag b/cells/mag/INVX2.mag
new file mode 100644
index 0000000..5105b3a
--- /dev/null
+++ b/cells/mag/INVX2.mag
@@ -0,0 +1,88 @@
+magic
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+tech sky130A
+timestamp 1621175817
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+<< end >>
diff --git a/cells/mag/INVX4.mag b/cells/mag/INVX4.mag
new file mode 100644
index 0000000..54aa9c6
--- /dev/null
+++ b/cells/mag/INVX4.mag
@@ -0,0 +1,164 @@
+magic
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+tech sky130A
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+<< end >>
diff --git a/cells/mag/INVX8.mag b/cells/mag/INVX8.mag
new file mode 100644
index 0000000..cc3040a
--- /dev/null
+++ b/cells/mag/INVX8.mag
@@ -0,0 +1,278 @@
+magic
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+tech sky130A
+timestamp 1621176318
+<< nwell >>
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+<< ndiffusion >>
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+<< pdiffusion >>
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+<< polycont >>
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+<< nplus >>
+<< pplus >>
+<< labels >>
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+port 1 se
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+rlabel met1 82 40 111 47 0 Y
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+rlabel met1 130 80 159 88 0 A
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+port 35 se
+rlabel met1 562 175 591 204 0 A
+port 36 se
+<< end >>
diff --git a/cells/mag/LATCH.mag b/cells/mag/LATCH.mag
new file mode 100644
index 0000000..c1efe44
--- /dev/null
+++ b/cells/mag/LATCH.mag
@@ -0,0 +1,254 @@
+magic
+# Generated by librecell
+tech sky130A
+timestamp 1621176781
+<< nwell >>
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+rect 27 333 982 340
+<< viali >>
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+<< poly >>
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+rect 848 173 881 206
+rect 857 206 872 330
+<< properties >>
+string FIXED_BBOX 0 0 1008 333
+<< li1 >>
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+<< li1 >>
+<< met1 >>
+<< li1 >>
+<< met1 >>
+rect 0 -24 1008 24
+rect 130 80 159 88
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+rect 0 309 1008 357
+<< ndiffusion >>
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+<< pdiffusion >>
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+<< polycont >>
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+<< ndiffc >>
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+rect 64 46 81 63
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+<< nplus >>
+<< pplus >>
+<< labels >>
+rlabel met1 0 309 1008 357 0 VDD
+port 1 se
+rlabel met1 0 -24 1008 24 0 GND
+port 2 se
+rlabel met1 898 40 927 69 0 Q
+port 3 se
+rlabel met1 706 175 735 204 0 Q
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+rlabel met1 905 69 919 215 0 Q
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+rlabel met1 898 215 927 223 0 Q
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+rlabel met1 713 223 927 237 0 Q
+port 8 se
+rlabel met1 898 237 927 244 0 Q
+port 9 se
+rlabel met1 274 121 303 150 0 D
+port 10 se
+rlabel met1 130 80 159 88 0 CLK
+port 11 se
+rlabel met1 418 80 447 88 0 CLK
+port 12 se
+rlabel met1 130 88 447 102 0 CLK
+port 13 se
+rlabel met1 130 102 159 109 0 CLK
+port 14 se
+rlabel met1 418 102 447 109 0 CLK
+port 15 se
+<< end >>
diff --git a/env.sh b/env.sh
new file mode 100644
index 0000000..20e6fa5
--- /dev/null
+++ b/env.sh
@@ -0,0 +1,9 @@
+export STDCELLLIB=/home/philipp/libresilicon/StdCellLib
+export OPENLANE_ROOT=$(readlink -f $(pwd)/../openlane )
+export OPENLANE_TAG=v0.15
+export CARAVEL=$(pwd)
+export CARAVEL_ROOT=$(pwd)/caravel
+export PDK_ROOT=$(readlink -f $(pwd)/../pdk )
+#export PDK_ROOT=$(pwd)/../pdk
+export PATH=$PATH:$(readlink -f $(pwd)../openlane_summary/ )
+
diff --git a/openlane/user_proj_example/config.tcl b/openlane/user_proj_example/config.tcl
index 4ea25c6..12ae7fa 100755
--- a/openlane/user_proj_example/config.tcl
+++ b/openlane/user_proj_example/config.tcl
@@ -20,13 +20,30 @@
set ::env(VERILOG_FILES) "\
$script_dir/../../caravel/verilog/rtl/defines.v \
$script_dir/../../verilog/rtl/user_proj_example.v"
+# $script_dir/../../verilog/rtl/user_proj_cells.v"
+
+set verilog_root $script_dir/../../verilog/
+set lef_root $script_dir/../../cells/lef/
+set gds_root $script_dir/../../cells/gds/
+# Adding the standard cells into OpenLane:
+set ::env(EXTRA_LEFS) [glob $script_dir/../../cells/lef/*.lef]
+set ::env(EXTRA_LIBS) [glob $script_dir/../../cells/lib/libres*.lib]
+set ::env(EXTRA_GDS_FILES) [glob $script_dir/../../cells/gds/*.gds]
+set ::env(VERILOG_FILES_BLACKBOX) "$verilog_root/rtl/user_proj_cells.v"
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+set ::env(CLOCK_TREE_SYNTH) 0
+#set ::env(CLOCK_PERIOD) 0
+set ::env(RUN_SPEF_EXTRACTION) 0
+
set ::env(CLOCK_PORT) ""
set ::env(CLOCK_NET) "counter.clk"
set ::env(CLOCK_PERIOD) "10"
set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 900 600"
+#set ::env(DIE_AREA) "0 0 900 600"
+set ::env(DIE_AREA) "0 0 300 300"
+
set ::env(DESIGN_IS_CORE) 0
set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}]
@@ -34,8 +51,8 @@
set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
-set ::env(PL_BASIC_PLACEMENT) 1
-set ::env(PL_TARGET_DENSITY) 0.05
+set ::env(PL_BASIC_PLACEMENT) 0
+#set ::env(PL_TARGET_DENSITY) 0.1
# If you're going to use multiple power domains, then keep this disabled.
set ::env(RUN_CVC) 0
diff --git a/openlane/user_proj_example/macro_placement.cfg b/openlane/user_proj_example/macro_placement.cfg
new file mode 100644
index 0000000..ae6dbf7
--- /dev/null
+++ b/openlane/user_proj_example/macro_placement.cfg
@@ -0,0 +1,14 @@
+AND2X1 40.48 13.6 N
+AND2X2 40.48 19.04 N
+AOI21X1 40.48 24.48 N
+AOI22X1 40.48 29.92 N
+BUFX2 40.48 35.36 N
+BUFX4 40.48 40.8 N
+CLKBUF1 40.48 46.24 N
+HAX1 40.48 51.68 N
+INV 40.48 57.12 N
+INVX1 40.48 62.56 N
+INVX2 40.48 68 N
+INVX4 40.48 73.44 N
+INVX8 40.48 78.88 N
+LATCH 40.48 84.32 N
diff --git a/scripts/cells.pl b/scripts/cells.pl
new file mode 100644
index 0000000..26a60a1
--- /dev/null
+++ b/scripts/cells.pl
@@ -0,0 +1,59 @@
+#!/usr/bin/perl -w
+
+my $STDCELLLIB=$ENV{'STDCELLLIB'} || "/home/philipp/libresilicon/StdCellLib";
+
+
+
+print <<EOF
+`default_nettype none
+
+/*
+ *-------------------------------------------------------------
+ *
+ * user_proj_cells (LibreSilicon Testwafer #1)
+ *
+ */
+
+EOF
+;
+
+our $nextla=0;
+our $nextio=0;
+
+foreach my $mag(<$STDCELLLIB/Catalog/*.mag>)
+{
+ next if((-s $mag)<=50);
+ #print `ls -la $mag`;
+ my $cell=$mag; $cell=~s/\.mag$/.cell/;
+ my $name=""; $name=$1 if($mag=~m/([\w\-\.]+)\.mag$/);
+ next unless(-f $cell);
+ open CELL,"<$cell";
+ print "module $name(\n";
+
+ while(<CELL>)
+ {
+ if(m/^\.inputs (.*)/)
+ {
+ foreach my $inp(split " ",$1)
+ {
+ my $io=$nextio++;
+ print " inout $inp, // input\n";
+ }
+ }
+ if(m/^\.outputs (.*)/)
+ {
+ foreach my $outp(split " ",$1)
+ {
+ my $io=$nextio++;
+ print " inout $outp, // output\n";
+ }
+ }
+
+ }
+ close CELL;
+ print " inout vdd, // cell power supply\n";
+ print " inout gnd // cell ground supply\n";
+ print ");\n";
+ print "endmodule\n\n";
+}
+
diff --git a/scripts/deploy2caravel.sh b/scripts/deploy2caravel.sh
new file mode 100644
index 0000000..858e560
--- /dev/null
+++ b/scripts/deploy2caravel.sh
@@ -0,0 +1,32 @@
+#!/bin/bash
+echo This script needs to be run from the StdCellLib/Catalog directory
+#CARAVEL=/media/philipp/Daten/skywater/caravel-stdcelllib-stdcells
+
+mkdir $CARAVEL/cells{,/lib,/lef,/lef/orig,/gds,/mag}
+
+rm -f $CARAVEL/cells/lib/*.lib $CARAVEL/cells/lef/orig/*.lef $CARAVEL/cells/lef/*.lef $CARAVEL/cells/gds/*.gds $CARAVEL/cells/mag/*.mag
+
+cd $STDCELLLIB/Catalog
+
+cp *.lib $CARAVEL/cells/lib/
+cp outputlib/*.lef $CARAVEL/cells/lef/orig/
+cp outputlib/*.gds $CARAVEL/cells/gds/
+cp *.mag $CARAVEL/cells/mag/
+rm $CARAVEL/cells/mag/demoboard.mag
+
+cd $CARAVEL/cells/lef
+perl fixup.pl
+
+cd $CARAVEL/cells/lib
+perl removenl.pl >new.lib
+mv new.lib libresilicon.lib
+
+perl $CARAVEL/scripts/generator.pl >$CARAVEL/verilog/rtl/user_proj_example.v
+perl $CARAVEL/scripts/cells.pl >$CARAVEL/verilog/rtl/user_proj_cells.v
+perl $CARAVEL/scripts/placement.pl >$CARAVEL/openlane/user_proj_example/macro_placement.cfg
+
+cd $CARAVEL
+#bash my.sh
+make user_proj_example
+
+echo "Deployment done.";
diff --git a/scripts/generator.pl b/scripts/generator.pl
new file mode 100644
index 0000000..9eb5972
--- /dev/null
+++ b/scripts/generator.pl
@@ -0,0 +1,122 @@
+#!/usr/bin/perl -w
+
+my $STDCELLLIB=$ENV{'STDCELLLIB'} || "/home/philipp/libresilicon/StdCellLib";
+
+print <<EOF
+`default_nettype none
+
+/*
+ *-------------------------------------------------------------
+ *
+ * user_proj_ls130tw1 (LibreSilicon Testwafer #1)
+ *
+ */
+
+module user_proj_example #(
+ parameter BITS = 32
+)(
+`ifdef USE_POWER_PINS
+ inout vdda1, // User area 1 3.3V supply
+ inout vdda2, // User area 2 3.3V supply
+ inout vssa1, // User area 1 analog ground
+ inout vssa2, // User area 2 analog ground
+ inout vccd1, // User area 1 1.8V supply
+ inout vccd2, // User area 2 1.8v supply
+ inout vssd1, // User area 1 digital ground
+ inout vssd2, // User area 2 digital ground
+`endif
+
+ // Wishbone Slave ports (WB MI A)
+ input wb_clk_i,
+ input wb_rst_i,
+ input wbs_stb_i,
+ input wbs_cyc_i,
+ input wbs_we_i,
+ input [3:0] wbs_sel_i,
+ input [31:0] wbs_dat_i,
+ input [31:0] wbs_adr_i,
+ output wbs_ack_o,
+ output [31:0] wbs_dat_o,
+
+ // Logic Analyzer Signals
+ input [127:0] la_data_in,
+ output [127:0] la_data_out,
+ input [127:0] la_oen,
+
+ // IOs
+ input [`MPRJ_IO_PADS-1:0] io_in,
+ output [`MPRJ_IO_PADS-1:0] io_out,
+ output [`MPRJ_IO_PADS-1:0] io_oeb
+);
+
+EOF
+;
+
+
+our $nextla=0;
+our $nextio=0;
+our $conf="";
+my $MPRJ_IO_PADS=38;
+
+foreach my $mag(<$STDCELLLIB/Catalog/*.mag>)
+{
+ next if((-s $mag)<=50);
+ #print `ls -la $mag`;
+ my $cell=$mag; $cell=~s/\.mag$/.cell/;
+ my $name=""; $name=$1 if($mag=~m/([\w\-\.]+)\.mag$/);
+ next unless(-f $cell);
+ open CELL,"<$cell";
+ print "$name $name(\n";
+ print " `ifdef USE_POWER_PINS\n";
+ print " \.vdd(vccd1),\n"; # ??? Should we do 3.3V or 1.8V ?
+ print " \.gnd(vssd1),\n";
+ print " `endif\n";
+
+
+ while(<CELL>)
+ {
+ if(m/^\.inputs (.*)/)
+ {
+ foreach my $inp(split " ",$1)
+ {
+ my $io=$nextio++;
+ if($io<$MPRJ_IO_PADS)
+ {
+ print " \.$inp(io_in[$io]),\n";
+ $conf.="assign io_oeb[$io] = 1'b1;\n";
+ $inout{"io$io"}="ioin";
+ }
+ else
+ {
+ my $la=$io-$MPRJ_IO_PADS;
+ print " \.$inp(la_data_in[$la]),\n";
+ $inout{"io$io"}="lain";
+ }
+ }
+ }
+ if(m/^\.outputs (.*)/)
+ {
+ foreach my $outp(split " ",$1)
+ {
+ my $io=$nextio++;
+ if($io<$MPRJ_IO_PADS)
+ {
+ print " \.$outp(io_out[$io]),\n";
+ $conf.="assign io_oeb[$io] = 1'b0;\n";
+ $inout{"io$io"}="ioout";
+ }
+ else
+ {
+ my $la=$io-$MPRJ_IO_PADS;
+ print " \.$outp(la_data_out[$la]),\n";
+ $inout{"io$io"}="laout";
+ }
+ }
+ }
+
+ }
+ close CELL;
+ print ");\n";
+}
+print $conf;
+print "endmodule\n";
diff --git a/scripts/placement.pl b/scripts/placement.pl
new file mode 100644
index 0000000..71ebe06
--- /dev/null
+++ b/scripts/placement.pl
@@ -0,0 +1,16 @@
+#!/usr/bin/perl -w
+
+our $nextla=2.72*5;
+
+my $STDCELLLIB=$ENV{'STDCELLLIB'} || "/home/philipp/libresilicon/StdCellLib";
+
+foreach my $mag(<$STDCELLLIB/Catalog/*.mag>)
+{
+ next if((-s $mag)<=50);
+ #print `ls -la $mag`;
+ my $cell=$mag; $cell=~s/\.mag$/.cell/;
+ next unless(-f $cell);
+ my $name=""; $name=$1 if($mag=~m/([\w\-\.]+)\.mag$/);
+ print "$name ".(46-0.46*12)." $nextla N\n";
+ $nextla+=2.72*2;
+}
diff --git a/scripts/testgen.pl b/scripts/testgen.pl
new file mode 100644
index 0000000..bd11706
--- /dev/null
+++ b/scripts/testgen.pl
@@ -0,0 +1,64 @@
+#!/usr/bin/perl -w
+open IN,"<$ARGV[0]";
+
+print <<EOF
+#include "../../defs.h"
+#include "../../stub.c"
+EOF
+;
+
+my $header=<IN>;
+my @l=split "->",$header;
+my @ins=split " ",$l[0];
+my @outs=split " ",$l[1];
+my %map=();
+
+my $reg=0;
+my @io=();
+print " printf(\"Initializing the Inputs of the cell:\\n\");\n";
+foreach(@ins)
+{
+ print " reg_mprj_io_$reg = GPIO_MODE_MGMT_STD_OUTPUT; // $_\n";
+ $io[$reg>>5]|=1<<($reg&31);
+ $reg++;
+}
+print " printf(\"Initializing the Outputs of the cell:\\n\");\n";
+foreach(@outs)
+{
+ $map{$_}=$reg++;
+
+ print " reg_mprj_io_$reg = GPIO_MODE_USER_STD_OUTPUT; // $_\n";
+}
+
+print " reg_mprj_xfer=1;\n";
+print " while (reg_mprj_xfer == 1);\n";
+
+foreach(0 .. 3)
+{
+ print "reg_la".$_."_ena=".sprintf("0x%08X",$io[$_]).";\n" if(defined($io[$_]));
+}
+
+my $counter=0;
+print " printf(\"Starting the tests:\\n\");\n";
+
+while(<IN>)
+{
+ last if(m/^function:/);
+ @l=split " ",$_;
+ my $if=0;
+ foreach(@l)
+ {
+ if(m/(\w+)=(\d)/)
+ {
+ print " assert(reg_la".$map{$1}."_data==$2); //$1\n";
+ }
+ else
+ {
+ print " reg_la".$if."_data=$_; //$ins[$if]\n";
+ }
+ $if++;
+ }
+ print " printf(\"Test $counter successful\\n\");\n\n";
+
+ $counter++;
+}
diff --git a/scripts/viewer.pl b/scripts/viewer.pl
new file mode 100644
index 0000000..ee60497
--- /dev/null
+++ b/scripts/viewer.pl
@@ -0,0 +1,13 @@
+#!/usr/bin/perl -w
+
+my $STDCELLLIB=$ENV{'STDCELLLIB'} || "/home/philipp/libresilicon/StdCellLib";
+my $CARAVEL=$ENV{'CARAVEL'} || "/media/philipp/Daten/skywater/caravel-stdcelllib-stdcells";
+
+open OUT,"|magic -noconsole -T sky130A";
+foreach(<$CARAVEL/cells/lef/*.lef>)
+{
+ print OUT "lef read $_\n";
+}
+print OUT "def read ".$ARGV[0]."\n";
+#print OUT "select top\n";
+close OUT;
diff --git a/verilog/rtl/user_proj_cells.v b/verilog/rtl/user_proj_cells.v
new file mode 100644
index 0000000..0f0ab64
--- /dev/null
+++ b/verilog/rtl/user_proj_cells.v
@@ -0,0 +1,131 @@
+`default_nettype none
+
+/*
+ *-------------------------------------------------------------
+ *
+ * user_proj_cells (LibreSilicon Testwafer #1)
+ *
+ */
+
+module AND2X1(
+ inout B, // input
+ inout A, // input
+ inout Y, // output
+ inout vdd, // cell power supply
+ inout gnd // cell ground supply
+);
+endmodule
+
+module AND2X2(
+ inout B, // input
+ inout A, // input
+ inout Y, // output
+ inout vdd, // cell power supply
+ inout gnd // cell ground supply
+);
+endmodule
+
+module AOI21X1(
+ inout C, // input
+ inout B, // input
+ inout A, // input
+ inout Y, // output
+ inout vdd, // cell power supply
+ inout gnd // cell ground supply
+);
+endmodule
+
+module AOI22X1(
+ inout D, // input
+ inout C, // input
+ inout B, // input
+ inout A, // input
+ inout Y, // output
+ inout vdd, // cell power supply
+ inout gnd // cell ground supply
+);
+endmodule
+
+module BUFX2(
+ inout A, // input
+ inout Y, // output
+ inout vdd, // cell power supply
+ inout gnd // cell ground supply
+);
+endmodule
+
+module BUFX4(
+ inout A, // input
+ inout Y, // output
+ inout vdd, // cell power supply
+ inout gnd // cell ground supply
+);
+endmodule
+
+module CLKBUF1(
+ inout A, // input
+ inout Y, // output
+ inout vdd, // cell power supply
+ inout gnd // cell ground supply
+);
+endmodule
+
+module HAX1(
+ inout B, // input
+ inout A, // input
+ inout YS, // output
+ inout YC, // output
+ inout vdd, // cell power supply
+ inout gnd // cell ground supply
+);
+endmodule
+
+module INV(
+ inout A, // input
+ inout Y, // output
+ inout vdd, // cell power supply
+ inout gnd // cell ground supply
+);
+endmodule
+
+module INVX1(
+ inout A, // input
+ inout Y, // output
+ inout vdd, // cell power supply
+ inout gnd // cell ground supply
+);
+endmodule
+
+module INVX2(
+ inout A, // input
+ inout Y, // output
+ inout vdd, // cell power supply
+ inout gnd // cell ground supply
+);
+endmodule
+
+module INVX4(
+ inout A, // input
+ inout Y, // output
+ inout vdd, // cell power supply
+ inout gnd // cell ground supply
+);
+endmodule
+
+module INVX8(
+ inout A, // input
+ inout Y, // output
+ inout vdd, // cell power supply
+ inout gnd // cell ground supply
+);
+endmodule
+
+module LATCH(
+ inout D, // input
+ inout CLK, // input
+ inout Q, // output
+ inout vdd, // cell power supply
+ inout gnd // cell ground supply
+);
+endmodule
+
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index b33e032..499a917 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -1,52 +1,24 @@
-// SPDX-FileCopyrightText: 2020 Efabless Corporation
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-
`default_nettype none
+
/*
*-------------------------------------------------------------
*
- * user_proj_example
+ * user_proj_ls130tw1 (LibreSilicon Testwafer #1)
*
- * This is an example of a (trivially simple) user project,
- * showing how the user project can connect to the logic
- * analyzer, the wishbone bus, and the I/O pads.
- *
- * This project generates an integer count, which is output
- * on the user area GPIO pads (digital output only). The
- * wishbone connection allows the project to be controlled
- * (start and stop) from the management SoC program.
- *
- * See the testbenches in directory "mprj_counter" for the
- * example programs that drive this user project. The three
- * testbenches are "io_ports", "la_test1", and "la_test2".
- *
- *-------------------------------------------------------------
*/
module user_proj_example #(
parameter BITS = 32
)(
`ifdef USE_POWER_PINS
- inout vdda1, // User area 1 3.3V supply
- inout vdda2, // User area 2 3.3V supply
- inout vssa1, // User area 1 analog ground
- inout vssa2, // User area 2 analog ground
- inout vccd1, // User area 1 1.8V supply
- inout vccd2, // User area 2 1.8v supply
- inout vssd1, // User area 1 digital ground
- inout vssd2, // User area 2 digital ground
+ inout vdda1, // User area 1 3.3V supply
+ inout vdda2, // User area 2 3.3V supply
+ inout vssa1, // User area 1 analog ground
+ inout vssa2, // User area 2 analog ground
+ inout vccd1, // User area 1 1.8V supply
+ inout vccd2, // User area 2 1.8v supply
+ inout vssd1, // User area 1 digital ground
+ inout vssd2, // User area 2 digital ground
`endif
// Wishbone Slave ports (WB MI A)
@@ -64,108 +36,172 @@
// Logic Analyzer Signals
input [127:0] la_data_in,
output [127:0] la_data_out,
- input [127:0] la_oenb,
+ input [127:0] la_oen,
// IOs
input [`MPRJ_IO_PADS-1:0] io_in,
output [`MPRJ_IO_PADS-1:0] io_out,
- output [`MPRJ_IO_PADS-1:0] io_oeb,
-
- // IRQ
- output [2:0] irq
+ output [`MPRJ_IO_PADS-1:0] io_oeb
);
- wire clk;
- wire rst;
- wire [`MPRJ_IO_PADS-1:0] io_in;
- wire [`MPRJ_IO_PADS-1:0] io_out;
- wire [`MPRJ_IO_PADS-1:0] io_oeb;
-
- wire [31:0] rdata;
- wire [31:0] wdata;
- wire [BITS-1:0] count;
-
- wire valid;
- wire [3:0] wstrb;
- wire [31:0] la_write;
-
- // WB MI A
- assign valid = wbs_cyc_i && wbs_stb_i;
- assign wstrb = wbs_sel_i & {4{wbs_we_i}};
- assign wbs_dat_o = rdata;
- assign wdata = wbs_dat_i;
-
- // IO
- assign io_out = count;
- assign io_oeb = {(`MPRJ_IO_PADS-1){rst}};
-
- // IRQ
- assign irq = 3'b000; // Unused
-
- // LA
- assign la_data_out = {{(127-BITS){1'b0}}, count};
- // Assuming LA probes [63:32] are for controlling the count register
- assign la_write = ~la_oenb[63:32] & ~{BITS{valid}};
- // Assuming LA probes [65:64] are for controlling the count clk & reset
- assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i;
- assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i;
-
- counter #(
- .BITS(BITS)
- ) counter(
- .clk(clk),
- .reset(rst),
- .ready(wbs_ack_o),
- .valid(valid),
- .rdata(rdata),
- .wdata(wbs_dat_i),
- .wstrb(wstrb),
- .la_write(la_write),
- .la_input(la_data_in[63:32]),
- .count(count)
- );
-
-endmodule
-
-module counter #(
- parameter BITS = 32
-)(
- input clk,
- input reset,
- input valid,
- input [3:0] wstrb,
- input [BITS-1:0] wdata,
- input [BITS-1:0] la_write,
- input [BITS-1:0] la_input,
- output ready,
- output [BITS-1:0] rdata,
- output [BITS-1:0] count
+AND2X1 AND2X1(
+ `ifdef USE_POWER_PINS
+ .vdd(vccd1),
+ .gnd(vssd1),
+ `endif
+ .B(io_in[0]),
+ .A(io_in[1]),
+ .Y(io_out[2]),
);
- reg ready;
- reg [BITS-1:0] count;
- reg [BITS-1:0] rdata;
-
- always @(posedge clk) begin
- if (reset) begin
- count <= 0;
- ready <= 0;
- end else begin
- ready <= 1'b0;
- if (~|la_write) begin
- count <= count + 1;
- end
- if (valid && !ready) begin
- ready <= 1'b1;
- rdata <= count;
- if (wstrb[0]) count[7:0] <= wdata[7:0];
- if (wstrb[1]) count[15:8] <= wdata[15:8];
- if (wstrb[2]) count[23:16] <= wdata[23:16];
- if (wstrb[3]) count[31:24] <= wdata[31:24];
- end else if (|la_write) begin
- count <= la_write & la_input;
- end
- end
- end
-
+AND2X2 AND2X2(
+ `ifdef USE_POWER_PINS
+ .vdd(vccd1),
+ .gnd(vssd1),
+ `endif
+ .B(io_in[3]),
+ .A(io_in[4]),
+ .Y(io_out[5]),
+);
+AOI21X1 AOI21X1(
+ `ifdef USE_POWER_PINS
+ .vdd(vccd1),
+ .gnd(vssd1),
+ `endif
+ .C(io_in[6]),
+ .B(io_in[7]),
+ .A(io_in[8]),
+ .Y(io_out[9]),
+);
+AOI22X1 AOI22X1(
+ `ifdef USE_POWER_PINS
+ .vdd(vccd1),
+ .gnd(vssd1),
+ `endif
+ .D(io_in[10]),
+ .C(io_in[11]),
+ .B(io_in[12]),
+ .A(io_in[13]),
+ .Y(io_out[14]),
+);
+BUFX2 BUFX2(
+ `ifdef USE_POWER_PINS
+ .vdd(vccd1),
+ .gnd(vssd1),
+ `endif
+ .A(io_in[15]),
+ .Y(io_out[16]),
+);
+BUFX4 BUFX4(
+ `ifdef USE_POWER_PINS
+ .vdd(vccd1),
+ .gnd(vssd1),
+ `endif
+ .A(io_in[17]),
+ .Y(io_out[18]),
+);
+CLKBUF1 CLKBUF1(
+ `ifdef USE_POWER_PINS
+ .vdd(vccd1),
+ .gnd(vssd1),
+ `endif
+ .A(io_in[19]),
+ .Y(io_out[20]),
+);
+HAX1 HAX1(
+ `ifdef USE_POWER_PINS
+ .vdd(vccd1),
+ .gnd(vssd1),
+ `endif
+ .B(io_in[21]),
+ .A(io_in[22]),
+ .YS(io_out[23]),
+ .YC(io_out[24]),
+);
+INV INV(
+ `ifdef USE_POWER_PINS
+ .vdd(vccd1),
+ .gnd(vssd1),
+ `endif
+ .A(io_in[25]),
+ .Y(io_out[26]),
+);
+INVX1 INVX1(
+ `ifdef USE_POWER_PINS
+ .vdd(vccd1),
+ .gnd(vssd1),
+ `endif
+ .A(io_in[27]),
+ .Y(io_out[28]),
+);
+INVX2 INVX2(
+ `ifdef USE_POWER_PINS
+ .vdd(vccd1),
+ .gnd(vssd1),
+ `endif
+ .A(io_in[29]),
+ .Y(io_out[30]),
+);
+INVX4 INVX4(
+ `ifdef USE_POWER_PINS
+ .vdd(vccd1),
+ .gnd(vssd1),
+ `endif
+ .A(io_in[31]),
+ .Y(io_out[32]),
+);
+INVX8 INVX8(
+ `ifdef USE_POWER_PINS
+ .vdd(vccd1),
+ .gnd(vssd1),
+ `endif
+ .A(io_in[33]),
+ .Y(io_out[34]),
+);
+LATCH LATCH(
+ `ifdef USE_POWER_PINS
+ .vdd(vccd1),
+ .gnd(vssd1),
+ `endif
+ .D(io_in[35]),
+ .CLK(io_in[36]),
+ .Q(io_out[37]),
+);
+assign io_oeb[0] = 1'b1;
+assign io_oeb[1] = 1'b1;
+assign io_oeb[2] = 1'b0;
+assign io_oeb[3] = 1'b1;
+assign io_oeb[4] = 1'b1;
+assign io_oeb[5] = 1'b0;
+assign io_oeb[6] = 1'b1;
+assign io_oeb[7] = 1'b1;
+assign io_oeb[8] = 1'b1;
+assign io_oeb[9] = 1'b0;
+assign io_oeb[10] = 1'b1;
+assign io_oeb[11] = 1'b1;
+assign io_oeb[12] = 1'b1;
+assign io_oeb[13] = 1'b1;
+assign io_oeb[14] = 1'b0;
+assign io_oeb[15] = 1'b1;
+assign io_oeb[16] = 1'b0;
+assign io_oeb[17] = 1'b1;
+assign io_oeb[18] = 1'b0;
+assign io_oeb[19] = 1'b1;
+assign io_oeb[20] = 1'b0;
+assign io_oeb[21] = 1'b1;
+assign io_oeb[22] = 1'b1;
+assign io_oeb[23] = 1'b0;
+assign io_oeb[24] = 1'b0;
+assign io_oeb[25] = 1'b1;
+assign io_oeb[26] = 1'b0;
+assign io_oeb[27] = 1'b1;
+assign io_oeb[28] = 1'b0;
+assign io_oeb[29] = 1'b1;
+assign io_oeb[30] = 1'b0;
+assign io_oeb[31] = 1'b1;
+assign io_oeb[32] = 1'b0;
+assign io_oeb[33] = 1'b1;
+assign io_oeb[34] = 1'b0;
+assign io_oeb[35] = 1'b1;
+assign io_oeb[36] = 1'b1;
+assign io_oeb[37] = 1'b0;
endmodule
-`default_nettype wire
