Update caravel-lite references
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index cf90dec..82814d4 100755
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -26,7 +26,7 @@
## Source Verilog Files
set ::env(VERILOG_FILES) "\
- $script_dir/../../caravel-lite/verilog/rtl/defines.v \
+ $script_dir/../../caravel/verilog/rtl/defines.v \
$script_dir/../../verilog/rtl/user_project_wrapper.v"
## Clock configurations
