| commit | d410a13bdca0048f878f274c8747020a066ebe53 | [log] [tgz] |
|---|---|---|
| author | Philipp Gühring <pg@futureware.at> | Sat Jun 19 04:31:20 2021 +0200 |
| committer | Philipp Gühring <pg@futureware.at> | Sat Jun 19 04:31:20 2021 +0200 |
| tree | 6c5e06fce02caefc8c4928a694f3e87d3c6197e4 | |
| parent | 3944ecf3bea4cdb7df58a1b0bff59f245dd73e71 [diff] |
Importing more views into Caravel
This project is a test-wafer which puts various LS130 cells into the user-area of a Caravel harness for taping the LS130 cells out on the Skywater 130nm process.
The LS130 cells are generated with the https://github.com/thesourcerer8/StdCellLib flow (which uses Librecell's lclayout and lctime), using the Tech.SKY130 configuration.
The build report can be seen here: https://pdk.libresilicon.com/dist/StdCellLib_20201106_SKY130/Catalog/ The cells were copied into this repository to avoid additional dependencies: https://github.com/thesourcerer8/caravel_stdcelllib_stdcells/tree/release/cells
A generator was developed to generate a Verilog file for all the cells that places each cell once and connects it to the IOs of the harness: https://github.com/thesourcerer8/caravel_stdcelllib_stdcells_project/blob/release/scripts/generator.pl The script needs to be run from the Catalog directory of your StdCellLib. The output is then used as https://github.com/thesourcerer8/caravel-stdcelllib-stdcells/blob/release/verilog/rtl/user_proj_example.v
In the end I adapted https://github.com/thesourcerer8/caravel_stdcelllib_stdcells_project/blob/release/openlane/user_proj_example/config.tcl to use the cells as blackbox cells.
Build process:
git clone git@github.com:thesourcerer8/caravel_stdcelllib_stdcells_project.git
cd caravel_stdcelllib_stdcells_project
. ./env.sh
make install # install caravel-lite make pdk # clone and build pdk make openlane # clone and build build openlane
scripts/deploy2caravel.sh
make user_proj_example
Refer to README for the Caravel documentation.