| commit | 4bcc14f4f171b6e3e5112121dd4ccf0b19f79b4b | [log] [tgz] |
|---|---|---|
| author | Philipp Gühring <pg@futureware.at> | Fri Jun 25 17:14:03 2021 +0200 |
| committer | Philipp Gühring <pg@futureware.at> | Fri Jun 25 17:14:03 2021 +0200 |
| tree | d35836a745c8cb79ae5931952ff719bbe9f3cad7 | |
| parent | 6896a8a540e63820ee962e8773074dcc155edee6 [diff] |
Fixed markup
This project is a test-wafer which puts various LS130 cells into the user-area of a Caravel harness for taping the LS130 cells out on the Skywater 130nm process.
The LS130 cells are generated with the https://github.com/thesourcerer8/StdCellLib flow (which uses Librecell's lclayout and lctime), using the Tech.SKY130 configuration.
The build report can be seen here: https://pdk.libresilicon.com/dist/StdCellLib_20210618/Catalog/buildreport.html The cells were copied into this repository to avoid additional dependencies: https://github.com/thesourcerer8/caravel_stdcelllib_stdcells_project/tree/main/cells
A generator was developed to generate a Verilog file for all the cells that places each cell once and connects it to the IOs of the harness: https://github.com/thesourcerer8/caravel_stdcelllib_stdcells_project/blob/main/scripts/generator.pl The script needs to be run from the Catalog directory of your StdCellLib. The output is then used as https://github.com/thesourcerer8/caravel_stdcelllib_stdcells_project/blob/main/verilog/rtl/user_proj_example.v
In the end I adapted https://github.com/thesourcerer8/caravel_stdcelllib_stdcells_project/blob/main/openlane/user_proj_example/config.tcl to use the cells as blackbox cells.
Build process:
git clone git@github.com:thesourcerer8/caravel_stdcelllib_stdcells_project.git
cd caravel_stdcelllib_stdcells_project
. ./env.sh
make install # install caravel-lite
make pdk # clone and build pdk
make openlane # clone and build build openlane
scripts/deploy2caravel.sh
make user_proj_example
Refer to README for the Caravel documentation.