| commit | b71661962a97797f9782fe0681fd49e15201ca83 | [log] [tgz] |
|---|---|---|
| author | S Skandha Deepsita <skandha.deepsita5@gmail.com> | Mon Jun 28 11:52:35 2021 +0530 |
| committer | GitHub <noreply@github.com> | Mon Jun 28 11:52:35 2021 +0530 |
| tree | 008389379fd8eafdaf5212167419ed08ee592455 | |
| parent | 4c2d93667bfbf0b81cc45870393c12ba6605fe7e [diff] |
Update info.yaml
diff --git a/info.yaml b/info.yaml index e01c97d..bec3e0e 100644 --- a/info.yaml +++ b/info.yaml
@@ -13,7 +13,7 @@ - "Open MPW" - "Test Harness" category: "Test Harness" - top_level_netlist: "verilog/rtl/user_analog_project_wrapper.v" + top_level_netlist: "verilog/rtl/caravel.v" user_level_netlist: "verilog/rtl/user_analog_project_wrapper.v" version: "1.00" cover_image: "Postlayout/Pictures/10bitdac layout desing.PNG "