Add files via upload
diff --git a/mag/10bitdac_cap_layout_design.mag b/mag/10bitdac_cap_layout_design.mag
new file mode 100644
index 0000000..c1ff8b0
--- /dev/null
+++ b/mag/10bitdac_cap_layout_design.mag
@@ -0,0 +1,110 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624221218
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+use 10bitdac_layout 10bitdac_layout_0
+timestamp 1624221218
+transform 1 0 428 0 1 57644
+box -428 -57692 205056 54770
+use cap_28p cap_28p_0
+timestamp 1624221218
+transform 1 0 210498 0 1 53878
+box -1968 -2452 24820 24898
+<< labels >>
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+port 14 nsew
+flabel metal4 s 201970 58220 202162 83072 0 FreeSans 195 0 0 0 vdd!
+port 15 nsew
+<< properties >>
+string FIXED_BBOX 0 0 1748 1088
+<< end >>
diff --git a/mag/10bitdac_layout.mag b/mag/10bitdac_layout.mag
new file mode 100644
index 0000000..a8d1e9d
--- /dev/null
+++ b/mag/10bitdac_layout.mag
@@ -0,0 +1,625 @@
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+rect 182742 -15096 182752 -15062
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+rect 182742 -15108 182802 -15096
+<< via1 >>
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+rect 202630 -594 202682 -542
+<< metal2 >>
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+rect 196108 27644 196198 28170
+rect 167888 -2118 168006 -2108
+rect 196120 -2118 196198 27644
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+<< via2 >>
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+<< metal3 >>
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+rect 203346 378 203354 435
+rect 203348 371 203354 378
+rect 203418 424 203422 435
+rect 203418 371 203430 424
+rect 203348 336 203430 371
+rect 203350 315 203430 336
+rect 203350 259 203363 315
+rect 203419 259 203430 315
+rect 203350 242 203430 259
+<< via3 >>
+rect 203354 371 203418 435
+<< metal4 >>
+rect 201162 31044 201518 31050
+rect 197054 30978 201640 31044
+rect 201162 30968 201640 30978
+rect 201540 25428 201640 30968
+rect 201540 25220 201734 25428
+rect 201542 648 201734 25220
+rect 201542 576 203420 648
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+rect 203348 516 203420 576
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+rect 203346 435 203422 496
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+rect 203346 371 203354 435
+rect 203418 424 203422 435
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+rect 203346 352 203434 371
+rect 166934 -1628 167402 -1624
+rect 201558 -1628 201724 314
+rect 166934 -1828 201724 -1628
+rect 166946 -2842 167064 -1828
+rect 166936 -2912 167064 -2842
+rect 166936 -4012 167054 -2912
+use 9bitdac_layout 9bitdac_layout_0
+timestamp 1624221218
+transform 1 0 0 0 1 1976
+box 0 -1976 198772 52794
+use 9bitdac_layout 9bitdac_layout_1
+timestamp 1624221218
+transform 1 0 -428 0 1 -55716
+box 0 -1976 198772 52794
+use switch_layout switch_layout_0
+timestamp 1624221218
+transform 1 0 202454 0 1 -818
+box 40 172 2460 1180
+use res250_layout res250_layout_0
+timestamp 1624221218
+transform 1 0 165760 0 1 5268
+box 218 -342 484 -90
+<< labels >>
+rlabel locali s 166002 5196 166002 5196 4 x1_vref5
+rlabel locali s 166178 4858 166178 4858 4 x2_vref1
+rlabel locali s 165594 -52506 165594 -52506 4 inp2
+rlabel locali s 830 53968 830 53968 4 inp1
+rlabel locali s 202424 -280 202424 -280 4 d9
+rlabel locali s 204962 -118 204962 -118 4 out_v
+rlabel metal2 s 202538 -566 202538 -566 4 gnd!
+rlabel metal4 s 203376 488 203376 488 4 vdd!
+rlabel locali s 204708 432 204708 432 4 x1_out_v
+rlabel locali s 204730 -712 204730 -712 4 x2_out_v
+rlabel locali s 166580 414 166580 414 4 d0
+rlabel locali s 169642 144 169642 144 4 d1
+rlabel locali s 173170 -566 173170 -566 4 d2
+rlabel locali s 176582 -860 176582 -860 4 d3
+rlabel locali s 179432 -344 179432 -344 4 d4
+rlabel locali s 182764 -170 182764 -170 4 d5
+rlabel locali s 188000 -138 188000 -138 4 d6
+rlabel locali s 191500 -950 191500 -950 4 d7
+rlabel locali s 195706 -1220 195706 -1220 4 d8
+<< end >>
diff --git a/mag/2bitdac_layout.mag b/mag/2bitdac_layout.mag
new file mode 100644
index 0000000..b4f3899
--- /dev/null
+++ b/mag/2bitdac_layout.mag
@@ -0,0 +1,346 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624221218
+<< checkpaint >>
+rect -1270 -2558 7762 2690
+<< locali >>
+rect 400 1308 2254 1310
+rect 2630 1308 3014 1310
+rect 400 1270 3014 1308
+rect 400 1268 2872 1270
+rect 400 1066 442 1268
+rect 2252 1266 2632 1268
+rect 170 738 220 986
+rect 400 864 440 1066
+rect 2978 1060 3014 1270
+rect 150 438 200 538
+rect 402 438 440 864
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+rect 3424 816 6160 854
+rect 3424 790 3468 816
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+rect 778 658 816 662
+rect 150 398 440 438
+rect 768 410 816 658
+rect 6110 576 6160 816
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+rect 672 170 728 184
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+rect 768 168 818 410
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+rect -10 -1140 40 -986
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+rect 3034 -1098 3068 -972
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+rect 1904 -1136 2634 -1134
+rect 330 -1138 704 -1136
+rect 330 -1140 380 -1138
+rect -10 -1174 380 -1140
+rect -10 -1234 40 -1174
+<< viali >>
+rect 3145 744 3179 778
+rect 682 135 716 169
+rect 6281 260 6315 294
+rect 918 131 952 165
+rect 678 -28 712 6
+rect 904 -26 938 8
+rect 3170 -543 3204 -509
+<< metal1 >>
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+rect 1602 1124 1682 1126
+rect 1602 1106 1694 1124
+rect 1602 1054 1630 1106
+rect 1682 1054 1694 1106
+rect 1602 1036 1694 1054
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+rect 4030 -173 4112 -108
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+rect 3170 -509 3204 -508
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+rect 942 -955 1002 -904
+rect 942 -1007 943 -955
+rect 995 -1007 1002 -955
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+<< via1 >>
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+rect 4789 568 4841 620
+rect 909 275 961 327
+rect 1665 -229 1717 -177
+rect 4039 -225 4091 -173
+rect 943 -1007 995 -955
+<< metal2 >>
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+rect 1622 1106 1694 1130
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+<< via2 >>
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+rect 4788 665 4844 721
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+<< metal3 >>
+rect 1620 1402 1728 1426
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+rect 1622 1234 1702 1316
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+rect 1656 89 1746 104
+rect 1656 25 1668 89
+rect 1732 25 1746 89
+rect 1656 18 1746 25
+rect 1656 -83 1744 18
+rect 1656 -139 1665 -83
+rect 1721 -139 1744 -83
+rect 1656 -154 1744 -139
+<< via3 >>
+rect 1636 1338 1700 1402
+rect 4784 876 4848 940
+rect 1668 25 1732 89
+<< metal4 >>
+rect 2188 1426 4042 1428
+rect 4488 1426 4870 1430
+rect 1622 1402 4870 1426
+rect 1622 1338 1636 1402
+rect 1700 1338 4870 1402
+rect 1622 1322 4870 1338
+rect 1622 1320 4504 1322
+rect 1622 1318 2190 1320
+rect 4032 1318 4504 1320
+rect 1744 102 1854 1318
+rect 4766 956 4864 1322
+rect 4766 940 4868 956
+rect 4766 876 4784 940
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+rect 4766 858 4868 876
+rect 1656 89 1854 102
+rect 1656 25 1668 89
+rect 1732 25 1854 89
+rect 1656 22 1854 25
+rect 1656 18 1772 22
+use switch_layout switch_layout_0
+timestamp 1624221218
+transform 1 0 3868 0 1 -434
+box 40 172 2460 1180
+use switch_layout switch_layout_1
+timestamp 1624221218
+transform 1 0 764 0 1 -1230
+box 40 172 2460 1180
+use switch_layout switch_layout_2
+timestamp 1624221218
+transform 1 0 732 0 1 50
+box 40 172 2460 1180
+use res250_layout res250_layout_0
+timestamp 1624221218
+transform 0 1 340 -1 0 -598
+box 218 -342 484 -90
+use res500_layout res500_layout_0
+timestamp 1624221218
+transform 0 1 296 -1 0 1046
+box 218 -288 598 -90
+use res500_layout res500_layout_1
+timestamp 1624221218
+transform 0 1 288 -1 0 -34
+box 218 -288 598 -90
+use res500_layout res500_layout_2
+timestamp 1624221218
+transform 0 1 288 -1 0 598
+box 218 -288 598 -90
+<< labels >>
+rlabel locali s 200 816 200 816 4 vref1
+rlabel locali s 196 412 196 412 4 x1_inp1
+rlabel locali s 160 -128 160 -128 4 x1_inp2
+rlabel locali s 244 -730 244 -730 4 x2_inp1
+rlabel locali s 6 -1154 6 -1154 4 vref5
+rlabel locali s 780 -162 780 -162 4 d0
+rlabel locali s 3868 120 3868 120 4 d1
+rlabel locali s 3302 754 3302 754 4 x1_vout
+rlabel locali s 3530 -520 3530 -520 4 x2_vout
+rlabel locali s 6396 274 6396 274 4 out_v
+rlabel metal4 s 2236 1374 2236 1374 4 vdd!
+rlabel metal2 s 2062 -1274 2062 -1274 4 gnd!
+<< end >>
diff --git a/mag/3bitdac_layout.mag b/mag/3bitdac_layout.mag
new file mode 100644
index 0000000..af391fe
--- /dev/null
+++ b/mag/3bitdac_layout.mag
@@ -0,0 +1,196 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624221218
+<< checkpaint >>
+rect -1314 -4320 11380 3924
+<< locali >>
+rect 180 2182 232 2372
+rect 8780 1550 9674 1556
+rect 6592 1544 9674 1550
+rect 6458 1474 9674 1544
+rect 6458 1468 8854 1474
+rect 6458 1466 6636 1468
+rect 3838 959 3938 1414
+rect 3838 925 3870 959
+rect 3904 925 3938 959
+rect 3838 884 3938 925
+rect 9598 702 9670 1474
+rect 742 269 838 568
+rect 742 235 768 269
+rect 802 235 838 269
+rect 742 198 838 235
+rect 3802 523 3934 542
+rect 3802 489 3870 523
+rect 3904 489 3934 523
+rect 0 -18 208 16
+rect 170 -278 208 -18
+rect -54 -612 -16 -360
+rect 746 -499 838 -476
+rect 746 -533 776 -499
+rect 810 -533 838 -499
+rect 146 -612 200 -610
+rect -54 -654 200 -612
+rect 146 -696 200 -654
+rect 746 -624 838 -533
+rect 3802 -623 3934 489
+rect 9786 417 10120 434
+rect 9786 383 9805 417
+rect 9839 383 10120 417
+rect 9786 372 10120 383
+rect 7348 208 7494 300
+rect 746 -994 842 -624
+rect 3802 -657 3838 -623
+rect 3872 -657 3934 -623
+rect 3802 -684 3934 -657
+rect 3808 -1053 3908 -1038
+rect 3808 -1087 3840 -1053
+rect 3874 -1087 3908 -1053
+rect 3808 -1568 3908 -1087
+rect 9640 -1334 9708 -36
+rect 9526 -1338 9718 -1334
+rect 6422 -1342 7278 -1340
+rect 8758 -1342 9718 -1338
+rect 6422 -1406 9718 -1342
+rect 6422 -1408 8850 -1406
+rect 7220 -1410 8850 -1408
+rect 9526 -1414 9718 -1406
+rect 9640 -1416 9708 -1414
+rect -32 -2936 20 -2818
+rect -36 -3060 24 -2936
+<< viali >>
+rect 3870 925 3904 959
+rect 768 235 802 269
+rect 3870 489 3904 523
+rect 776 -533 810 -499
+rect 9805 383 9839 417
+rect 3838 -657 3872 -623
+rect 3840 -1087 3874 -1053
+<< metal1 >>
+rect 3834 959 3934 994
+rect 3834 925 3870 959
+rect 3904 925 3934 959
+rect 3834 523 3934 925
+rect 8272 734 8378 752
+rect 8272 682 8305 734
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+rect 3834 489 3870 523
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+rect 3834 464 3934 489
+rect 9802 417 9842 420
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+rect 742 269 840 290
+rect 742 235 768 269
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+rect 742 -499 840 235
+rect 7558 -40 7634 16
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+rect 7558 -128 7634 -92
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+rect 3804 -623 3904 -600
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+rect 3804 -1053 3904 -657
+rect 3804 -1087 3840 -1053
+rect 3874 -1087 3904 -1053
+rect 3804 -1130 3904 -1087
+<< via1 >>
+rect 8305 682 8357 734
+rect 7572 -92 7624 -40
+<< metal2 >>
+rect 8290 823 8380 842
+rect 8290 767 8305 823
+rect 8361 767 8380 823
+rect 8290 734 8380 767
+rect 8290 682 8305 734
+rect 8357 682 8380 734
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+rect 3456 -1282 3506 -6
+rect 7428 -22 7638 -18
+rect 7426 -40 7638 -22
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+rect 7426 -122 7638 -92
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+rect 7426 -586 7488 -272
+rect 3450 -2958 3510 -1282
+rect 7420 -2766 7492 -586
+rect 5068 -2840 6822 -2838
+rect 7420 -2840 7486 -2766
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+rect 3880 -2898 5110 -2896
+rect 6762 -2898 7486 -2896
+rect 3880 -2900 4912 -2898
+rect 3880 -2902 4298 -2900
+<< via2 >>
+rect 8305 767 8361 823
+<< metal3 >>
+rect 8290 973 8380 988
+rect 8290 909 8304 973
+rect 8368 909 8380 973
+rect 8290 823 8380 909
+rect 8290 767 8305 823
+rect 8361 767 8380 823
+rect 8290 754 8380 767
+<< via3 >>
+rect 8304 909 8368 973
+<< metal4 >>
+rect 6774 2270 6876 2296
+rect 7720 2270 8386 2274
+rect 6340 2264 8386 2270
+rect 6228 2262 8386 2264
+rect 5886 2260 8386 2262
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+rect 6774 -176 6872 -114
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+rect 4730 -332 6872 -216
+rect 4730 -336 5494 -332
+use res250_layout res250_layout_0
+timestamp 1624221218
+transform 0 1 296 -1 0 28
+box 218 -342 484 -90
+use switch_layout switch_layout_0
+timestamp 1624221218
+transform 1 0 7394 0 1 -310
+box 40 172 2460 1180
+use 2bitdac_layout 2bitdac_layout_0
+timestamp 1624221218
+transform 1 0 10 0 1 1234
+box -10 -1298 6502 1430
+use 2bitdac_layout 2bitdac_layout_1
+timestamp 1624221218
+transform 1 0 -24 0 1 -1650
+box -10 -1298 6502 1430
+<< labels >>
+rlabel locali s -2 -2910 -2 -2910 4 inp2
+rlabel locali s 206 2306 206 2306 4 inp1
+rlabel locali s 184 -152 184 -152 4 x1_vref5
+rlabel locali s -40 -518 -40 -518 4 x2_vref1
+rlabel locali s 798 -706 798 -706 4 d0
+rlabel locali s 3838 -106 3838 -106 4 d1
+rlabel locali s 7412 268 7412 268 4 d2
+rlabel locali s 6704 1510 6704 1510 4 x1_out_v
+rlabel locali s 6584 -1370 6584 -1370 4 x2_out_v
+rlabel locali s 9986 400 9986 400 4 out_v
+rlabel metal4 s 7546 2226 7546 2226 4 vdd!
+rlabel metal2 s 7462 -2700 7462 -2700 4 gnd!
+<< end >>
diff --git a/mag/4bitdac_layout.mag b/mag/4bitdac_layout.mag
new file mode 100644
index 0000000..9ddf9c6
--- /dev/null
+++ b/mag/4bitdac_layout.mag
@@ -0,0 +1,239 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624221218
+<< checkpaint >>
+rect -1266 -7308 14774 6984
+<< locali >>
+rect 232 5402 290 5482
+rect 13190 3488 13240 3490
+rect 10096 3434 13240 3488
+rect 10096 3428 12540 3434
+rect 7408 2028 7508 3300
+rect 7408 1994 7442 2028
+rect 7476 1994 7508 2028
+rect 7408 1962 7508 1994
+rect 3880 1546 3940 1602
+rect 3880 1420 3948 1546
+rect 7398 1424 7500 1478
+rect 3880 1414 3952 1420
+rect 3884 1069 3952 1414
+rect 3884 1035 3896 1069
+rect 3930 1035 3952 1069
+rect 3884 1022 3952 1035
+rect 7398 1390 7432 1424
+rect 7466 1390 7500 1424
+rect 7398 1034 7500 1390
+rect 7390 862 7500 1034
+rect 3880 741 3948 764
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+rect 3880 707 3898 741
+rect 3932 707 3948 741
+rect 788 464 852 468
+rect 788 430 805 464
+rect 839 430 852 464
+rect 788 424 852 430
+rect 3880 386 3948 707
+rect 794 226 858 234
+rect 794 192 808 226
+rect 842 192 858 226
+rect 794 186 858 192
+rect 20 0 316 46
+rect 266 -280 316 0
+rect 800 -296 846 186
+rect 788 -306 864 -296
+rect 788 -317 866 -306
+rect 788 -351 809 -317
+rect 843 -351 866 -317
+rect 40 -572 90 -358
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+rect 786 -539 860 -518
+rect 40 -622 282 -572
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+rect 796 -1042 846 -754
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+rect 798 -1106 872 -1070
+rect 3884 -1071 3954 -1052
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+rect 3934 -1105 3954 -1071
+rect 3884 -1584 3954 -1105
+rect 7396 -1152 7498 -120
+rect 7396 -1186 7428 -1152
+rect 7462 -1186 7498 -1152
+rect 7396 -1222 7498 -1186
+rect 7398 -1678 7492 -1626
+rect 7398 -1712 7422 -1678
+rect 7456 -1712 7492 -1678
+rect 7398 -2702 7492 -1712
+rect 13196 -2524 13258 -194
+rect 9972 -2584 13266 -2524
+rect 10 -6048 72 -5968
+<< viali >>
+rect 7442 1994 7476 2028
+rect 3896 1035 3930 1069
+rect 7432 1390 7466 1424
+rect 3898 707 3932 741
+rect 805 430 839 464
+rect 808 192 842 226
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+rect 3898 -655 3932 -621
+rect 3900 -1105 3934 -1071
+rect 7428 -1186 7462 -1152
+rect 7422 -1712 7456 -1678
+<< metal1 >>
+rect 7392 2028 7506 2070
+rect 7392 1994 7442 2028
+rect 7476 1994 7506 2028
+rect 7392 1424 7506 1994
+rect 7392 1390 7432 1424
+rect 7466 1390 7506 1424
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+rect 3884 1084 3930 1130
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+rect 11092 -260 11096 -208
+rect 11148 -260 11208 -208
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+rect 788 -306 864 -296
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+rect 3882 -1071 3952 -676
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+rect 3934 -1105 3952 -1071
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+rect 7396 -1134 7500 -1118
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+rect 7390 -1186 7428 -1152
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+rect 7390 -1678 7492 -1218
+rect 7390 -1712 7422 -1678
+rect 7456 -1712 7492 -1678
+rect 7390 -1750 7492 -1712
+<< via1 >>
+rect 11859 539 11911 591
+rect 11096 -260 11148 -208
+<< metal2 >>
+rect 11848 687 11924 702
+rect 11848 631 11860 687
+rect 11916 631 11924 687
+rect 11848 591 11924 631
+rect 11848 539 11859 591
+rect 11911 539 11924 591
+rect 11848 530 11924 539
+rect 6532 -216 6570 218
+rect 11090 -208 11164 -192
+rect 11090 -216 11096 -208
+rect 6532 -260 11096 -216
+rect 11148 -260 11164 -208
+rect 6532 -264 11164 -260
+rect 6532 -5868 6570 -264
+<< via2 >>
+rect 11860 631 11916 687
+<< metal3 >>
+rect 11850 826 11926 840
+rect 11850 772 11860 826
+rect 11848 762 11860 772
+rect 11924 762 11926 826
+rect 11848 687 11926 762
+rect 11848 631 11860 687
+rect 11916 631 11926 687
+rect 11848 620 11926 631
+<< via3 >>
+rect 11860 762 11924 826
+<< metal4 >>
+rect 6842 962 6920 3000
+rect 6820 884 11926 962
+rect 6842 -774 6920 884
+rect 11850 826 11926 884
+rect 11850 762 11860 826
+rect 11924 762 11926 826
+rect 11850 750 11926 762
+use res250_layout res250_layout_0
+timestamp 1624221218
+transform 0 -1 -48 1 0 -668
+box 218 -342 484 -90
+use switch_layout switch_layout_0
+timestamp 1624221218
+transform 1 0 10954 0 1 -454
+box 40 172 2460 1180
+use 3bitdac_layout 3bitdac_layout_0
+timestamp 1624221218
+transform 1 0 54 0 1 3060
+box -54 -3060 10120 2664
+use 3bitdac_layout 3bitdac_layout_1
+timestamp 1624221218
+transform 1 0 48 0 1 -2954
+box -54 -3060 10120 2664
+<< labels >>
+rlabel locali s 13434 248 13434 248 4 out_v
+rlabel locali s 10976 102 10976 102 4 d3
+rlabel locali s 7436 126 7436 126 4 d2
+rlabel locali s 3908 -10 3908 -10 4 d1
+rlabel locali s 818 -52 818 -52 4 d0
+rlabel locali s 202 -604 202 -604 4 x2_vref1
+rlabel locali s 292 -138 292 -138 4 x1_vref5
+rlabel locali s 40 -6024 40 -6024 4 inp2
+rlabel locali s 254 5442 254 5442 4 inp1
+rlabel locali s 10334 -2560 10334 -2560 4 x2_out_v
+rlabel locali s 10594 3462 10594 3462 4 x1_out_v
+rlabel metal2 s 10968 -246 10968 -246 4 gnd!
+rlabel metal4 s 11590 914 11590 914 4 vdd!
+<< end >>
diff --git a/mag/5bitdac_layout.mag b/mag/5bitdac_layout.mag
new file mode 100644
index 0000000..d331ccf
--- /dev/null
+++ b/mag/5bitdac_layout.mag
@@ -0,0 +1,278 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624221218
+<< checkpaint >>
+rect -1330 -13330 17632 13032
+<< locali >>
+rect 236 11484 292 11620
+rect 13494 6278 16080 6312
+rect 13494 6276 16078 6278
+rect 10824 6080 11014 6204
+rect 10824 4040 10940 6080
+rect 10824 4006 10852 4040
+rect 10886 4006 10940 4040
+rect 10824 3958 10940 4006
+rect 7380 2087 7492 3404
+rect 7380 2053 7398 2087
+rect 7432 2053 7492 2087
+rect 7380 2030 7492 2053
+rect 10792 2876 10924 2974
+rect 10792 2842 10860 2876
+rect 10894 2842 10924 2876
+rect 10792 2020 10924 2842
+rect 16042 2424 16078 6276
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+rect 3794 1520 3936 1620
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+rect 754 503 822 828
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+rect 14 -164 76 0
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+rect 10826 -1780 10958 -974
+rect 16062 -1396 16098 598
+rect 10826 -1814 10886 -1780
+rect 10920 -1814 10958 -1780
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+rect 10840 -2820 10972 -2706
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+rect 10840 -5868 10972 -2854
+rect 16044 -3300 16098 -1396
+rect 16044 -5290 16080 -3300
+rect 16042 -5652 16082 -5290
+rect 13412 -5710 16082 -5652
+rect 13412 -5714 16074 -5710
+rect -54 -12070 4 -11964
+<< viali >>
+rect 10852 4006 10886 4040
+rect 7398 2053 7432 2087
+rect 10860 2842 10894 2876
+rect 3809 1046 3843 1080
+rect 7406 1339 7440 1373
+rect 778 469 812 503
+rect 3817 548 3851 582
+rect 776 129 810 163
+rect 786 -221 820 -187
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+rect 3823 -542 3857 -508
+rect 3835 -1032 3869 -998
+rect 7348 -999 7382 -965
+rect 16216 1027 16250 1061
+rect 7364 -1803 7398 -1769
+rect 10886 -1814 10920 -1780
+rect 10886 -2854 10920 -2820
+<< metal1 >>
+rect 10808 4040 10916 4124
+rect 10808 4006 10852 4040
+rect 10886 4006 10916 4040
+rect 10808 2876 10916 4006
+rect 10808 2842 10860 2876
+rect 10894 2842 10916 2876
+rect 10808 2770 10916 2842
+rect 7376 2087 7476 2232
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+rect 10848 -2820 10956 -1814
+rect 10848 -2854 10886 -2820
+rect 10920 -2854 10956 -2820
+rect 10848 -2978 10956 -2854
+<< via1 >>
+rect 14725 1338 14777 1390
+rect 13952 546 14004 598
+<< metal2 >>
+rect 10460 4878 10550 5848
+rect 10460 4866 13424 4878
+rect 10460 4774 13484 4866
+rect 13394 570 13484 4774
+rect 14702 1514 14802 1530
+rect 14700 1510 14802 1514
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+rect 13394 -172 13484 518
+rect 13388 -254 13484 -172
+rect 13388 -4702 13478 -254
+rect 13388 -4746 13484 -4702
+rect 10758 -6932 10840 -6150
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+rect 13394 -6936 13484 -4746
+rect 10744 -7006 13486 -6936
+rect 10758 -7010 10840 -7006
+rect 12108 -7010 13486 -7006
+rect 13394 -7022 13484 -7010
+<< via2 >>
+rect 14725 1454 14781 1510
+<< metal3 >>
+rect 14698 1626 14816 1660
+rect 14698 1562 14728 1626
+rect 14792 1562 14816 1626
+rect 14698 1540 14816 1562
+rect 14702 1510 14798 1540
+rect 14702 1454 14725 1510
+rect 14781 1454 14798 1510
+rect 14702 1434 14798 1454
+<< via3 >>
+rect 14728 1562 14792 1626
+<< metal4 >>
+rect 10134 3322 10222 7012
+rect 10134 1824 10224 3322
+rect 14698 1824 14814 1828
+rect 10130 1712 14814 1824
+rect 10134 -5100 10224 1712
+rect 14698 1626 14814 1712
+rect 14698 1562 14728 1626
+rect 14792 1562 14814 1626
+rect 14698 1540 14814 1562
+use res250_layout res250_layout_0
+timestamp 1624221218
+transform 1 0 -230 0 1 -62
+box 218 -342 484 -90
+use switch_layout switch_layout_0
+timestamp 1624221218
+transform 1 0 13800 0 1 336
+box 40 172 2460 1180
+use 4bitdac_layout 4bitdac_layout_0
+timestamp 1624221218
+transform 1 0 6 0 1 6048
+box -6 -6048 13514 5724
+use 4bitdac_layout 4bitdac_layout_1
+timestamp 1624221218
+transform 1 0 -64 0 1 -5936
+box -6 -6048 13514 5724
+<< labels >>
+rlabel locali s 36 -122 36 -122 4 x1_vref5
+rlabel locali s 188 -432 188 -432 4 x2_vref1
+rlabel locali s 784 -46 784 -46 4 d0
+rlabel locali s 3842 -18 3842 -18 4 d1
+rlabel locali s 7356 -74 7356 -74 4 d2
+rlabel locali s 10878 -158 10878 -158 4 d3
+rlabel locali s 13812 896 13812 896 4 d4
+rlabel locali s 16320 1034 16320 1034 4 out_v
+rlabel locali s 13596 -5688 13596 -5688 4 x2_out_v
+rlabel locali s 13732 6288 13732 6288 4 x1_out_v
+rlabel locali s 262 11508 262 11508 4 inp1
+rlabel locali s 258 11576 258 11576 4 inp1
+rlabel locali s -36 -12014 -36 -12014 4 inp2
+rlabel metal4 s 14500 1778 14500 1778 4 vdd!
+rlabel metal2 s 13440 532 13440 532 4 gnd!
+<< end >>
diff --git a/mag/6bitdac_layout.mag b/mag/6bitdac_layout.mag
new file mode 100644
index 0000000..daef065
--- /dev/null
+++ b/mag/6bitdac_layout.mag
@@ -0,0 +1,376 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624221218
+<< checkpaint >>
+rect -1504 -25390 20976 25102
+<< locali >>
+rect 302 23654 358 23734
+rect 16410 13092 19408 13156
+rect 19358 13050 19408 13092
+rect 13744 12924 13862 13024
+rect 13744 6592 13790 12924
+rect 19358 12682 19412 13050
+rect 19358 11948 19420 12682
+rect 19358 11592 19424 11948
+rect 19358 11198 19416 11592
+rect 19358 10832 19420 11198
+rect 19358 10068 19416 10832
+rect 19358 9674 19412 10068
+rect 19358 9330 19424 9674
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+rect 19358 7038 19412 8946
+rect 19366 6664 19420 7038
+rect 13728 6575 13810 6592
+rect 13728 6541 13754 6575
+rect 13788 6541 13810 6575
+rect 13728 6522 13810 6541
+rect 10752 6176 11058 6318
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+rect 10770 4804 10844 4848
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+rect 10 -112 80 20
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+rect 14660 -9304 14784 -9234
+rect 14668 -10260 14784 -9304
+use res250_layout res250_layout_0
+timestamp 1624221218
+transform 1 0 -462 0 1 -66
+box 218 -342 484 -90
+use switch_layout switch_layout_0
+timestamp 1624221218
+transform 1 0 17134 0 1 -222
+box 40 172 2460 1180
+use 5bitdac_layout 5bitdac_layout_0
+timestamp 1624221218
+transform 1 0 68 0 1 12070
+box -70 -12070 16372 11772
+use 5bitdac_layout 5bitdac_layout_1
+timestamp 1624221218
+transform 1 0 -32 0 1 -11978
+box -70 -12070 16372 11772
+<< labels >>
+rlabel locali s 19666 494 19666 494 4 out_v
+rlabel locali s 17138 330 17138 330 4 d5
+rlabel locali s 19384 1048 19384 1048 4 x1_out_v
+rlabel locali s 19514 -126 19514 -126 4 x2_out_v
+rlabel locali s -160 -152 -160 -152 4 x1_vref5
+rlabel locali s 64 -428 64 -428 4 x2_vref1
+rlabel locali s -66 -24090 -66 -24090 4 inp2
+rlabel locali s 322 23712 322 23712 4 inp1
+rlabel locali s 834 58 834 58 4 d0
+rlabel locali s 3912 -58 3912 -58 4 d1
+rlabel locali s 7406 -58 7406 -58 4 d2
+rlabel locali s 10798 -618 10798 -618 4 d3
+rlabel locali s 13766 -734 13766 -734 4 d4
+rlabel metal4 s 18068 1250 18068 1250 4 vdd!
+rlabel metal2 s 16740 20 16740 20 4 gnd!
+<< end >>
diff --git a/mag/7bitdac_layout.mag b/mag/7bitdac_layout.mag
new file mode 100644
index 0000000..57aebc4
--- /dev/null
+++ b/mag/7bitdac_layout.mag
@@ -0,0 +1,592 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624221218
+<< checkpaint >>
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+<< viali >>
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+<< metal1 >>
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+rect 34194 -1612 34280 -1520
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+rect 21200 -2405 21260 -2390
+rect 21200 -2439 21211 -2405
+rect 21245 -2439 21260 -2405
+rect 21200 -2452 21260 -2439
+<< via1 >>
+rect 43811 25326 43863 25378
+rect 43063 24556 43115 24608
+<< metal2 >>
+rect 19138 48464 24104 48470
+rect 16350 48460 24104 48464
+rect 10768 48384 24104 48460
+rect 10768 48378 19186 48384
+rect 10768 48374 16396 48378
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+rect 37200 23790 41970 23802
+rect 42944 23790 42976 23834
+rect 37200 23756 42976 23790
+rect 42944 23754 42976 23756
+<< via2 >>
+rect 43809 25408 43865 25464
+<< metal3 >>
+rect 43790 25566 43890 25574
+rect 43790 25502 43811 25566
+rect 43875 25502 43890 25566
+rect 43790 25464 43890 25502
+rect 43790 25408 43809 25464
+rect 43865 25408 43890 25464
+rect 43790 25398 43890 25408
+<< via3 >>
+rect 43811 25502 43875 25566
+<< metal4 >>
+rect 7746 48242 7842 48246
+rect 22460 48242 22590 48246
+rect 7746 48160 22590 48242
+rect 7746 47486 7842 48160
+rect 22460 48158 22590 48160
+rect 22514 47824 22590 48158
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+rect 43788 25626 43884 26170
+rect 43788 25612 43890 25626
+rect 43790 25566 43890 25612
+rect 43790 25502 43811 25566
+rect 43875 25502 43890 25566
+rect 43790 25494 43890 25502
+use res250_layout res250_layout_0
+timestamp 1624221218
+transform 1 0 -176 0 1 -20
+box 218 -342 484 -90
+use switch_layout switch_layout_0
+timestamp 1624221218
+transform 1 0 42896 0 1 24336
+box 40 172 2460 1180
+use 6bitdac_layout 6bitdac_layout_0
+timestamp 1624221218
+transform 1 0 20506 0 1 24092
+box -244 -24130 19716 23842
+use 6bitdac_layout 6bitdac_layout_1
+timestamp 1624221218
+transform 1 0 244 0 1 24130
+box -244 -24130 19716 23842
+<< labels >>
+rlabel locali s 86 -116 86 -116 4 x1_vref5
+rlabel locali s 254 -402 254 -402 4 x2_vref1
+rlabel locali s 20436 -88 20436 -88 4 inp2
+rlabel locali s 574 47944 574 47944 4 inp1
+rlabel locali s 42914 24889 42914 24889 4 d6
+rlabel locali s 45424 25060 45424 25060 4 out_v
+rlabel metal4 s 43842 25592 43842 25592 4 vdd!
+rlabel metal2 s 43000 24558 43000 24558 4 gnd!
+rlabel locali s 45196 24296 45196 24296 4 x2_out_v
+rlabel locali s 45154 25632 45154 25632 4 x1_out_v
+rlabel locali s 978 254 978 254 4 d0
+rlabel locali s 3992 214 3992 214 4 d1
+rlabel locali s 10852 480 10852 480 4 d3
+rlabel locali s 14002 926 14002 926 4 d4
+rlabel locali s 17326 810 17326 810 4 d5
+rlabel locali s 7486 -1174 7486 -1174 4 d2
+<< end >>
diff --git a/mag/8bitdac_layout.mag b/mag/8bitdac_layout.mag
new file mode 100644
index 0000000..3088a71
--- /dev/null
+++ b/mag/8bitdac_layout.mag
@@ -0,0 +1,433 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624221218
+<< checkpaint >>
+rect -1260 -2492 97780 52822
+<< locali >>
+rect 45770 51554 90780 51562
+rect 95360 51554 96184 51558
+rect 45770 51520 96184 51554
+rect 45770 51370 45824 51520
+rect 95364 51516 96184 51520
+rect 45770 51336 45777 51370
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+rect 21190 51274 37460 51278
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+rect 27734 -1232 40650 -1230
+<< viali >>
+rect 45777 51336 45811 51370
+rect 20399 51221 20433 51255
+rect 45777 51156 45811 51190
+rect 811 50591 845 50625
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+rect 48521 -1211 48555 -1177
+<< metal1 >>
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+rect 48506 -1177 48574 -1162
+rect 48506 -1211 48521 -1177
+rect 48555 -1211 48574 -1177
+rect 48506 -1224 48574 -1211
+<< via1 >>
+rect 94825 27302 94877 27354
+rect 94073 26526 94125 26578
+<< metal2 >>
+rect 24290 50910 25152 50920
+rect 24290 50906 58282 50910
+rect 24290 50854 58400 50906
+rect 24290 50850 58282 50854
+rect 25120 50848 58282 50850
+rect 94810 27436 94880 27446
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+rect 93934 26586 94146 26592
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+rect 94125 26526 94146 26578
+rect 93914 26500 94146 26526
+rect 93914 26240 93954 26500
+rect 91012 26238 93958 26240
+rect 90500 26202 93958 26238
+rect 90500 26200 92030 26202
+rect 90500 26198 91014 26200
+<< via2 >>
+rect 94816 27380 94872 27436
+<< metal3 >>
+rect 94810 27530 94890 27538
+rect 94810 27466 94820 27530
+rect 94884 27466 94890 27530
+rect 94810 27456 94890 27466
+rect 94810 27436 94880 27456
+rect 94810 27380 94816 27436
+rect 94872 27380 94880 27436
+rect 94810 27372 94880 27380
+<< via3 >>
+rect 94820 27466 94884 27530
+<< metal4 >>
+rect 23762 51496 49764 51500
+rect 22752 51434 49764 51496
+rect 22752 51432 23808 51434
+rect 22764 50622 22848 51432
+rect 49692 50314 49762 51434
+rect 91334 28070 94890 28140
+rect 94816 27590 94890 28070
+rect 94810 27584 94890 27590
+rect 94810 27530 94888 27584
+rect 94810 27466 94820 27530
+rect 94884 27466 94888 27530
+rect 94810 27460 94888 27466
+use 7bitdac_layout 7bitdac_layout_0
+timestamp 1624221218
+transform 1 0 47558 0 1 2444
+box -252 -2456 45562 48686
+use 7bitdac_layout 7bitdac_layout_1
+timestamp 1624221218
+transform 1 0 252 0 1 2456
+box -252 -2456 45562 48686
+use switch_layout switch_layout_0
+timestamp 1624221218
+transform 1 0 93914 0 1 26310
+box 40 172 2460 1180
+use res250_layout res250_layout_0
+timestamp 1624221218
+transform 1 0 20392 0 1 2302
+box 218 -342 484 -90
+<< labels >>
+rlabel locali s 20652 2264 20652 2264 4 x1_vref5
+rlabel locali s 20812 1868 20812 1868 4 x2_vref1
+rlabel locali s 804 50664 804 50664 4 inp1
+rlabel locali s 67994 2294 67994 2294 4 inp2
+rlabel locali s 93952 26862 93952 26862 4 d7
+rlabel locali s 96452 27014 96452 27014 4 out_v
+rlabel locali s 96176 27544 96176 27544 4 x1_out_v
+rlabel locali s 96200 26388 96200 26388 4 x2_out_v
+rlabel metal2 s 93978 26540 93978 26540 4 gnd!
+rlabel metal4 s 94864 27554 94864 27554 4 vdd!
+rlabel locali s 43126 44 43126 44 4 d6
+rlabel locali s 37842 -218 37842 -218 4 d5
+rlabel locali s 34364 612 34364 612 4 d4
+rlabel locali s 31132 486 31132 486 4 d3
+rlabel locali s 27736 152 27736 152 4 d2
+rlabel locali s 24396 40 24396 40 4 d1
+rlabel locali s 21316 -64 21316 -64 4 d0
+<< end >>
diff --git a/mag/9bitdac_layout.mag b/mag/9bitdac_layout.mag
new file mode 100644
index 0000000..fb7b008
--- /dev/null
+++ b/mag/9bitdac_layout.mag
@@ -0,0 +1,590 @@
+magic
+tech sky130A
+magscale 1 2
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+<< viali >>
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+<< metal4 >>
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+use 8bitdac_layout 8bitdac_layout_0
+timestamp 1624221218
+transform 1 0 0 0 1 1232
+box 0 -1232 96520 51562
+use 8bitdac_layout 8bitdac_layout_1
+timestamp 1624221218
+transform 1 0 98026 0 1 1086
+box 0 -1232 96520 51562
+use switch_layout switch_layout_0
+timestamp 1624221218
+transform 1 0 196132 0 1 26700
+box 40 172 2460 1180
+use res250_layout res250_layout_0
+timestamp 1624221218
+transform 1 0 67642 0 1 3396
+box 218 -342 484 -90
+<< labels >>
+rlabel locali s 198666 27404 198666 27404 4 out_v
+rlabel metal4 s 197072 27958 197072 27958 4 vdd!
+rlabel metal2 s 196242 26928 196242 26928 4 gnd!
+rlabel locali s 198396 26794 198396 26794 4 x2_out_v
+rlabel locali s 198392 27904 198392 27904 4 x1_out_v
+rlabel locali s 196140 27266 196140 27266 4 d8
+rlabel locali s 67886 3392 67886 3392 4 x1_vref5
+rlabel locali s 68056 2954 68056 2954 4 x2_vref1
+rlabel locali s 166012 3308 166012 3308 4 inp2
+rlabel locali s 824 51932 824 51932 4 inp1
+rlabel locali s 68780 -66 68780 -66 4 d0
+rlabel locali s 90414 582 90414 582 4 d6
+rlabel locali s 93764 2660 93764 2660 4 d7
+rlabel locali s 85134 -908 85134 -908 4 d5
+rlabel locali s 81746 -1340 81746 -1340 4 d4
+rlabel locali s 78594 -484 78594 -484 4 d3
+rlabel locali s 75332 -1538 75332 -1538 4 d2
+rlabel locali s 71824 -1620 71824 -1620 4 d1
+<< end >>
diff --git a/mag/INV.mag b/mag/INV.mag
new file mode 100644
index 0000000..7f0a1ad
--- /dev/null
+++ b/mag/INV.mag
@@ -0,0 +1,153 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624221218
+<< checkpaint >>
+rect -1348 -1700 1550 1810
+<< nwell >>
+rect 0 334 288 550
+rect 0 0 282 334
+<< pwell >>
+rect 20 -430 278 -312
+<< nmos >>
+rect 130 -242 160 -120
+<< pmos >>
+rect 130 60 160 300
+<< ndiff >>
+rect 42 -163 130 -120
+rect 42 -197 57 -163
+rect 91 -197 130 -163
+rect 42 -242 130 -197
+rect 160 -163 248 -120
+rect 160 -197 199 -163
+rect 233 -197 248 -163
+rect 160 -242 248 -197
+<< pdiff >>
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+rect 50 125 63 159
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+rect 50 60 130 125
+rect 160 232 242 300
+rect 160 198 194 232
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+rect 228 130 242 164
+rect 160 60 242 130
+<< ndiffc >>
+rect 57 -197 91 -163
+rect 199 -197 233 -163
+<< pdiffc >>
+rect 63 193 97 227
+rect 63 125 97 159
+rect 194 198 228 232
+rect 194 130 228 164
+<< psubdiff >>
+rect 20 -368 278 -312
+rect 20 -402 97 -368
+rect 131 -402 179 -368
+rect 213 -402 278 -368
+rect 20 -430 278 -402
+<< nsubdiff >>
+rect 40 451 250 498
+rect 40 447 166 451
+rect 40 413 94 447
+rect 128 417 166 447
+rect 200 417 250 451
+rect 128 413 250 417
+rect 40 378 250 413
+<< psubdiffcont >>
+rect 97 -402 131 -368
+rect 179 -402 213 -368
+<< nsubdiffcont >>
+rect 94 413 128 447
+rect 166 417 200 451
+<< poly >>
+rect 130 300 160 330
+rect -88 -39 -30 -10
+rect -88 -73 -76 -39
+rect -42 -40 -30 -39
+rect 130 -40 160 60
+rect -42 -73 160 -40
+rect -88 -80 160 -73
+rect -88 -102 -30 -80
+rect 130 -120 160 -80
+rect 130 -270 160 -242
+<< polycont >>
+rect -76 -73 -42 -39
+<< locali >>
+rect 10 451 270 520
+rect 10 447 166 451
+rect 10 425 94 447
+rect 10 391 41 425
+rect 75 413 94 425
+rect 128 417 166 447
+rect 200 425 270 451
+rect 200 417 213 425
+rect 128 413 213 417
+rect 75 391 213 413
+rect 247 391 270 425
+rect 10 368 270 391
+rect 50 302 100 368
+rect 50 227 102 302
+rect 50 193 63 227
+rect 97 193 102 227
+rect 50 159 102 193
+rect 50 125 63 159
+rect 97 125 102 159
+rect 50 58 102 125
+rect 190 232 242 300
+rect 190 198 194 232
+rect 228 198 242 232
+rect 190 164 242 198
+rect 190 130 194 164
+rect 228 130 242 164
+rect 190 60 242 130
+rect -88 -39 -30 -10
+rect -88 -73 -76 -39
+rect -42 -73 -30 -39
+rect -88 -102 -30 -73
+rect 190 -120 240 60
+rect 40 -163 100 -120
+rect 40 -197 57 -163
+rect 91 -197 100 -163
+rect 40 -310 100 -197
+rect 190 -163 248 -120
+rect 190 -197 199 -163
+rect 233 -197 248 -163
+rect 190 -240 248 -197
+rect 20 -336 280 -310
+rect 20 -370 52 -336
+rect 86 -338 280 -336
+rect 86 -368 224 -338
+rect 86 -370 97 -368
+rect 20 -402 97 -370
+rect 131 -402 179 -368
+rect 213 -372 224 -368
+rect 258 -372 280 -338
+rect 213 -402 280 -372
+rect 20 -430 280 -402
+<< viali >>
+rect 41 391 75 425
+rect 213 391 247 425
+rect 52 -370 86 -336
+rect 224 -372 258 -338
+<< metal1 >>
+rect 0 425 282 528
+rect 0 420 41 425
+rect -2 391 41 420
+rect 75 391 213 425
+rect 247 420 282 425
+rect 247 391 278 420
+rect -2 358 278 391
+rect 8 -336 290 -298
+rect 8 -370 52 -336
+rect 86 -338 290 -336
+rect 86 -370 224 -338
+rect 8 -372 224 -370
+rect 258 -372 290 -338
+rect 8 -440 290 -372
+<< end >>
diff --git a/mag/cap_28p.mag b/mag/cap_28p.mag
new file mode 100644
index 0000000..e15989c
--- /dev/null
+++ b/mag/cap_28p.mag
@@ -0,0 +1,21 @@
+magic
+tech sky130A
+timestamp 1624221218
+<< checkpaint >>
+rect -1614 -1856 13040 13079
+<< metal1 >>
+rect -984 12417 -496 12449
+rect -984 11818 12410 12417
+rect -984 -1163 12375 11818
+rect -984 -1226 -464 -1163
+rect 11855 -1226 12375 -1163
+<< metal3 >>
+rect -984 12417 -496 12449
+rect -984 11818 12410 12417
+rect -984 11706 12375 11818
+rect -984 -442 -260 11706
+rect 11803 -442 12375 11706
+rect -984 -1163 12375 -442
+rect -984 -1226 -464 -1163
+rect 11855 -1226 12375 -1163
+<< end >>
diff --git a/mag/dot.magicrc.dist b/mag/dot.magicrc.dist
new file mode 100644
index 0000000..94668c3
--- /dev/null
+++ b/mag/dot.magicrc.dist
@@ -0,0 +1,120 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+#---------------------------------------------------------------------
+# 1) must set the variable PDK_ROOT
+#---------------------------------------------------------------------
+
+puts stdout "Sourcing design .magicrc for technology sky130A ..."
+
+#---------------------------------------------------------------------
+
+# Put grid on 0.005 pitch. This is important, as some commands don't
+# rescale the grid automatically (such as lef read?).
+
+set scalefac [tech lambda]
+if {[lindex $scalefac 1] < 2} {
+ scalegrid 1 2
+}
+#---------------------------------------------------------------------
+#
+# Allow override of DRC on/off from environment variable DRC
+#
+#---------------------------------------------------------------------
+if {[catch {set DRC $env(DRC)}]} {
+ # default value
+ drc off
+} else {
+ drc style drc(full)
+ drc euclidean on
+ sdrc $DRC
+}
+#
+#---------------------------------------------------------------------
+# Allow override of PDK path from environment variable PDKPATH
+#
+if {[catch {set PDKPATH $env(PDKPATH)}]} {
+ set PDKPATH "$::env(PDK_ROOT)/sky130A"
+}
+#---------------------------------------------------------------------
+# loading technology
+tech load $PDKPATH/libs.tech/magic/current/sky130A.tech
+
+#---------------------------------------------------------------------
+# load device generator
+source $PDKPATH/libs.tech/magic/current/sky130A.tcl
+
+#---------------------------------------------------------------------
+# load bind keys (optional)
+# source $PDKPATH/libs.tech/magic/current/sky130A-BindKeys
+
+#---------------------------------------------------------------------
+# set units to lambda grid
+snap lambda
+
+#---------------------------------------------------------------------
+
+# set sky130 standard power, ground, and substrate names
+set VDD VPWR
+set GND VGND
+set SUB VSUBS
+
+#---------------------------------------------------------------------
+
+# Allow override of type of magic library views used, "mag" or "maglef",
+# from environment variable MAGTYPE. Deafault value is MAGTYPE=maglef
+
+if {[catch {set MAGTYPE $env(MAGTYPE)}]} {
+ set MAGTYPE maglef
+}
+
+path search [concat "../$MAGTYPE" [path search]]
+
+#---------------------------------------------------------------------
+
+# add path to reference cells
+if {[file isdir ${PDKPATH}/libs.ref/${MAGTYPE}]} {
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_pr
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_io
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hd
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hdll
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hs
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hvl
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_lp
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ls
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ms
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_osu_sc
+} else {
+ addpath ${PDKPATH}/libs.ref/sky130_fd_pr/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_io/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hd/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hdll/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hs/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hvl/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_lp/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ls/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ms/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_osu_sc/${MAGTYPE}
+}
+
+# add path to GDS cells
+
+ addpath ../gds
+
+# add path to IP from catalog. This procedure defined in the PDK script.
+catch {magic::query_mylib_ip}
+# add path to local IP from user design space. Defined in the PDK script.
+catch {magic::query_my_projects}
diff --git a/mag/res250_layout.mag b/mag/res250_layout.mag
new file mode 100644
index 0000000..fb29e47
--- /dev/null
+++ b/mag/res250_layout.mag
@@ -0,0 +1,37 @@
+magic
+tech sky130A
+timestamp 1624221218
+<< checkpaint >>
+rect -521 -801 872 585
+<< ndiff >>
+rect 119 -100 140 -94
+rect 119 -117 121 -100
+rect 138 -117 140 -100
+rect 119 -123 140 -117
+rect 205 -100 226 -93
+rect 205 -117 207 -100
+rect 224 -117 226 -100
+rect 205 -124 226 -117
+<< ndiffc >>
+rect 121 -117 138 -100
+rect 207 -117 224 -100
+<< ndiffres >>
+rect 114 -93 241 -78
+rect 114 -94 205 -93
+rect 114 -123 119 -94
+rect 140 -123 205 -94
+rect 114 -124 205 -123
+rect 226 -124 241 -93
+rect 114 -126 241 -124
+rect 114 -142 242 -126
+<< locali >>
+rect 112 -47 145 -45
+rect 109 -100 154 -47
+rect 109 -117 121 -100
+rect 138 -117 154 -100
+rect 109 -142 154 -117
+rect 195 -100 241 -77
+rect 195 -117 207 -100
+rect 224 -117 241 -100
+rect 195 -171 241 -117
+<< end >>
diff --git a/mag/res500_layout.mag b/mag/res500_layout.mag
new file mode 100644
index 0000000..672ea82
--- /dev/null
+++ b/mag/res500_layout.mag
@@ -0,0 +1,39 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624221218
+<< checkpaint >>
+rect -1042 -1548 1858 1170
+<< ndiff >>
+rect 238 -200 280 -188
+rect 238 -234 242 -200
+rect 276 -234 280 -200
+rect 238 -246 280 -234
+rect 528 -195 570 -184
+rect 528 -229 532 -195
+rect 566 -229 570 -195
+rect 528 -240 570 -229
+<< ndiffc >>
+rect 242 -234 276 -200
+rect 532 -229 566 -195
+<< ndiffres >>
+rect 228 -158 416 -156
+rect 228 -184 596 -158
+rect 228 -188 528 -184
+rect 228 -246 238 -188
+rect 280 -240 528 -188
+rect 570 -240 596 -184
+rect 280 -246 596 -240
+rect 228 -284 596 -246
+rect 416 -286 596 -284
+<< locali >>
+rect 224 -94 290 -90
+rect 218 -200 308 -94
+rect 218 -234 242 -200
+rect 276 -234 308 -200
+rect 218 -284 308 -234
+rect 508 -195 598 -96
+rect 508 -229 532 -195
+rect 566 -229 598 -195
+rect 508 -288 598 -229
+<< end >>
diff --git a/mag/sky130A.tech b/mag/sky130A.tech
new file mode 100644
index 0000000..196d5b9
--- /dev/null
+++ b/mag/sky130A.tech
@@ -0,0 +1,6328 @@
+#------------------------------------------------------------------------
+# Copyright (c) 2020 R. Timothy Edwards
+# Revisions: See below
+#
+# This file is an Open Source foundry process describing
+# the SkyWater sky130 hybrid 0.18um / 0.13um fabrication
+# process. The file may be distributed under the terms
+# of the Apache 2.0 license agreement.
+#
+#------------------------------------------------------------------------
+# This file is designed to be used with magic versions
+# 8.3.24 or newer.
+#------------------------------------------------------------------------
+tech
+ format 35
+ sky130A
+end
+
+version
+ version 1.0.85-0-g32cdb20
+ description "SkyWater SKY130: PRE ALPHA Vendor Open Source rules and DRC"
+end
+
+#------------------------------------------------------------------------
+# Status 7/10/20: Rev 1 (alpha):
+# First public release
+# Status 8/14/20: Rev 2 (alpha):
+# Started updating with new device/model naming convention
+#------------------------------------------------------------------------
+
+#------------------------------------------------------------------------
+# Supported device types
+#------------------------------------------------------------------------
+# device name magic ID layer description
+#------------------------------------------------------------------------
+# sky130_fd_pr__nfet_01v8 nfet standard nFET
+# sky130_fd_pr__nfet_01v8 scnfet standard nFET in standard cell**
+# sky130_fd_pr__special_nfet_latch npd special nFET in SRAM cell
+# sky130_fd_pr__special_nfet_pass npass special nFET in SRAM cell
+# sky130_fd_pr__nfet_01v8_lvt nfetlvt low Vt nFET
+# sky130_fd_bs_flash__special_sonosfet_star nsonos SONOS nFET
+# sky130_fd_pr__pfet_01v8 pfet standard pFET
+# sky130_fd_pr__pfet_01v8 scpfet standard pFET in standard cell**
+# sky130_fd_pr__special_pfet_pass ppu special pFET in SRAM cell
+# sky130_fd_pr__pfet_01v8_lvt pfetlvt low Vt pFET
+# sky130_fd_pr__pfet_01v8_mvt pfetmvt med Vt pFET
+# sky130_fd_pr__pfet_01v8_hvt pfethvt high Vt pFET
+# sky130_fd_pr__nfet_03v3_nvt --- native nFET
+# sky130_fd_pr__pfet_g5v0d10v5 mvpfet thickox pFET
+# sky130_fd_pr__nfet_g5v0d10v5 mvnfet thickox nFET
+# sky130_fd_pr__nfet_01v8_nvt mvnnfet thickox native nFET
+# sky130_fd_pr__diode_pw2nd_05v5 ndiode n+ diff diode
+# sky130_fd_pr__diode_pw2nd_05v5_lvt ndiodelvt low Vt n+ diff diode
+# sky130_fd_pr__diode_pw2nd_05v5_nvt nndiode diode with nndiff
+# sky130_fd_pr__diode_pw2nd_11v0 mvndiode thickox n+ diff diode
+# sky130_fd_pr__diode_pd2nw_05v5 pdiode p+ diff diode
+# sky130_fd_pr__diode_pd2nw_05v5_lvt pdiodelvt low Vt p+ diff diode
+# sky130_fd_pr__diode_pd2nw_05v5_hvt pdiodehvt high Vt p+ diff diode
+# sky130_fd_pr__diode_pd2nw_11v0 mvpdiode thickox p+ diff diode
+# sky130_fd_pr__npn_05v0 pbase NPN in deep nwell
+# sky130_fd_pr__npn_11v0 pbase thick oxide gated NPN
+# sky130_fd_pr__pnp_05v0 nbase PNP
+# sky130_fd_pr__cap_mim_m3_1 mimcap MiM cap 1st plate
+# sky130_fd_pr__cap_mim_m3_2 mimcap2 MiM cap 2nd plate
+# sky130_fd_pr__res_generic_nd rdn n+ diff resistor
+# sky130_fd_pr__res_generic_nd__hv mvrdn thickox n+ diff resistor
+# sky130_fd_pr__res_generic_pd rdp p+ diff resistor
+# sky130_fd_pr__res_generic_pd__nv mvrdp thickox p+ diff resistor
+# sky130_fd_pr__res_generic_l1 rli local interconnect resistor
+# sky130_fd_pr__res_generic_po npres n+ poly resistor
+# sky130_fd_pr__res_high_po_* ppres (*) p+ poly resistor (300 Ohms/sq)
+# sky130_fd_pr__res_xhigh_po_* xres (*) p+ poly resistor (2k Ohms/sq)
+# sky130_fd_pr__cap_var_lvt varactor low Vt varactor
+# sky130_fd_pr__cap_var_hvt varactorhvt high Vt varactor
+# sky130_fd_pr__cap_var mvvaractor thickox varactor
+# sky130_fd_pr__res_iso_pw rpw pwell resistor (in deep nwell)
+#
+# (*) Note that ppres may extract into some generic type called
+# "sky130_fd_pr__res_xhigh_po", but only specific sizes of xhrpoly are
+# allowed, and these are created from fixed layouts like the types below.
+#
+# (**) nFET and pFET in standard cells are the same as devices
+# outside of the standard cell except for the DRC rule for
+# FET to diffusion contact spacing (which is 0.05um, not 0.055um)
+#
+#-------------------------------------------------------------
+# The following devices are not extracted but are represented
+# only by script-generated subcells in the PDK.
+#-------------------------------------------------------------
+# sky130_fd_pr__esd_nfet_01v8 ESD nFET
+# sky130_fd_pr__esd_nfet_g5v0d10v5 ESD thickox nFET
+# sky130_fd_pr__esd_nfet_05v0_nvt ESD native nFET
+# sky130_fd_pr__esd_pfet_g5v0d10v5 ESD thickox pFET
+# sky130_fd_pr__special_nfet_pass_flash flash nFET device
+# sky130_fd_pr__esd_rf_diode_pw2nd_11v0 ESD n+ diode
+# sky130_fd_pr__esd_rf_diode_pd2nw_11v0 ESD p+ diode
+# sky130_fd_pr__cap_vpp_* Vpp cap
+# sky130_fd_pr__ind_* inductor
+# sky130_fd_pr__fuse_m4 metal fuse device
+#--------------------------------------------------------------
+
+#-----------------------------------------------------
+# Tile planes
+#-----------------------------------------------------
+
+planes
+ dwell,dw
+ well,w
+ active,a
+ locali,li1,li
+ metal1,m1
+ metal2,m2
+ metal3,m3
+ cap1,c1
+ metal4,m4
+ cap2,c2
+ metal5,m5
+ metali,mi
+ block,b
+ comment,c
+end
+
+#-----------------------------------------------------
+# Tile types
+#-----------------------------------------------------
+
+types
+# Deep nwell
+ dwell dnwell,dnw
+
+# Wells
+ well nwell,nw
+ well pwell,pw
+ well rpw,rpwell
+ -well obswell
+ well pbase,npn
+ well nbase,pnp
+
+# Transistors
+ active nmos,ntransistor,nfet
+ -active scnmos,scntransistor,scnfet
+ -active npd,npdfet,sramnfet
+ -active npass,npassfet,srampassfet
+ active pmos,ptransistor,pfet
+ -active scpmos,scptransistor,scpfet
+ -active scpmoshvt,scpfethvt
+ -active ppu,ppufet,srampfet
+ active nnmos,nntransistor
+ active mvnmos,mvntransistor,mvnfet
+ active mvpmos,mvptransistor,mvpfet
+ active mvnnmos,mvnntransistor,mvnnfet,nnfet
+ active varactor,varact,var
+ active mvvaractor,mvvaract,mvvar
+
+ active pmoslvt,pfetlvt
+ active pmosmvt,pfetmvt
+ active pmoshvt,pfethvt
+ active nmoslvt,nfetlvt
+ active varactorhvt,varacthvt,varhvt
+ -active nsonos,sonos
+ active sramnvar,corenvar,corenvaractor
+ active srampvar,corepvar,corepvaractor
+
+# Diffusions
+ active ndiff,ndiffusion,ndif
+ active pdiff,pdiffusion,pdif
+ active mvndiff,mvndiffusion,mvndif
+ active mvpdiff,mvpdiffusion,mvpdif
+ active ndiffc,ndcontact,ndc
+ active pdiffc,pdcontact,pdc
+ active mvndiffc,mvndcontact,mvndc
+ active mvpdiffc,mvpdcontact,mvpdc
+ active psubdiff,psubstratepdiff,ppdiff,ppd,psd
+ active nsubdiff,nsubstratendiff,nndiff,nnd,nsd
+ active mvpsubdiff,mvpsubstratepdiff,mvppdiff,mvppd,mvpsd
+ active mvnsubdiff,mvnsubstratendiff,mvnndiff,mvnnd,mvnsd
+ active psubdiffcont,psubstratepcontact,psc
+ active nsubdiffcont,nsubstratencontact,nsc
+ active mvpsubdiffcont,mvpsubstratepcontact,mvpsc
+ active mvnsubdiffcont,mvnsubstratencontact,mvnsc
+ -active obsactive
+ -active mvobsactive
+
+# Poly
+ active poly,p,polysilicon
+ active polycont,pc,pcontact,polycut,polyc
+ active xpolycontact,xpolyc,xpc
+
+# Resistors
+ active npolyres,npres,mrp1
+ active ppolyres,ppres,xhrpoly
+ active xpolyres,xpres,xres,uhrpoly
+ active ndiffres,rnd,rdn,rndiff
+ active pdiffres,rpd,rdp,rpdiff
+ active mvndiffres,mvrnd,mvrdn,mvrndiff
+ active mvpdiffres,mvrpd,mvrdp,mvrpdiff
+ active rmp
+
+# Diodes
+ active pdiode,pdi
+ active ndiode,ndi
+ active nndiode,nndi
+ active pdiodec,pdic
+ active ndiodec,ndic
+ active nndiodec,nndic
+ active mvpdiode,mvpdi
+ active mvndiode,mvndi
+ active mvpdiodec,mvpdic
+ active mvndiodec,mvndic
+ active pdiodelvt,pdilvt
+ active pdiodehvt,pdihvt
+ active ndiodelvt,ndilvt
+ active pdiodelvtc,pdilvtc
+ active pdiodehvtc,pdihvtc
+ active ndiodelvtc,ndilvtc
+
+# Local Interconnect
+ locali locali,li1,li
+ -locali corelocali,coreli1,coreli
+ locali rlocali,rli1,rli
+ locali viali,vial,mcon,lic,licon,m1c,v0
+ -locali obsli1,obsli
+ -locali obsli1c,obslic,obslicon
+
+# Metal 1
+ metal1 metal1,m1,met1
+ metal1 rmetal1,rm1,rmet1
+ metal1 via1,m2contact,m2cut,m2c,via,v,v1
+ -metal1 obsm1
+ metal1 padl
+ -metal1 m1fill
+
+# Metal 2
+ metal2 metal2,m2,met2
+ metal2 rmetal2,rm2,rmet2
+ metal2 via2,m3contact,m3cut,m3c,v2
+ -metal2 obsm2
+ -metal2 m2fill
+
+# Metal 3
+ metal3 metal3,m3,met3
+ metal3 rmetal3,rm3,rmet3
+ -metal3 obsm3
+ metal3 via3,v3
+ -metal3 m3fill
+
+ cap1 mimcap,mim,capm
+ cap1 mimcapcontact,mimcapc,mimcc,capmc
+
+# Metal 4
+ metal4 metal4,m4,met4
+ metal4 rmetal4,rm4,rmet4
+ -metal4 obsm4
+ metal4 via4,v4
+ -metal4 m4fill
+
+ cap2 mimcap2,mim2,capm2
+ cap2 mimcap2contact,mimcap2c,mim2cc,capm2c
+
+# Metal 5
+ metal5 metal5,m5,met5
+ metal5 rm5,rmetal5,rmet5
+ -metal5 obsm5
+ -metal5 m5fill
+
+ metal5 mrdlcontact,mrdlc
+ metali metalrdl,mrdl,metrdl
+ -metali obsmrdl
+
+# Miscellaneous
+ -block glass
+ -block fillblock
+ comment comment
+ -comment obscomment
+# fixed resistor width identifiers
+ -comment res0p35
+ -comment res0p69
+ -comment res1p41
+ -comment res2p85
+ -comment res5p73
+
+end
+
+#-----------------------------------------------------
+# Magic contact types
+#-----------------------------------------------------
+
+contact
+ pc poly locali
+ ndc ndiff locali
+ pdc pdiff locali
+ nsc nsd locali
+ psc psd locali
+ ndic ndiode locali
+ ndilvtc ndiodelvt locali
+ nndic nndiode locali
+ pdic pdiode locali
+ pdilvtc pdiodelvt locali
+ pdihvtc pdiodehvt locali
+ xpc xpc locali
+
+ mvndc mvndiff locali
+ mvpdc mvpdiff locali
+ mvnsc mvnsd locali
+ mvpsc mvpsd locali
+ mvndic mvndiode locali
+ mvpdic mvpdiode locali
+
+ lic locali metal1
+ obslic obsli metal1
+
+ via1 metal1 metal2
+ via2 metal2 metal3
+ via3 metal3 metal4
+ via4 metal4 metal5
+ stackable
+
+ # MiM cap contacts are not stackable!
+ mimcc mimcap metal4
+ mim2cc mimcap2 metal5
+
+ padl m1 m2 m3 m4 m5 glass
+
+ mrdlc metal5 mrdl
+end
+
+#-----------------------------------------------------
+# Layer aliases
+#-----------------------------------------------------
+
+aliases
+
+ allwellplane nwell
+ allnwell nwell,obswell,pnp
+
+ allnfets nfet,npass,npd,scnfet,mvnfet,mvnnfet,nfetlvt,nsonos
+ allpfets pfet,ppu,scpfet,scpfethvt,mvpfet,pfethvt,pfetlvt,pfetmvt
+ allfets allnfets,allpfets,varactor,mvvaractor,varhvt,corenvar,corepvar
+ allfetsstd nfet,mvnfet,mvnnfet,nfetlvt,pfet,mvpfet,pfethvt,pfetlvt,pfetmvt
+ allfetsspecial scnfet,scpfet,scpfethvt
+ allfetscore npass,npd,nsonos,ppu,corenvar,corepvar
+ allfetsnolvt nfet,npass,npd,scnfet,mvnfet,mvnnfet,nsonos,pfet,ppu,scpfet,scpfethvt,mvpfet,pfethvt,pfetmvt,varactor,mvvaractor,varhvt,corenvar
+
+ allnactivenonfet *ndiff,*nsd,*ndiode,*nndiode,*mvndiff,*mvnsd,*mvndiode,*ndiodelvt
+ allnactive allnactivenonfet,allnfets
+ allnactivenontap *ndiff,*ndiode,*nndiode,*mvndiff,*mvndiode,*ndiodelvt,allnfets
+ allnactivetap *nsd,*mvnsd,var,varhvt,mvvar,corenvar
+
+ allpactivenonfet *pdiff,*psd,*pdiode,*mvpdiff,*mvpsd,*mvpdiode,*pdiodelvt,*pdiodehvt
+ allpactive allpactivenonfet,allpfets
+ allpactivenontap *pdiff,*pdiode,*mvpdiff,*mvpdiode,*pdiodelvt,*pdiodehvt,allpfets
+ allpactivetap *psd,*mvpsd,corepvar
+
+ allactivenonfet allnactivenonfet,allpactivenonfet
+ allactive allactivenonfet,allfets
+
+ allactiveres ndiffres,pdiffres,mvndiffres,mvpdiffres
+
+ allndifflv *ndif,*nsd,*ndiode,ndiffres,nfet,npass,npd,scnfet,nfetlvt,nsonos
+ allpdifflv *pdif,*psd,*pdiode,pdiffres,pfet,ppu,scpfet,scpfethvt,pfetlvt,pfetmvt,pfethvt
+ alldifflv allndifflv,allpdifflv
+ allndifflvnonfet *ndif,*nsd,*ndiode,*nndiode,ndiffres,*ndiodelvt
+ allpdifflvnonfet *pdif,*psd,*pdiode,pdiffres,*pdiodelvt,*pdiodehvt
+ alldifflvnonfet allndifflvnonfet,allpdifflvnonfet
+
+ allndiffmv *mvndif,*mvnsd,*mvndiode,*nndiode,mvndiffres,mvnfet,mvnnfet
+ allpdiffmv *mvpdif,*mvpsd,*mvpdiode,mvpdiffres,mvpfet
+ alldiffmv allndiffmv,allpdiffmv
+ allndiffmvnontap *mvndif,*mvndiode,*nndiode,mvndiffres,mvnfet,mvnnfet
+ allpdiffmvnontap *mvpdif,*mvpdiode,mvpdiffres,mvpfet
+ alldiffmvnontap allndiffmvnontap,allpdiffmvnontap
+ allndiffmvnonfet *mvndif,*mvnsd,*mvndiode,*nndiode,mvndiffres
+ allpdiffmvnonfet *mvpdif,*mvpsd,*mvpdiode,mvpdiffres
+ alldiffmvnonfet allndiffmvnonfet,allpdiffmvnonfet
+
+ alldiffnonfet alldifflvnonfet,alldiffmvnonfet
+ alldiff alldifflv,alldiffmv
+
+ allpolyres mrp1,xhrpoly,uhrpoly,rmp
+ allpolynonfet *poly,allpolyres,xpc
+ allpolynonres *poly,allfets,xpc
+
+ allpoly allpolynonfet,allfets
+ allpolynoncap *poly,xpc,allfets,allpolyres
+
+ allndiffcontlv ndc,nsc,ndic,nndic,ndilvtc
+ allpdiffcontlv pdc,psc,pdic,pdilvtc,pdihvtc
+ allndiffcontmv mvndc,mvnsc,mvndic
+ allpdiffcontmv mvpdc,mvpsc,mvpdic
+ allndiffcont allndiffcontlv,allndiffcontmv
+ allpdiffcont allpdiffcontlv,allpdiffcontmv
+ alldiffcontlv allndiffcontlv,allpdiffcontlv
+ alldiffcontmv allndiffcontmv,allpdiffcontmv
+ alldiffcont alldiffcontlv,alldiffcontmv
+
+ allcont alldiffcont,pc
+
+ allres allpolyres,allactiveres
+
+ allli *locali,coreli,rli
+ allm1 *m1,rm1
+ allm2 *m2,rm2
+ allm3 *m3,rm3
+ allm4 *m4,rm4
+ allm5 *m5,rm5
+
+ allpad padl
+
+ psub pwell
+
+end
+
+#-----------------------------------------------------
+# Layer drawing styles
+#-----------------------------------------------------
+
+styles
+ styletype mos
+ dnwell cwell
+ nwell nwell
+ pwell pwell
+ rpwell pwell ptransistor_stripes
+ ndiff ndiffusion
+ pdiff pdiffusion
+ nsd ndiff_in_nwell
+ psd pdiff_in_pwell
+ nfet ntransistor ntransistor_stripes
+ scnfet ntransistor ntransistor_stripes
+ npass ntransistor ntransistor_stripes
+ npd ntransistor ntransistor_stripes
+ pfet ptransistor ptransistor_stripes
+ scpfet ptransistor ptransistor_stripes
+ scpfethvt ptransistor ptransistor_stripes implant2
+ ppu ptransistor ptransistor_stripes
+ var polysilicon ndiff_in_nwell
+ ndc ndiffusion metal1 contact_X'es
+ pdc pdiffusion metal1 contact_X'es
+ nsc ndiff_in_nwell metal1 contact_X'es
+ psc pdiff_in_pwell metal1 contact_X'es
+ corenvar polysilicon ndiff_in_nwell
+ corepvar polysilicon pdiff_in_pwell
+
+ pnp nwell ntransistor_stripes
+ npn pwell ptransistor_stripes
+
+ pfetlvt ptransistor ptransistor_stripes implant1
+ pfetmvt ptransistor ptransistor_stripes implant3
+ pfethvt ptransistor ptransistor_stripes implant2
+ nfetlvt ntransistor ntransistor_stripes implant1
+ nsonos ntransistor implant3
+ varhvt polysilicon ndiff_in_nwell implant2
+
+ mvndiff ndiffusion hvndiff_mask
+ mvpdiff pdiffusion hvpdiff_mask
+ mvnsd ndiff_in_nwell hvndiff_mask
+ mvpsd pdiff_in_pwell hvpdiff_mask
+ mvnfet ntransistor ntransistor_stripes hvndiff_mask
+ mvnnfet ntransistor ndiff_in_nwell hvndiff_mask
+ mvpfet ptransistor ptransistor_stripes
+ mvvar polysilicon ndiff_in_nwell hvndiff_mask
+ mvndc ndiffusion metal1 contact_X'es hvndiff_mask
+ mvpdc pdiffusion metal1 contact_X'es hvpdiff_mask
+ mvnsc ndiff_in_nwell metal1 contact_X'es hvndiff_mask
+ mvpsc pdiff_in_pwell metal1 contact_X'es hvpdiff_mask
+
+ poly polysilicon
+ pc polysilicon metal1 contact_X'es
+ npolyres polysilicon silicide_block nselect2
+ ppolyres polysilicon silicide_block pselect2
+ xpc polysilicon pselect2 metal1 contact_X'es
+ rmp polysilicon poly_resist_stripes
+
+ res0p35 implant1
+ res0p69 implant1
+ res1p41 implant1
+ res2p85 implant1
+ res5p73 implant1
+
+ pdiode pdiffusion pselect2
+ ndiode ndiffusion nselect2
+ pdiodec pdiffusion pselect2 metal1 contact_X'es
+ ndiodec ndiffusion nselect2 metal1 contact_X'es
+
+ nndiode ndiffusion nselect2 implant3
+ ndiodelvt ndiffusion nselect2 implant1
+ pdiodelvt pdiffusion pselect2 implant1
+ pdiodehvt pdiffusion pselect2 implant2
+ pdilvtc pdiffusion pselect2 implant1 metal1 contact_X'es
+ pdihvtc pdiffusion pselect2 implant2 metal1 contact_X'es
+ ndilvtc ndiffusion nselect2 implant1 metal1 contact_X'es
+
+ mvpdiode pdiffusion pselect2 hvpdiff_mask
+ mvndiode ndiffusion nselect2 hvndiff_mask
+ mvpdiodec pdiffusion pselect2 metal1 contact_X'es hvpdiff_mask
+ mvndiodec ndiffusion nselect2 metal1 contact_X'es hvndiff_mask
+ nndiodec ndiff_in_nwell nselect2 metal1 contact_X'es hvndiff_mask
+
+ locali metal1
+ coreli metal1
+ rli metal1 poly_resist_stripes
+ lic metal1 metal2 via1arrow
+ obsli metal1
+ obslic metal1 metal2 via1arrow
+
+ metal1 metal2
+ m1fill metal2
+ rm1 metal2 poly_resist_stripes
+ obsm1 metal2
+ m2c metal2 metal3 via2arrow
+ metal2 metal3
+ m2fill metal3
+ rm2 metal3 poly_resist_stripes
+ obsm2 metal3
+ m3c metal3 metal4 via3alt
+ metal3 metal4
+ m3fill metal4
+ rm3 metal4 poly_resist_stripes
+ obsm3 metal4
+ mimcap metal3 mems
+ mimcc metal3 contact_X'es mems
+ mimcap2 metal4 mems
+ mim2cc metal4 contact_X'es mems
+ via3 metal4 metal5 via4
+ metal4 metal5
+ m4fill metal5
+ rm4 metal5 poly_resist_stripes
+ obsm4 metal5
+ via4 metal5 metal6 via5
+ metal5 metal6
+ m5fill metal6
+ rm5 metal6 poly_resist_stripes
+ obsm5 metal6
+ mrdlc metal6 metal7 via6
+ metalrdl metal7
+ obsmrdl metal7
+
+ glass overglass
+ mrp1 poly_resist poly_resist_stripes
+ xhrpoly poly_resist silicide_block
+ uhrpoly poly_resist
+ ndiffres ndiffusion ndop_stripes
+ pdiffres pdiffusion pdop_stripes
+ mvndiffres ndiffusion hvndiff_mask ndop_stripes
+ mvpdiffres pdiffusion hvpdiff_mask pdop_stripes
+ comment comment
+ error_p error_waffle
+ error_s error_waffle
+ error_ps error_waffle
+ fillblock cwell
+
+ obswell cwell
+ obsactive implant4
+
+ padl metal6 via6 overglass
+
+ magnet substrate_field_implant
+ rotate via3alt
+ fence via5
+end
+
+#-----------------------------------------------------
+# Special paint/erase rules
+#-----------------------------------------------------
+
+compose
+ compose nfet poly ndiff
+ compose pfet poly pdiff
+ compose var poly nsd
+
+ compose mvnfet poly mvndiff
+ compose mvpfet poly mvpdiff
+ compose mvvar poly mvnsd
+
+ paint obslic locali via1
+ paint obslic obsm1 obsli,obsm1
+
+ paint ndc nwell pdc
+ paint nfet nwell pfet
+ paint scnfet nwell scpfet
+ paint ndiff nwell pdiff
+ paint psd nwell nsd
+ paint psc nwell nsc
+ paint npd nwell ppu
+
+ paint pdc pwell ndc
+ paint pfet pwell nfet
+ paint scpfet pwell scnfet
+ paint pdiff pwell ndiff
+ paint nsd pwell psd
+ paint nsc pwell psc
+ paint ppu pwell npd
+
+ paint pdc coreli pdc
+ paint ndc coreli ndc
+ paint pc coreli pc
+ paint nsc coreli nsc
+ paint psc coreli psc
+ paint viali coreli viali
+
+ paint coreli pdc pdc
+ paint coreli ndc ndc
+ paint coreli pc pc
+ paint coreli nsc nsc
+ paint coreli psc psc
+ paint coreli viali viali
+
+ paint m4 obsm4 m4
+ paint m5 obsm5 m5
+end
+
+#-----------------------------------------------------
+# Electrical connectivity
+#-----------------------------------------------------
+
+connect
+ *nwell,*nsd,*mvnsd,dnwell,pnp *nwell,*nsd,*mvnsd,dnwell,pnp
+ pwell,*psd,*mvpsd,npn pwell,*psd,*mvpsd,npn
+ *li,coreli *li,coreli
+ *m1,m1fill,obslic *m1,m1fill,obslic
+ *m2,m2fill *m2,m2fill
+ *m3,m3fill *m3,m3fill
+ *m4,m4fill *m4,m4fill
+ *m5,m5fill *m5,m5fill
+ *mimcap *mimcap
+ *mimcap2 *mimcap2
+ allnactivenonfet allnactivenonfet
+ allpactivenonfet allpactivenonfet
+ *poly,xpc,allfets *poly,xpc,allfets
+ # RDL connects to m5 (i.e., padl) through glass cut
+ *mrdl *mrdl
+ glass metrdl
+end
+
+#-----------------------------------------------------
+# CIF/GDS output layer definitions
+#-----------------------------------------------------
+# NOTE: All values in this section MUST be multiples of 25
+# or else magic will scale below the allowed layout grid size
+
+cifoutput
+
+#----------------------------------------------------------------
+style gdsii
+# NOTE: This section is used for actual GDS output
+#----------------------------------------------------------------
+ scalefactor 10 nanometers
+ options calma-permissive-labels
+ gridlimit 5
+
+#----------------------------------------------------------------
+# Create a temp layer from the cell bounding box for use in
+# generating ID layers. Note that "boundary", unlike "bbox",
+# requires the FIXED_BBOX property (abutment box) in the cell.
+#----------------------------------------------------------------
+ templayer CELLBOUND
+ boundary
+
+#----------------------------------------------------------------
+# BOUND
+#----------------------------------------------------------------
+ layer BOUND CELLBOUND
+ calma 235 4
+
+# Create a boundary outside of an abutment box, so that layers
+# can be made to stretch to the abutment box edges. First strink
+# so that any box that would be so small as to interact with
+# itself will be removed.
+
+ templayer CELLRING CELLBOUND
+ shrink 345
+ grow 545
+ and-not CELLBOUND
+
+#----------------------------------------------------------------
+# DNWELL
+#----------------------------------------------------------------
+
+ layer DNWELL dnwell,pnp
+ calma 64 18
+
+ layer PWRES rpw
+ and dnwell
+ calma 64 13
+
+#----------------------------------------------------------------
+# NWELL
+#----------------------------------------------------------------
+
+ layer NWELL allnwell
+ bloat-all rpw dnwell
+ and-not rpw,pwell
+ calma 64 20
+
+ layer WELLTXT
+ labels allnwell noport
+ calma 64 16
+
+ layer WELLPIN
+ labels allnwell port
+ calma 64 5
+
+#----------------------------------------------------------------
+# SUB (text/port only)
+#----------------------------------------------------------------
+
+ layer SUBTXT
+ labels pwell noport
+ calma 122 16
+
+ layer SUBPIN
+ labels pwell port
+ calma 64 59
+
+#----------------------------------------------------------------
+# DIFF
+#----------------------------------------------------------------
+
+ layer DIFF allnactivenontap,allpactivenontap,allactiveres
+ labels allnactivenontap,allpactivenontap
+ calma 65 20
+
+#----------------------------------------------------------------
+# TAP
+#----------------------------------------------------------------
+
+ layer TAP allnactivetap,allpactivetap
+ labels allnactivetap,allpactivetap
+ calma 65 44
+
+#----------------------------------------------------------------
+# PPLUS, NPLUS (PSDM, NSDM)
+#----------------------------------------------------------------
+
+ templayer basePPLUS pdiffres,mvpdiffres
+ grow 15
+ or xhrpoly,uhrpoly,xpc
+ grow 110
+ bloat-or allpactivetap * 125 allnactivenontap 0
+ bloat-or allpactivenontap * 125 allnactivetap 0
+
+ templayer baseNPLUS ndiffres,mvndiffres
+ grow 125
+ bloat-or allnactivetap * 125 allpactivenontap 0
+ bloat-or allnactivenontap * 125 allpactivetap 0
+
+ templayer extendPPLUS basePPLUS,CELLRING
+ bridge 380 380
+ and-not baseNPLUS
+ and-not CELLRING
+
+ layer PPLUS basePPLUS,extendPPLUS
+ grow 185
+ shrink 185
+ close 265000
+ calma 94 20
+
+ templayer extendNPLUS baseNPLUS,CELLRING
+ bridge 380 380
+ and-not basePPLUS
+ and-not CELLRING
+
+ layer NPLUS baseNPLUS,extendNPLUS
+ grow 185
+ shrink 185
+ close 265000
+ calma 93 44
+
+#----------------------------------------------------------------
+# LVTN
+#----------------------------------------------------------------
+
+ layer LVTN pfetlvt,nfetlvt,mvvar,mvnnfet,nsonos,*pdiodelvt,*ndiodelvt,*nndiode
+ grow 180
+ bridge 380 380
+ grow 185
+ shrink 185
+ close 265000
+ calma 125 44
+
+#----------------------------------------------------------------
+# HVTR
+#----------------------------------------------------------------
+
+ layer HVTR pfetmvt
+ grow 180
+ bridge 380 380
+ grow 185
+ shrink 185
+ close 265000
+ calma 18 20
+
+#----------------------------------------------------------------
+# HVTP
+#----------------------------------------------------------------
+
+ layer HVTP scpfethvt,ppu,pfethvt,varhvt,*pdiodehvt
+ grow 180
+ bridge 380 380
+ grow 185
+ shrink 185
+ close 265000
+ calma 78 44
+
+#----------------------------------------------------------------
+# SONOS
+#----------------------------------------------------------------
+
+ layer SONOS nsonos
+ grow 100
+ grow-min 410
+ bridge 500 410
+ grow 250
+ shrink 250
+ calma 80 20
+
+#----------------------------------------------------------------
+# SONOS requires COREID around area (areaid.ce). Also, the
+# coreli layer indicates a cell needing COREID. Also, devices
+# npd, npass, and ppu indicate a COREID cell.
+#----------------------------------------------------------------
+
+ layer COREID
+ bloat-all nsonos,coreli,ppu,npd,npass,corepvar,corenvar CELLBOUND
+ calma 81 2
+
+#----------------------------------------------------------------
+# STDCELL applies to all cells containing scnfet or scpfet.
+#----------------------------------------------------------------
+
+ layer STDCELL scnfet
+ bloat-all scpfet,scpfethvt,scnfet CELLBOUND
+ calma 81 4
+
+#----------------------------------------------------------------
+# NPNID and PNPID apply to bipolar transistors
+#----------------------------------------------------------------
+
+ layer NPNID
+ bloat-all npn dnwell
+ calma 82 20
+
+ templayer pnparea pnp
+ grow 400
+
+ layer PNPID
+ bloat-all pnparea *psd
+ or pnparea
+ calma 82 44
+
+#----------------------------------------------------------------
+# RPM
+#----------------------------------------------------------------
+
+ layer RPM
+ bloat-all xhrpoly xpc
+ grow 200
+ grow-min 1270
+ grow 420
+ shrink 420
+ calma 86 20
+
+#----------------------------------------------------------------
+# URPM (2kOhms/sq. poly implant)
+#----------------------------------------------------------------
+
+ layer URPM
+ bloat-all uhrpoly xpc
+ grow 200
+ grow-min 1270
+ grow 420
+ shrink 420
+ calma 79 20
+
+#----------------------------------------------------------------
+# LDNTM (Tip implant for SONOS FETs)
+#----------------------------------------------------------------
+
+ layer LDNTM
+ bloat-all nsonos *ndiff
+ grow 185
+ grow 345
+ shrink 345
+ calma 11 44
+
+#----------------------------------------------------------------
+# HVNTM (Tip implant for MV ndiff devices)
+#----------------------------------------------------------------
+
+ templayer hvntm_block *mvpsd
+ grow 185
+
+ layer HVNTM
+ bloat-all mvnfet,mvnnfet,*mvndiode,mvrdn,*nndiode *mvndiff
+ bloat-all mvvaractor *mvnsd
+ and-not hvntm_block
+ grow 185
+ grow 345
+ shrink 345
+ and-not hvntm_block
+ calma 125 20
+
+#----------------------------------------------------------------
+# POLY
+#----------------------------------------------------------------
+
+ layer POLY allpoly
+ calma 66 20
+
+ layer POLYTXT
+ labels allpoly noport
+ calma 66 16
+
+ layer POLYPIN
+ labels allpoly port
+ calma 66 5
+
+#----------------------------------------------------------------
+# THKOX (HVI) (includes rules NWELL 8-11 and DIFFTAP 14-26)
+#----------------------------------------------------------------
+
+ templayer thkox_area alldiffmv,mvvar
+ grow 185
+ bloat-all alldiffmv nwell
+ grow 345
+ shrink 345
+
+ templayer large_ptap_mv thkox_area
+ shrink 420
+ grow 420
+
+ templayer small_ptap_mv thkox_area
+ and-not large_ptap_mv
+ # (HVI min width rule is 0.6 but CNTM min width rule is 0.84um)
+ grow-min 840
+
+ templayer baseTHKOX thkox_area,small_ptap_mv
+ bridge 700 600
+ grow 345
+ shrink 345
+
+ templayer extendTHKOX baseTHKOX,CELLRING
+ grow 345
+ shrink 345
+ and-not CELLRING
+
+ layer THKOX baseTHKOX,extendTHKOX
+ calma 75 20
+
+#----------------------------------------------------------------
+# CONT (LICON)
+#----------------------------------------------------------------
+
+ layer CONT allcont
+ squares-grid 0 170 170
+ calma 66 44
+
+ # Contact for pres is different than other LICON contacts
+ # See rules LICON 1b, 1c (width/length) and 2b (spacing)
+ templayer xpc_horiz xpc
+ shrink 1007
+ grow 1007
+
+ layer CONT xpc
+ and-not xpc_horiz
+ # Force long edge vertical for contacts narrower than 2um
+ # Minimum space is 350 but 520 satisfies no. of contacts rule
+ slots 80 190 520 80 2000 350
+ calma 66 44
+
+ layer CONT xpc
+ and xpc_horiz
+ # Force long edge vertical for contacts wider than 2um
+ # Minimum space is 350 but 520 satisfies no. of contacts rule
+ slots 80 2000 350 80 190 520
+ calma 66 44
+
+#----------------------------------------------------------------
+# NPC (Nitride poly cut)
+# surrounds CONT (LICON) on poly only (i.e., pc)
+#----------------------------------------------------------------
+
+ layer NPC pc
+ squares-grid 0 170 170
+ grow 100
+ bridge 270 270
+ grow 130
+ shrink 130
+ calma 95 20
+
+ # NPC is also generated on xhrpoly and uhrpoly resistors
+
+ layer NPC xpc,xhrpoly,uhrpoly
+ # xpc surrounds precision_resistor by 0.095um
+ grow 95
+ grow 130
+ shrink 130
+ calma 95 20
+
+#----------------------------------------------------------------
+# Device markers
+#----------------------------------------------------------------
+
+ layer DIFFRES rdn,mvrdn,rdp,mvrdp
+ calma 65 13
+
+ layer POLYRES mrp1
+ calma 66 13
+
+ # POLYSHORT is a poly layer resistor like rli, rm1, etc., for metal layers
+ layer POLYSHORT rmp
+ calma 66 15
+
+ # POLYRES extends to edge of contact cut
+ layer POLYRES xhrpoly,uhrpoly
+ grow 60
+ and xpc
+ or xhrpoly,uhrpoly
+ calma 66 13
+
+ layer DIODE *pdi,*ndi,*nndi,*mvpdi,*mvndi,*pdilvt,*pdihvt,*ndilvt
+ # To be done: Expand to include anode, cathode, and guard ring
+ calma 81 23
+
+#----------------------------------------------------------------
+# LI
+#----------------------------------------------------------------
+ layer LI allli
+ calma 67 20
+
+ layer LITXT
+ labels *locali,coreli noport
+ calma 67 16
+
+ layer LIPIN
+ labels *locali,coreli port
+ calma 67 5
+
+ layer LIRES rli
+ labels rli
+ calma 67 13
+
+#----------------------------------------------------------------
+# MCON
+#----------------------------------------------------------------
+ layer MCON lic
+ squares-grid 0 170 190
+ calma 67 44
+
+#----------------------------------------------------------------
+# MET1
+#----------------------------------------------------------------
+ layer MET1 allm1,m1fill
+ calma 68 20
+
+ layer MET1TXT
+ labels allm1 noport
+ calma 68 16
+
+ layer MET1PIN
+ labels allm1 port
+ calma 68 5
+
+ layer MET1RES rm1
+ labels rm1
+ calma 68 13
+
+#----------------------------------------------------------------
+# VIA1
+#----------------------------------------------------------------
+ layer VIA1 via1
+ squares-grid 55 150 170
+ calma 68 44
+
+#----------------------------------------------------------------
+# MET2
+#----------------------------------------------------------------
+ layer MET2 allm2,m2fill
+ calma 69 20
+
+ layer MET2TXT
+ labels allm2 noport
+ calma 69 16
+
+ layer MET2PIN
+ labels allm2 port
+ calma 69 5
+
+ layer MET2RES rm2
+ labels rm2
+ calma 69 13
+
+#----------------------------------------------------------------
+# VIA2
+#----------------------------------------------------------------
+ layer VIA2 via2
+ squares-grid 40 200 200
+ calma 69 44
+
+#----------------------------------------------------------------
+# MET3
+#----------------------------------------------------------------
+ layer MET3 allm3,m3fill
+ calma 70 20
+
+ layer MET3TXT
+ labels allm3 noport
+ calma 70 16
+
+ layer MET3PIN
+ labels allm3 port
+ calma 70 5
+
+ layer MET3RES rm3
+ labels rm3
+ calma 70 13
+
+#----------------------------------------------------------------
+# VIA3
+#----------------------------------------------------------------
+ layer VIA3 via3
+ or mimcc
+ squares-grid 60 200 200
+ calma 70 44
+
+#----------------------------------------------------------------
+# MET4
+#----------------------------------------------------------------
+ layer MET4 allm4,m4fill
+ calma 71 20
+
+ layer MET4TXT
+ labels allm4 noport
+ calma 71 16
+
+ layer MET4PIN
+ labels allm4 port
+ calma 71 5
+
+ layer MET4RES rm4
+ labels rm4
+ calma 71 13
+
+#----------------------------------------------------------------
+# VIA4
+#----------------------------------------------------------------
+ layer VIA4 via4
+ or mim2cc
+ squares-grid 190 800 800
+ calma 71 44
+
+#----------------------------------------------------------------
+# MET5
+#----------------------------------------------------------------
+ layer MET5 allm5,m5fill
+ calma 72 20
+
+ layer MET5TXT
+ labels allm5 noport
+ calma 72 16
+
+ layer MET5PIN
+ labels allm5 port
+ calma 72 5
+
+ layer MET5RES rm5
+ labels rm5
+ calma 72 13
+
+
+#----------------------------------------------------------------
+# RDL
+#----------------------------------------------------------------
+ layer RDL *metrdl
+ calma 74 20
+
+ layer RDLTXT
+ labels *metrdl noport
+ calma 74 16
+
+ layer RDLPIN
+ labels *metrdl port
+ calma 74 5
+
+ layer PI1 *metrdl
+ and padl,glass
+ # Test only---needs GDS layer number
+
+ layer UBM *metrdl
+ shrink 50000
+ grow 40000
+ # Test only---needs GDS layer number
+
+ layer PI2 *metrdl
+ shrink 50000
+ grow 25000
+ # Test only---needs GDS layer number
+
+
+#----------------------------------------------------------------
+# GLASS
+#----------------------------------------------------------------
+ layer GLASS glass
+ calma 76 20
+
+#----------------------------------------------------------------
+# CAPM
+#----------------------------------------------------------------
+ layer CAPM *mimcap
+ labels mimcap
+ calma 89 44
+
+ layer CAPM2 *mimcap2
+ labels mimcap2
+ calma 97 44
+
+#----------------------------------------------------------------
+# Chip top level marker for DRC latchup rules to check 15um
+# distance to taps (otherwise 6um is used)
+#----------------------------------------------------------------
+
+ layer LOWTAPDENSITY
+ bbox top
+ # Clear 200um for pads + 50um for required high tap density
+ # in critical area.
+ shrink 250000
+ calma 81 14
+
+#----------------------------------------------------------------
+# FILLBLOCK
+#----------------------------------------------------------------
+ layer FILLOBSM1 fillblock
+ calma 62 24
+
+ layer FILLOBSM2 fillblock
+ calma 105 52
+
+ layer FILLOBSM3 fillblock
+ calma 107 24
+
+ layer FILLOBSM4 fillblock
+ calma 112 4
+
+ render DNWELL cwell -0.1 0.1
+ render NWELL nwell 0.0 0.2062
+ render DIFF ndiffusion 0.2062 0.12
+ render TAP pdiffusion 0.2062 0.12
+ render POLY polysilicon 0.3262 0.18
+ render CONT via 0.5062 0.43
+ render LI metal1 0.9361 0.10
+ render MCON via 1.0361 0.34
+ render MET1 metal2 1.3761 0.36
+ render VIA1 via 1.7361 0.27
+ render MET2 metal3 2.0061 0.36
+ render VIA2 via 2.3661 0.42
+ render MET3 metal4 2.7861 0.845
+ render VIA3 via 3.6311 0.39
+ render MET4 metal5 4.0211 0.845
+ render VIA4 via 4.8661 0.505
+ render MET5 metal6 5.3711 1.26
+ render CAPM metal8 2.4661 0.2
+ render CAPM2 metal9 3.7311 0.2
+ render RDL metal7 11.8834 4.0
+
+#----------------------------------------------------------------
+style drc
+#----------------------------------------------------------------
+# NOTE: This style is used for DRC only, not for GDS output
+#----------------------------------------------------------------
+ scalefactor 10 nanometers
+ options calma-permissive-labels
+
+ # Ensure nwell overlaps dnwell at least 0.4um outside and 1.03um inside
+ templayer dnwell_shrink dnwell
+ shrink 1030
+
+ templayer nwell_missing dnwell
+ grow 400
+ and-not dnwell_shrink
+ and-not nwell
+
+ templayer pwell_in_dnwell dnwell
+ and-not nwell
+
+ # SONOS nFET devices must be in deep nwell
+ templayer dnwell_missing nsonos
+ and-not dnwell
+
+ # SONOS nFET devices must be in cell with abutment box
+ templayer abutment_box
+ boundary
+
+ templayer bbox_missing nsonos
+ and-not abutment_box
+
+ # Make sure nwell covers varactor poly
+ templayer var_poly_no_nwell
+ bloat-all varactor,mvvaractor *poly
+ grow 150
+ and-not nwell
+
+ # Define MiM cap bottom plate for spacing rule
+ templayer mim_bottom
+ bloat-all *mimcap *metal3
+
+ # Define MiM2 cap bottom plate for spacing rule
+ templayer mim2_bottom
+ bloat-all *mimcap2 *metal4
+
+ # Note that metal fill is performed by the foundry and so is not
+ # an option for a cifoutput style.
+
+ # Check latchup rule (15um minimum from tap LICON center to any
+ # non-tap diffusion. Note that to count as a tap, the diffusion
+ # must be contacted to LI
+
+ templayer ptap_reach psc,mvpsc
+ and-not dnwell
+ # grow total is 15um. grow in 0.84um increments to ensure that
+ # no nwell ring is crossed
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 635
+ and-not nwell,dnwell
+
+ templayer ptap_missing *ndiff,*mvndiff
+ and-not dnwell
+ and-not ptap_reach
+
+ templayer ntap_reach nsc,mvnsc
+ # grow total is 15um. grow in 1.27um increments to ensure that
+ # no nwell ring is crossed. There is no difference between
+ # ntaps in and out of deep nwell.
+ grow 1270
+ and nwell,pnp
+ grow 1270
+ and nwell,pnp
+ grow 1270
+ and nwell,pnp
+ grow 1270
+ and nwell,pnp
+ grow 1270
+ and nwell,pnp
+ grow 1270
+ and nwell,pnp
+ grow 1270
+ and nwell,pnp
+ grow 1270
+ and nwell,pnp
+ grow 1270
+ and nwell,pnp
+ grow 1270
+ and nwell,pnp
+ grow 1270
+ and nwell,pnp
+ grow 945
+ and nwell,pnp
+
+ templayer ntap_missing *pdiff,*mvpdiff
+ and-not pwell_in_dnwell
+ and-not ntap_reach
+
+ templayer dptap_reach psc,mvpsc
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 635
+ and-not nwell
+ and dnwell
+
+ templayer dptap_missing *ndiff,*mvndiff
+ and dnwell
+ and-not dptap_reach
+
+ templayer pdiff_crosses_dnwell dnwell
+ grow 20
+ and-not dnwell
+ and allpdifflv,allpdiffmv
+
+ # MV nwell must be 2um from any other nwell
+ templayer mvnwell
+ bloat-all alldiffmv nwell
+ grow-min 840
+ bridge 700 600
+
+ # Simple spacing checks to lvnwell must use CIF-DRC rule
+ templayer allmvdiffnowell *mvndiff,*mvpsd
+
+ templayer lvnwell nwell
+ and-not mvnwell
+
+ templayer nwell_with_tap
+ bloat-all nsc,mvnsc nwell,pnp
+
+ templayer nwell_missing_tap nwell,pnp
+ and-not nwell_with_tap
+
+ templayer tap_with_licon
+ bloat-all psc,mvpsc psd,mvpsd
+ bloat-all nsc,mvnsc nsd,mvnsd
+
+ templayer tap_missing_licon psd,nsd,mvpsd,mvnsd
+ and-not tap_with_licon
+
+ # Make sure varactor nwell contains no P diffusion
+ templayer pdiff_in_varactor_well
+ bloat-all varactor,mvvaractor nwell
+ and allpactive
+
+ # HVNTM spacing requires recreating HVNTM
+ templayer hvntm_block *mvpsd
+ grow 185
+
+ templayer hvntm_generate
+ bloat-all mvnfet,mvnnfet,*mvndiode,mvrdn,*nndiode *mvndiff
+ bloat-all mvvaractor *mvnsd
+ and-not hvntm_block
+ grow 185
+ grow 345
+ shrink 345
+ and-not hvntm_block
+
+ templayer m1_small_hole allm1,obsm1,obslic
+ close 140000
+
+ templayer m1_hole_empty m1_small_hole
+ and-not allm1,obsm1,obslic
+
+ templayer m2_small_hole allm2,obsm2
+ close 140000
+
+ templayer m2_hole_empty m2_small_hole
+ and-not allm2,obsm2
+
+ templayer m1_huge allm1
+ shrink 1500
+ grow 1500
+
+ templayer m1_large_halo m1_huge
+ grow 280
+ and-not m1_huge
+ and allm1
+
+ templayer m2_huge allm2
+ shrink 1500
+ grow 1500
+
+ templayer m2_large_halo m2_huge
+ grow 280
+ and-not m2_huge
+ and allm2
+
+ templayer m3_huge allm3
+ shrink 1500
+ grow 1500
+
+ templayer m3_large_halo m3_huge
+ grow 400
+ and-not m3_huge
+ and allm3
+
+ templayer m4_huge allm4
+ shrink 1500
+ grow 1500
+
+ templayer m4_large_halo m4_huge
+ grow 400
+ and-not m4_huge
+ and allm4
+
+
+#----------------------------------------------------------------
+style wafflefill
+#----------------------------------------------------------------
+# Style used by scripts for automatically generating fill layers
+# NOTE: Be sure to generate output on flattened layout.
+#----------------------------------------------------------------
+ scalefactor 10 nanometers
+ options calma-permissive-labels
+ gridlimit 5
+
+#----------------------------------------------------------------
+# Generate and retain a layer representing the bounding box
+#----------------------------------------------------------------
+ templayer topbox
+ bbox top
+
+#----------------------------------------------------------------
+# Generate guard-band around nwells to keep FOM from crossing
+# Spacing from LV nwell = Diff/Tap 9 = 0.34um
+# Spacing from HV nwell = Diff/Tap 18 = 0.43um (= 0.18 + 0.25)
+# Enclosure by nwell = Diff/Tap 8 = 0.18um
+#----------------------------------------------------------------
+
+ templayer mvnwell
+ bloat-all alldiffmv nwell
+
+ templayer lvnwell nwell
+ and-not mvnwell
+
+ templayer well_shrink mvnwell
+ shrink 250
+ or lvnwell
+ shrink 180
+ templayer well_guardband nwell
+ grow 340
+ and-not well_shrink
+
+#---------------------------------------------------
+# Diffusion and poly keep-out areas
+#---------------------------------------------------
+ templayer obstruct_fom alldiff,allpoly,rpw
+ grow 500
+ or well_guardband
+
+ templayer obstruct_poly alldiff,allpoly,rpw
+ grow 1000
+
+#---------------------------------------------------
+# FOM and POLY fill
+#---------------------------------------------------
+ templayer fomfill_pass1 topbox
+ slots 0 4080 1320 0 4080 1320 1360 0
+ and-not obstruct_fom
+ and topbox
+ shrink 2035
+ grow 2035
+
+#---------------------------------------------------
+
+ templayer obstruct_poly_pass1 fomfill_pass1
+ grow 300
+ or obstruct_poly
+ templayer polyfill_pass1 topbox
+ slots 0 720 360 0 720 360 240 0
+ and-not obstruct_poly_pass1
+ and topbox
+ shrink 355
+ grow 355
+
+#---------------------------------------------------
+
+ templayer obstruct_fom_pass2 fomfill_pass1
+ grow 1290
+ or polyfill_pass1
+ grow 300
+ or obstruct_fom
+ templayer fomfill_pass2 topbox
+ slots 0 2500 1320 0 2500 1320 1360 0
+ and-not obstruct_fom_pass2
+ and topbox
+ shrink 1245
+ grow 1245
+
+#---------------------------------------------------
+
+ templayer obstruct_poly_coarse polyfill_pass1
+ grow 60
+ or fomfill_pass1,fomfill_pass2
+ grow 300
+ or obstruct_poly
+ templayer polyfill_coarse topbox
+ slots 0 720 360 0 720 360 240 120
+ and-not obstruct_poly_coarse
+ and topbox
+ shrink 355
+ grow 355
+
+#---------------------------------------------------
+ templayer obstruct_poly_medium polyfill_pass1,polyfill_coarse
+ grow 60
+ or fomfill_pass1,fomfill_pass2
+ grow 300
+ or obstruct_poly
+ templayer polyfill_medium topbox
+ slots 0 540 360 0 540 360 240 100
+ and-not obstruct_poly_medium
+ and topbox
+ shrink 265
+ grow 265
+
+#---------------------------------------------------
+ templayer obstruct_poly_fine polyfill_pass1,polyfill_coarse,polyfill_medium
+ grow 60
+ or fomfill_pass1,fomfill_pass2
+ grow 300
+ or obstruct_poly
+ templayer polyfill_fine topbox
+ slots 0 480 360 0 480 360 240 200
+ and-not obstruct_poly_fine
+ and topbox
+ shrink 235
+ grow 235
+
+#---------------------------------------------------
+
+ templayer obstruct_fom_coarse fomfill_pass1,fomfill_pass2
+ grow 1290
+ or polyfill_pass1,polyfill_coarse,polyfill_medium,polyfill_fine
+ grow 300
+ or obstruct_fom
+ templayer fomfill_coarse topbox
+ slots 0 1500 1320 0 1500 1320 1360 0
+ and-not obstruct_fom_coarse
+ and topbox
+ shrink 745
+ grow 745
+
+#---------------------------------------------------
+
+ templayer obstruct_fom_fine fomfill_pass1,fomfill_pass2,fomfill_coarse
+ grow 1290
+ or polyfill_pass1,polyfill_coarse,polyfill_medium,polyfill_fine
+ grow 300
+ or obstruct_fom
+ templayer fomfill_fine topbox
+ slots 0 500 400 0 500 400 160 0
+ and-not obstruct_fom_fine
+ and topbox
+ shrink 245
+ grow 245
+
+#---------------------------------------------------
+ templayer fomfill
+ or fomfill_pass1
+ or fomfill_pass2
+ or fomfill_coarse
+ or fomfill_fine
+
+ templayer polyfill
+ or polyfill_pass1
+ or polyfill_coarse
+ or polyfill_medium
+ or polyfill_fine
+
+ layer FOMMASK fomfill
+ calma 23 0
+ layer POLYMASK polyfill
+ calma 28 0
+
+#---------------------------------------------------
+# MET1 fill
+#---------------------------------------------------
+
+ templayer obstruct_m1_coarse allm1,allpad,obsm1,m1fill,fillblock
+ grow 3000
+ templayer met1fill_coarse topbox
+ slots 0 2000 200 0 2000 200 700 0
+ and-not obstruct_m1_coarse
+ and topbox
+ shrink 995
+ grow 995
+
+ templayer obstruct_m1_medium allm1,allpad,obsm1,m1fill,fillblock
+ grow 2800
+ or met1fill_coarse
+ grow 200
+ templayer met1fill_medium topbox
+ slots 0 1000 200 0 1000 200 700 0
+ and-not obstruct_m1_medium
+ and topbox
+ shrink 495
+ grow 495
+
+ templayer obstruct_m1_fine allm1,allpad,obsm1,m1fill,fillblock
+ grow 300
+ or met1fill_coarse,met1fill_medium
+ grow 200
+ templayer met1fill_fine topbox
+ slots 0 580 200 0 580 200 700 0
+ and-not obstruct_m1_fine
+ and topbox
+ shrink 285
+ grow 285
+
+ templayer obstruct_m1_veryfine allm1,allpad,obsm1,m1fill,fillblock
+ grow 100
+ or met1fill_coarse,met1fill_medium,met1fill_fine
+ grow 200
+ templayer met1fill_veryfine topbox
+ slots 0 300 200 0 300 200 100 50
+ and-not obstruct_m1_veryfine
+ and topbox
+ shrink 145
+ grow 145
+
+ layer MET1MASK met1fill_coarse
+ or met1fill_medium
+ or met1fill_fine
+ or met1fill_veryfine
+ calma 36 0
+
+#---------------------------------------------------
+# MET2 fill
+#---------------------------------------------------
+ templayer obstruct_m2 allm2,allpad,obsm2,m2fill,fillblock
+ grow 3000
+ templayer met2fill_coarse topbox
+ slots 0 2000 200 0 2000 200 700 350
+ and-not obstruct_m2
+ and topbox
+ shrink 995
+ grow 995
+
+ templayer obstruct_m2_medium allm2,allpad,obsm2,m2fill,fillblock
+ grow 2800
+ or met2fill_coarse
+ grow 200
+ templayer met2fill_medium topbox
+ slots 0 1000 200 0 1000 200 700 350
+ and-not obstruct_m2_medium
+ and topbox
+ shrink 495
+ grow 495
+
+ templayer obstruct_m2_fine allm2,allpad,obsm2,m2fill,fillblock
+ grow 300
+ or met2fill_coarse,met2fill_medium
+ grow 200
+ templayer met2fill_fine topbox
+ slots 0 580 200 0 580 200 700 350
+ and-not obstruct_m2_fine
+ and topbox
+ shrink 285
+ grow 285
+
+ templayer obstruct_m2_veryfine allm2,allpad,obsm2,m2fill,fillblock
+ grow 100
+ or met2fill_coarse,met2fill_medium,met2fill_fine
+ grow 200
+ templayer met2fill_veryfine topbox
+ slots 0 300 200 0 300 200 100 100
+ and-not obstruct_m2_veryfine
+ and topbox
+ shrink 145
+ grow 145
+
+ layer MET2MASK met2fill_coarse
+ or met2fill_medium
+ or met2fill_fine
+ or met2fill_veryfine
+ calma 41 0
+
+#---------------------------------------------------
+# MET3 fill
+#---------------------------------------------------
+ templayer obstruct_m3 allm3,allpad,obsm3,m3fill,fillblock
+ grow 3000
+ templayer met3fill_coarse topbox
+ slots 0 2000 300 0 2000 300 700 700
+ and-not obstruct_m3
+ and topbox
+ shrink 995
+ grow 995
+
+ templayer obstruct_m3_medium allm3,allpad,obsm3,m3fill,fillblock
+ grow 2700
+ or met3fill_coarse
+ grow 300
+ templayer met3fill_medium topbox
+ slots 0 1000 300 0 1000 300 700 700
+ and-not obstruct_m3_medium
+ and topbox
+ shrink 495
+ grow 495
+
+ templayer obstruct_m3_fine allm3,allpad,obsm3,m3fill,fillblock
+ grow 200
+ or met3fill_coarse,met3fill_medium
+ grow 300
+ templayer met3fill_fine topbox
+ slots 0 580 300 0 580 300 700 700
+ and-not obstruct_m3_fine
+ and topbox
+ shrink 285
+ grow 285
+
+ templayer obstruct_m3_veryfine allm3,allpad,obsm3,m3fill,fillblock
+ # Note: Adding 0.1 to waffle rule to clear wide spacing rule
+ grow 100
+ or met3fill_coarse,met3fill_medium,met3fill_fine
+ grow 300
+ templayer met3fill_veryfine topbox
+ slots 0 400 300 0 400 300 150 200
+ and-not obstruct_m3_veryfine
+ and topbox
+ shrink 195
+ grow 195
+
+ layer MET3MASK met3fill_coarse
+ or met3fill_medium
+ or met3fill_fine
+ or met3fill_veryfine
+ calma 34 0
+
+#---------------------------------------------------
+# MET4 fill
+#---------------------------------------------------
+ templayer obstruct_m4 allm4,allpad,obsm4,m4fill,fillblock
+ grow 3000
+ templayer met4fill_coarse topbox
+ slots 0 2000 300 0 2000 300 700 1050
+ and-not obstruct_m4
+ and topbox
+ shrink 995
+ grow 995
+
+ templayer obstruct_m4_medium allm4,allpad,obsm4,m4fill,fillblock
+ grow 2700
+ or met4fill_coarse
+ grow 300
+ templayer met4fill_medium topbox
+ slots 0 1000 300 0 1000 300 700 1050
+ and-not obstruct_m4_medium
+ shrink 495
+ grow 495
+
+ templayer obstruct_m4_fine allm4,allpad,obsm4,m4fill,fillblock
+ grow 200
+ or met4fill_coarse,met4fill_medium
+ grow 300
+ templayer met4fill_fine topbox
+ slots 0 580 300 0 580 300 700 1050
+ and-not obstruct_m4_fine
+ and topbox
+ shrink 285
+ grow 285
+
+ templayer obstruct_m4_veryfine allm4,allpad,obsm4,m4fill,fillblock
+ # Note: Adding 0.1 to waffle rule to clear wide spacing rule
+ grow 100
+ or met4fill_coarse,met4fill_medium,met4fill_fine
+ grow 300
+ templayer met4fill_veryfine topbox
+ slots 0 400 300 0 400 300 150 300
+ and-not obstruct_m4_veryfine
+ and topbox
+ shrink 195
+ grow 195
+
+ layer MET4MASK met4fill_coarse
+ or met4fill_medium
+ or met4fill_fine
+ or met4fill_veryfine
+ calma 51 0
+
+#---------------------------------------------------
+# MET5 fill
+#---------------------------------------------------
+ templayer obstruct_m5 allm5,allpad,obsm5,m5fill,fillblock
+ grow 3000
+ templayer met5fill_gen topbox
+ slots 0 3000 1600 0 3000 1600 1000 100
+ and-not obstruct_m5
+ and topbox
+ shrink 1495
+ grow 1495
+
+ layer MET5MASK met5fill_gen
+ calma 59 0
+
+end
+
+#-----------------------------------------------------------------------
+cifinput
+#-----------------------------------------------------------------------
+# NOTE: All values in this section MUST be multiples of 25
+# or else magic will scale below the allowed layout grid size
+#-----------------------------------------------------------------------
+
+style sky130
+ scalefactor 10 nanometers
+ gridlimit 5
+
+ options ignore-unknown-layer-labels no-reconnect-labels
+
+ ignore NPC
+ ignore SEALID
+ ignore CAPID
+ ignore LDNTM
+ ignore HVNTM
+ ignore POLYMOD
+ ignore LOWTAPDENSITY
+
+ layer pnp NWELL,WELLTXT,WELLPIN
+ and PNPID
+ labels NWELL
+ labels WELLTXT text
+ labels WELLPIN port
+
+ layer nwell NWELL,WELLTXT,WELLPIN
+ and-not PNPID
+ labels NWELL
+ labels WELLTXT text
+ labels WELLPIN port
+
+ layer pwell SUBTXT,SUBPIN
+ labels SUBTXT text
+ labels SUBPIN port
+
+ # Always draw pwell under p-tap
+ layer pwell TAP
+ and-not NWELL
+
+ layer dnwell DNWELL
+ labels DNWELL
+
+ layer npn DNWELL
+ and-not NWELL
+ and NPNID
+
+ layer rpw PWRES
+ and DNWELL
+ labels PWRES
+
+ templayer ndiffarea DIFF,DIFFTXT,DIFFPIN
+ and-not POLY
+ and-not NWELL
+ and-not PPLUS
+ and-not DIODE
+ and-not DIFFRES
+ and-not THKOX
+ and NPLUS
+ copyup ndifcheck
+ labels DIFF
+ labels DIFFTXT text
+ labels DIFFPIN port
+ labels TAPPIN port
+
+ layer ndiff ndiffarea
+
+ # Copy ndiff areas up for contact checks
+ templayer xndifcheck ndifcheck
+ copyup ndifcheck
+
+ templayer mvndiffarea DIFF,DIFFTXT,DIFFPIN
+ and-not POLY
+ and-not NWELL
+ and-not PPLUS
+ and-not DIODE
+ and-not DIFFRES
+ and THKOX
+ and NPLUS
+ copyup ndifcheck
+ labels DIFF
+ labels DIFFTXT text
+ labels DIFFPIN port
+
+ layer mvndiff mvndiffarea
+
+ # Copy ndiff areas up for contact checks
+ templayer mvxndifcheck mvndifcheck
+ copyup mvndifcheck
+
+ layer ndiode DIFF
+ and NPLUS
+ and DIODE
+ and-not NWELL
+ and-not POLY
+ and-not PPLUS
+ and-not THKOX
+ and-not LVTN
+ labels DIFF
+
+ layer ndiodelvt DIFF
+ and NPLUS
+ and DIODE
+ and-not NWELL
+ and-not POLY
+ and-not PPLUS
+ and-not THKOX
+ and LVTN
+ labels DIFF
+
+ templayer ndiodearea DIODE
+ and NPLUS
+ and-not THKOX
+ and-not NWELL
+ copyup DIODE,NPLUS
+
+ layer ndiffres DIFFRES
+ and NPLUS
+ and-not THKOX
+ labels DIFF
+
+ templayer pdiffarea DIFF,DIFFTXT,DIFFPIN
+ and-not POLY
+ and NWELL
+ and-not NPLUS
+ and-not DIODE
+ and-not THKOX
+ and PPLUS
+ copyup pdifcheck
+ labels DIFF
+ labels DIFFTXT text
+ labels DIFFPIN port
+
+ layer pdiff pdiffarea
+
+ layer mvndiode DIFF
+ and NPLUS
+ and DIODE
+ and THKOX
+ and-not POLY
+ and-not PPLUS
+ and-not LVTN
+ labels DIFF
+
+ layer nndiode DIFF
+ and NPLUS
+ and DIODE
+ and THKOX
+ and-not POLY
+ and-not PPLUS
+ and LVTN
+ labels DIFF
+
+ templayer mvndiodearea DIODE
+ and NPLUS
+ and THKOX
+ and-not NWELL
+ copyup DIODE,NPLUS
+
+ layer mvndiffres DIFFRES
+ and NPLUS
+ and THKOX
+ labels DIFF
+
+ templayer mvpdiffarea DIFF,DIFFTXT,DIFFPIN
+ and-not POLY
+ and NWELL
+ and-not NPLUS
+ and THKOX
+ and-not DIODE
+ and-not DIFFRES
+ and PPLUS
+ copyup mvpdifcheck
+ labels DIFF
+ labels DIFFTXT text
+ labels DIFFPIN port
+
+ layer mvpdiff mvpdiffarea
+
+ # Copy pdiff areas up for contact checks
+ templayer xpdifcheck pdifcheck
+ copyup pdifcheck
+
+ layer pdiode DIFF
+ and PPLUS
+ and-not POLY
+ and-not NPLUS
+ and-not THKOX
+ and-not LVTN
+ and-not HVTP
+ and DIODE
+ labels DIFF
+
+ layer pdiodelvt DIFF
+ and PPLUS
+ and-not POLY
+ and-not NPLUS
+ and-not THKOX
+ and LVTN
+ and-not HVTP
+ and DIODE
+ labels DIFF
+
+ layer pdiodehvt DIFF
+ and PPLUS
+ and-not POLY
+ and-not NPLUS
+ and-not THKOX
+ and-not LVTN
+ and HVTP
+ and DIODE
+ labels DIFF
+
+ templayer pdiodearea DIODE
+ and PPLUS
+ and-not THKOX
+ copyup DIODE,PPLUS
+
+ # Define pfet areas as known pdiff, regardless of the presence of a well.
+
+ templayer pfetarea DIFF
+ and-not NPLUS
+ and-not THKOX
+ and POLY
+
+ layer pfet pfetarea
+ and-not LVTN
+ and-not HVTP
+ and-not STDCELL
+ and-not COREID
+ labels DIFF
+
+ layer scpfet pfetarea
+ and-not LVTN
+ and-not HVTP
+ and STDCELL
+ labels DIFF
+
+ layer scpfethvt pfetarea
+ and-not LVTN
+ and HVTP
+ and STDCELL
+ labels DIFF
+
+ layer ppu pfetarea
+ and-not LVTN
+ and HVTP
+ and COREID
+ labels DIFF
+
+ layer pfetlvt pfetarea
+ and LVTN
+ labels DIFF
+
+ layer pfetmvt pfetarea
+ and HVTR
+ labels DIFF
+
+ layer pfethvt pfetarea
+ and HVTP
+ and-not STDCELL
+ and-not COREID
+ labels DIFF
+
+ # Always force nwell under pfet (nwell encloses pdiff by 0.18)
+ layer nwell pfetarea
+ grow 180
+
+ # Copy mvpdiff areas up for contact checks
+ templayer mvxpdifcheck mvpdifcheck
+ copyup mvpdifcheck
+
+ layer mvpdiode DIFF
+ and PPLUS
+ and-not POLY
+ and-not NPLUS
+ and THKOX
+ and DIODE
+ labels DIFF
+
+ templayer mvpdiodearea DIODE
+ and PPLUS
+ and THKOX
+ copyup DIODE,PPLUS
+
+ # Define pfet areas as known pdiff,
+ # regardless of the presence of a
+ # well.
+
+ templayer mvpfetarea DIFF
+ and-not NPLUS
+ and THKOX
+ and POLY
+
+ layer mvpfet mvpfetarea
+ labels DIFF
+
+ layer pdiff DIFF,DIFFTXT,DIFFPIN
+ and-not NPLUS
+ and-not POLY
+ and-not THKOX
+ and-not DIODE
+ and-not DIFFRES
+ labels DIFF
+ labels DIFFTXT text
+ labels DIFFPIN port
+
+ layer pdiffres DIFFRES
+ and PPLUS
+ and NWELL
+ and-not THKOX
+ labels DIFF
+
+ layer nfet DIFF
+ and POLY
+ and-not PPLUS
+ and NPLUS
+ and-not THKOX
+ and-not LVTN
+ and-not SONOS
+ and-not STDCELL
+ labels DIFF
+
+ layer scnfet DIFF
+ and POLY
+ and-not PPLUS
+ and NPLUS
+ and-not NWELL
+ and-not THKOX
+ and-not LVTN
+ and-not SONOS
+ and STDCELL
+ labels DIFF
+
+ layer npass DIFF
+ and POLY
+ and-not PPLUS
+ and NPLUS
+ and-not NWELL
+ and COREID
+ labels DIFF
+
+ layer npd DIFF
+ and POLY
+ and-not PPLUS
+ and NPLUS
+ and-not NWELL
+ and COREID
+ # Shrink-grow operation eliminates the smaller npass device
+ shrink 70
+ grow 70
+ labels DIFF
+
+ layer nfetlvt DIFF
+ and POLY
+ and-not PPLUS
+ and NPLUS
+ and-not THKOX
+ and LVTN
+ and-not SONOS
+ labels DIFF
+
+ layer nsonos DIFF
+ and POLY
+ and-not PPLUS
+ and NPLUS
+ and-not THKOX
+ and LVTN
+ and SONOS
+ labels DIFF
+
+ templayer nsdarea TAP
+ and NPLUS
+ and NWELL
+ and-not POLY
+ and-not PPLUS
+ and-not THKOX
+ copyup nsubcheck
+
+ layer nsd nsdarea
+ labels TAP
+
+ layer nsd TAP,TAPPIN
+ and NPLUS
+ and-not POLY
+ and-not THKOX
+ labels TAP
+ labels TAPPIN port
+
+ layer corenvar TAP
+ and NPLUS
+ and POLY
+ and COREID
+ labels TAP
+
+ templayer nsdexpand nsdarea
+ grow 500
+
+ # Copy nsub areas up for contact checks
+ templayer xnsubcheck nsubcheck
+ copyup nsubcheck
+
+ templayer psdarea TAP
+ and PPLUS
+ and-not NWELL
+ and-not POLY
+ and-not NPLUS
+ and-not THKOX
+ and-not pfetexpand
+ copyup psubcheck
+
+ layer psd psdarea
+ labels TAP
+
+ layer psd TAP,TAPPIN
+ and PPLUS
+ and-not POLY
+ and-not THKOX
+ labels TAP
+ labels TAPPIN port
+
+ layer corepvar TAP
+ and PPLUS
+ and POLY
+ and COREID
+ labels TAP
+
+ templayer psdexpand psdarea
+ grow 500
+
+ layer mvpdiff DIFF,DIFFTXT,DIFFPIN
+ and-not NPLUS
+ and-not POLY
+ and THKOX
+ and mvpfetexpand
+ labels DIFF
+ labels DIFFTXT text
+ labels DIFFPIN port
+
+ layer mvpdiffres DIFFRES
+ and PPLUS
+ and NWELL
+ and THKOX
+ and-not mvrdpioedge
+ labels DIFF
+
+ templayer mvnfetarea DIFF
+ and POLY
+ and-not PPLUS
+ and NPLUS
+ and-not LVTN
+ and THKOX
+ grow 1000
+
+ templayer mvnnfetarea DIFF,TAP
+ and POLY
+ and-not PPLUS
+ and NPLUS
+ and LVTN
+ and THKOX
+ and-not mvnfetarea
+
+ layer mvnfet DIFF
+ and POLY
+ and-not PPLUS
+ and NPLUS
+ and THKOX
+ and-not mvnnfetarea
+ labels DIFF
+
+ layer mvnnfet mvnnfetarea
+ labels DIFF
+
+ templayer mvnsdarea TAP
+ and NPLUS
+ and NWELL
+ and-not POLY
+ and-not PPLUS
+ and THKOX
+ copyup mvnsubcheck
+
+ layer mvnsd mvnsdarea
+ labels TAP
+
+ layer mvnsd TAP,TAPPIN
+ and NPLUS
+ and THKOX
+ labels TAP
+ labels TAPPIN port
+
+ templayer mvnsdexpand mvnsdarea
+ grow 500
+
+ # Copy nsub areas up for contact checks
+ templayer mvxnsubcheck mvnsubcheck
+ copyup mvnsubcheck
+
+ templayer mvpsdarea DIFF
+ and PPLUS
+ and-not NWELL
+ and-not POLY
+ and-not NPLUS
+ and THKOX
+ and-not mvpfetexpand
+ copyup mvpsubcheck
+
+ layer mvpsd mvpsdarea
+ labels DIFF
+
+ layer mvpsd TAP,TAPPIN
+ and PPLUS
+ and THKOX
+ labels TAP
+ labels TAPPIN port
+
+ templayer mvpsdexpand mvpsdarea
+ grow 500
+
+ # Copy psub areas up for contact checks
+ templayer xpsubcheck psubcheck
+ copyup psubcheck
+
+ templayer mvxpsubcheck mvpsubcheck
+ copyup mvpsubcheck
+
+ layer psd TAP
+ and-not PPLUS
+ and-not NPLUS
+ and-not POLY
+ and-not THKOX
+ and-not pfetexpand
+ and psdexpand
+
+ layer nsd TAP
+ and-not PPLUS
+ and-not NPLUS
+ and-not POLY
+ and-not THKOX
+ and nsdexpand
+
+ layer mvpsd TAP
+ and-not PPLUS
+ and-not NPLUS
+ and-not POLY
+ and THKOX
+ and-not mvpfetexpand
+ and mvpsdexpand
+
+ layer mvnsd TAP
+ and-not PPLUS
+ and-not NPLUS
+ and-not POLY
+ and THKOX
+ and mvnsdexpand
+
+ templayer hresarea POLY
+ and RPM
+ grow 3000
+
+ templayer uresarea POLY
+ and URPM
+ grow 3000
+
+ templayer diffresarea DIFFRES
+ and-not THKOX
+ grow 3000
+
+ templayer mvdiffresarea DIFFRES
+ and THKOX
+ grow 3000
+
+ templayer resarea diffresarea,mvdiffresarea,hresarea,uresarea
+
+ layer pfet POLY
+ and DIFF
+ and diffresarea
+ and-not NPLUS
+ and-not STDCELL
+
+ layer scpfet POLY
+ and DIFF
+ and diffresarea
+ and-not HVTP
+ and-not NPLUS
+ and STDCELL
+
+ layer scpfethvt POLY
+ and DIFF
+ and diffresarea
+ and HVTP
+ and-not NPLUS
+ and STDCELL
+
+ templayer xpolyterm RPM,URPM
+ and POLY
+ and-not POLYRES
+ # add back the 0.06um contact surround in the direction of the resistor
+ grow 60
+ and POLY
+
+ layer xpc xpolyterm
+
+ templayer polyarea POLY
+ and-not POLYRES
+ and-not POLYSHORT
+ and-not DIFF
+ and-not TAP
+ and-not RPM
+ and-not URPM
+ copyup polycheck
+
+ layer poly polyarea,POLYTXT,POLYPIN
+ labels POLY
+ labels POLYTXT text
+ labels POLYPIN port
+
+ # Copy (non-resistor) poly areas up for contact checks
+ templayer xpolycheck polycheck
+ copyup polycheck
+
+ layer mrp1 POLY
+ and POLYRES
+ and-not RPM
+ and-not URPM
+ labels POLY
+
+ layer rmp POLY
+ and POLYSHORT
+ labels POLY
+
+ layer xhrpoly POLY
+ and POLYRES
+ and RPM
+ and-not URPM
+ and PPLUS
+ and NPC
+ and-not xpolyterm
+ labels POLY
+
+ layer uhrpoly POLY
+ and POLYRES
+ and URPM
+ and-not RPM
+ and NPC
+ and-not xpolyterm
+ labels POLY
+
+ templayer ndcbase CONT
+ and DIFF
+ and NPLUS
+ and-not NWELL
+ and LI
+ and-not THKOX
+
+ layer ndc ndcbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or ndcbase
+ labels CONT
+
+ templayer nscbase CONT
+ and DIFF,TAP
+ and NPLUS
+ and NWELL
+ and LI
+ and-not THKOX
+
+ layer nsc nscbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or nscbase
+ labels CONT
+
+ templayer pdcbase CONT
+ and DIFF
+ and PPLUS
+ and NWELL
+ and LI
+ and-not THKOX
+
+ layer pdc pdcbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pdcbase
+ labels CONT
+
+ templayer pdcnowell CONT
+ and DIFF
+ and PPLUS
+ and pfetexpand
+ and LI
+ and-not THKOX
+
+ layer pdc pdcnowell
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pdcnowell
+ labels CONT
+
+ templayer pscbase CONT
+ and DIFF,TAP
+ and PPLUS
+ and-not NWELL
+ and-not pfetexpand
+ and LI
+ and-not THKOX
+
+ layer psc pscbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pscbase
+ labels CONT
+
+ templayer pcbase CONT
+ and POLY
+ and-not DIFF
+ and-not RPM,URPM
+ and LI
+
+ layer pc pcbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pcbase
+ labels CONT
+
+ templayer ndicbase CONT
+ and DIFF
+ and NPLUS
+ and DIODE
+ and-not POLY
+ and-not PPLUS
+ and-not THKOX
+ and-not LVTN
+
+ layer ndic ndicbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or ndicbase
+ labels CONT
+
+ templayer ndilvtcbase CONT
+ and DIFF
+ and NPLUS
+ and DIODE
+ and-not POLY
+ and-not PPLUS
+ and-not THKOX
+ and LVTN
+
+ layer ndilvtc ndilvtcbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or ndilvtcbase
+ labels CONT
+
+ templayer pdicbase CONT
+ and DIFF
+ and PPLUS
+ and DIODE
+ and-not POLY
+ and-not NPLUS
+ and-not THKOX
+ and-not LVTN
+ and-not HVTP
+
+ layer pdic pdicbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pdicbase
+ labels CONT
+
+ templayer pdilvtcbase CONT
+ and DIFF
+ and PPLUS
+ and DIODE
+ and-not POLY
+ and-not NPLUS
+ and-not THKOX
+ and LVTN
+ and-not HVTP
+
+ layer pdilvtc pdilvtcbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pdilvtcbase
+ labels CONT
+
+ templayer pdihvtcbase CONT
+ and DIFF
+ and PPLUS
+ and DIODE
+ and-not POLY
+ and-not NPLUS
+ and-not THKOX
+ and-not LVTN
+ and HVTP
+
+ layer pdihvtc pdihvtcbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pdihvtcbase
+ labels CONT
+
+ templayer mvndcbase CONT
+ and DIFF
+ and NPLUS
+ and-not NWELL
+ and LI
+ and THKOX
+
+ layer mvndc mvndcbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvndcbase
+ labels CONT
+
+ templayer mvnscbase CONT
+ and DIFF,TAP
+ and NPLUS
+ and NWELL
+ and LI
+ and THKOX
+
+ layer mvnsc mvnscbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvnscbase
+ labels CONT
+
+ templayer mvpdcbase CONT
+ and DIFF
+ and PPLUS
+ and NWELL
+ and LI
+ and THKOX
+
+ layer mvpdc mvpdcbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvpdcbase
+ labels CONT
+
+ templayer mvpdcnowell CONT
+ and DIFF
+ and PPLUS
+ and mvpfetexpand
+ and MET1
+ and THKOX
+
+ layer mvpdc mvpdcnowell
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvpdcnowell
+ labels CONT
+
+ templayer mvpscbase CONT
+ and DIFF,TAP
+ and PPLUS
+ and-not NWELL
+ and-not mvpfetexpand
+ and LI
+ and THKOX
+
+ layer mvpsc mvpscbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvpscbase
+ labels CONT
+
+ templayer mvndicbase CONT
+ and DIFF
+ and NPLUS
+ and DIODE
+ and-not POLY
+ and-not PPLUS
+ and-not LVTN
+ and THKOX
+
+ layer mvndic mvndicbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvndicbase
+ labels CONT
+
+ templayer nndicbase CONT
+ and DIFF
+ and NPLUS
+ and DIODE
+ and-not POLY
+ and-not PPLUS
+ and LVTN
+ and THKOX
+
+ layer nndic nndicbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or nndicbase
+ labels CONT
+
+ templayer mvpdicbase CONT
+ and DIFF
+ and PPLUS
+ and DIODE
+ and-not POLY
+ and-not NPLUS
+ and THKOX
+
+ layer mvpdic mvpdicbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvpdicbase
+ labels CONT
+
+ layer coreli LI,LITXT,LIPIN
+ and-not LIRES,LISHORT
+ and COREID
+ labels LI
+ labels LITXT text
+ labels LIPIN port
+
+ layer locali LI,LITXT,LIPIN
+ and-not LIRES,LISHORT
+ and-not COREID
+ labels LI
+ labels LITXT text
+ labels LIPIN port
+
+ layer rli LI
+ and LIRES,LISHORT
+ labels LIRES,LISHORT
+
+ layer lic MCON
+ grow 95
+ shrink 95
+ shrink 85
+ grow 85
+ or MCON
+ labels MCON
+
+ layer m1 MET1,MET1TXT,MET1PIN
+ and-not MET1RES,MET1SHORT
+ labels MET1
+ labels MET1TXT text
+ labels MET1PIN port
+
+ layer rm1 MET1
+ and MET1RES,MET1SHORT
+ labels MET1RES,MET1SHORT
+
+ layer m1fill MET1FILL
+ labels MET1FILL
+
+ layer mimcap MET3
+ and CAPM
+ labels CAPM
+
+ layer mimcc VIA3
+ and CAPM
+ grow 60
+ grow 40
+ shrink 40
+ labels CAPM
+
+ layer mimcap2 MET4
+ and CAPM2
+ labels CAPM2
+
+ layer mim2cc VIA4
+ and CAPM2
+ grow 190
+ grow 210
+ shrink 210
+ labels CAPM2
+
+
+ templayer m2cbase VIA1
+ grow 55
+
+ layer m2c m2cbase
+ grow 30
+ shrink 30
+ shrink 130
+ grow 130
+ or m2cbase
+
+ layer m2 MET2,MET2TXT,MET2PIN
+ and-not MET2RES,MET2SHORT
+ labels MET2
+ labels MET2TXT text
+ labels MET2PIN port
+
+ layer rm2 MET2
+ and MET2RES,MET2SHORT
+ labels MET2RES,MET2SHORT
+
+ layer m2fill MET2FILL
+ labels MET2FILL
+
+ templayer m3cbase VIA2
+ grow 40
+
+ layer m3c m3cbase
+ grow 60
+ shrink 60
+ shrink 140
+ grow 140
+ or m3cbase
+
+ layer m3 MET3,MET3TXT,MET3PIN
+ and-not MET3RES,MET3SHORT
+ and-not CAPM
+ labels MET3
+ labels MET3TXT text
+ labels MET3PIN port
+
+ layer rm3 MET3
+ and MET3RES,MET3SHORT
+ labels MET3RES,MET3SHORT
+
+ layer m3fill MET3FILL
+ labels MET3FILL
+
+
+ templayer via3base VIA3
+ and-not CAPM
+ grow 60
+
+ layer via3 via3base
+ grow 40
+ shrink 40
+ shrink 160
+ grow 160
+ or via3base
+
+ layer m4 MET4,MET4TXT,MET4PIN
+ and-not MET4RES,MET4SHORT
+ and-not CAPM2
+ labels MET4
+ labels MET4TXT text
+ labels MET4PIN port
+
+ layer rm4 MET4
+ and MET4RES,MET4SHORT
+ labels MET4RES,MET4SHORT
+
+ layer m4fill MET4FILL
+ labels MET4FILL
+
+ layer m5 MET5,MET5TXT,MET5PIN
+ and-not MET5RES,MET5SHORT
+ labels MET5
+ labels MET5TXT text
+ labels MET5PIN port
+
+ layer rm5 MET5
+ and MET5RES,MET5SHORT
+ labels MET5RES,MET5SHORT
+
+ layer m5fill MET5FILL
+ labels MET5FILL
+
+ templayer via4base VIA4
+ and-not CAPM2
+ grow 190
+
+ layer via4 via4base
+ grow 210
+ shrink 210
+ shrink 590
+ grow 590
+ or via4base
+
+ layer metrdl RDL,RDLTXT,RDLPIN
+ labels RDL
+ labels RDLTXT text
+ labels RDLPIN port
+
+ # Find diffusion not covered in
+ # NPLUS or PPLUS and pull it into
+ # the next layer up
+
+ templayer gentrans DIFF
+ and-not PPLUS
+ and-not NPLUS
+ and POLY
+ copyup DIFF,POLY
+
+ templayer gendiff DIFF,TAP
+ and-not PPLUS
+ and-not NPLUS
+ and-not POLY
+ copyup DIFF
+
+ # Handle contacts found by copyup
+
+ templayer ndiccopy CONT
+ and LI
+ and DIODE
+ and NPLUS
+ and-not THKOX
+
+ layer ndic ndiccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or ndiccopy
+ labels CONT
+
+ templayer mvndiccopy CONT
+ and LI
+ and DIODE
+ and NPLUS
+ and THKOX
+
+ layer mvndic mvndiccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvndiccopy
+ labels CONT
+
+ templayer pdiccopy CONT
+ and LI
+ and DIODE
+ and PPLUS
+ and-not THKOX
+
+ layer pdic pdiccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pdiccopy
+ labels CONT
+
+ templayer mvpdiccopy CONT
+ and LI
+ and DIODE
+ and PPLUS
+ and THKOX
+
+ layer mvpdic mvpdiccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvpdiccopy
+ labels CONT
+
+ templayer ndccopy CONT
+ and ndifcheck
+
+ layer ndc ndccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or ndccopy
+ labels CONT
+
+ templayer mvndccopy CONT
+ and mvndifcheck
+
+ layer mvndc mvndccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvndccopy
+ labels CONT
+
+ templayer pdccopy CONT
+ and pdifcheck
+
+ layer pdc pdccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pdccopy
+ labels CONT
+
+ templayer mvpdccopy CONT
+ and mvpdifcheck
+
+ layer mvpdc mvpdccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvpdccopy
+ labels CONT
+
+ templayer pccopy CONT
+ and polycheck
+
+ layer pc pccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pccopy
+ labels CONT
+
+ templayer nsccopy CONT
+ and nsubcheck
+
+ layer nsc nsccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or nsccopy
+ labels CONT
+
+ templayer mvnsccopy CONT
+ and mvnsubcheck
+
+ layer mvnsc mvnsccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvnsccopy
+ labels CONT
+
+ templayer psccopy CONT
+ and psubcheck
+
+ layer psc psccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or psccopy
+ labels CONT
+
+ templayer mvpsccopy CONT
+ and mvpsubcheck
+
+ layer mvpsc mvpsccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvpsccopy
+ labels CONT
+
+ # Find contacts not covered in
+ # metal and pull them into the
+ # next layer up
+
+ templayer gencont CONT
+ and LI
+ and-not DIFF,TAP
+ and-not POLY
+ and-not DIODE
+ and-not nsubcheck
+ and-not psubcheck
+ and-not mvnsubcheck
+ and-not mvpsubcheck
+ copyup CONT,LI
+
+ templayer barecont CONT
+ and-not LI
+ and-not nsubcheck
+ and-not psubcheck
+ and-not mvnsubcheck
+ and-not mvpsubcheck
+ copyup CONT
+
+ layer glass GLASS,PADTXT,PADPIN
+ labels GLASS
+ labels PADTXT text
+ labels PADPIN port
+
+ templayer boundary BOUND,STDCELL,PADCELL
+ boundary
+
+ layer comment LVSTEXT
+ labels LVSTEXT text
+
+ layer comment TTEXT
+ labels TTEXT text
+
+ layer fillblock FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4
+ labels FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4
+
+# MOS Varactor
+
+ layer var POLY
+ and TAP
+ and NPLUS
+ and NWELL
+ and-not THKOX
+ and-not HVTP
+ # NOTE: Else forms a varactor that is not in the vendor netlist.
+ and-not COREID
+ labels POLY
+
+ layer varhvt POLY
+ and TAP
+ and NPLUS
+ and NWELL
+ and-not THKOX
+ and HVTP
+ labels POLY
+
+ layer mvvar POLY
+ and TAP
+ and NPLUS
+ and NWELL
+ and THKOX
+ labels POLY
+
+ calma NWELL 64 20
+ calma DIFF 65 20
+ calma DNWELL 64 18
+ calma PWRES 64 13
+ calma TAP 65 44
+ # LVTN
+ calma LVTN 125 44
+ # HVTR
+ calma HVTR 18 20
+ # HVTP
+ calma HVTP 78 44
+ # SONOS (TUNM)
+ calma SONOS 80 20
+ # NPLUS = NSDM
+ calma NPLUS 93 44
+ # PPLUS = PSDM
+ calma PPLUS 94 20
+ # HVI
+ calma THKOX 75 20
+ # NPC
+ calma NPC 95 20
+ # P+ POLY MASK
+ calma RPM 86 20
+ calma URPM 79 20
+ calma LDNTM 11 44
+ calma HVNTM 125 20
+ # Poly resistor ID mark
+ calma POLYRES 66 13
+ # Diffusion resistor ID mark
+ calma DIFFRES 65 13
+ calma POLY 66 20
+ calma POLYMOD 66 83
+ # Diode ID mark
+ calma DIODE 81 23
+ # Bipolar NPN mark
+ calma NPNID 82 20
+ # Bipolar PNP mark
+ calma PNPID 82 44
+ # Capacitor ID
+ calma CAPID 82 64
+ # Core area ID mark
+ calma COREID 81 2
+ # Standard cell ID mark
+ calma STDCELL 81 4
+ # Padframe cell ID mark
+ calma PADCELL 81 3
+ # Seal ring ID mark
+ calma SEALID 81 1
+ # Low tap density ID mark
+ calma LOWTAPDENSITY 81 14
+
+ # LICON
+ calma CONT 66 44
+ calma LI 67 20
+ calma MCON 67 44
+
+ calma MET1 68 20
+ calma VIA1 68 44
+ calma MET2 69 20
+ calma VIA2 69 44
+ calma MET3 70 20
+ calma VIA3 70 44
+ calma MET4 71 20
+ calma VIA4 71 44
+ calma MET5 72 20
+ calma RDL 74 20
+ calma GLASS 76 20
+
+ calma SUBPIN 64 59
+ calma PADPIN 76 5
+ calma DIFFPIN 65 6
+ calma TAPPIN 65 5
+ calma WELLPIN 64 5
+ calma LIPIN 67 5
+ calma POLYPIN 66 5
+ calma MET1PIN 68 5
+ calma MET2PIN 69 5
+ calma MET3PIN 70 5
+ calma MET4PIN 71 5
+ calma MET5PIN 72 5
+ calma RDLPIN 74 5
+
+ calma LIRES 67 13
+ calma MET1RES 68 13
+ calma MET2RES 69 13
+ calma MET3RES 70 13
+ calma MET4RES 71 13
+ calma MET5RES 72 13
+
+ calma MET1FILL 68 28
+ calma MET2FILL 69 28
+ calma MET3FILL 70 28
+ calma MET4FILL 71 28
+ calma MET5FILL 72 28
+
+ calma POLYSHORT 66 15
+ calma LISHORT 67 15
+ calma MET1SHORT 68 15
+ calma MET2SHORT 69 15
+ calma MET3SHORT 70 15
+ calma MET4SHORT 71 15
+ calma MET5SHORT 72 15
+
+ calma SUBTXT 122 16
+ calma PADTXT 76 16
+ calma DIFFTXT 65 16
+ calma POLYTXT 66 16
+ calma WELLTXT 64 16
+ calma LITXT 67 16
+ calma MET1TXT 68 16
+ calma MET2TXT 69 16
+ calma MET3TXT 70 16
+ calma MET4TXT 71 16
+ calma MET5TXT 72 16
+ calma RDLPIN 74 16
+
+ calma BOUND 235 4
+
+ calma LVSTEXT 83 44
+
+ calma CAPM 89 44
+ calma CAPM2 97 44
+
+ calma FILLOBSM1 62 24
+ calma FILLOBSM2 105 52
+ calma FILLOBSM3 107 24
+ calma FILLOBSM4 112 4
+
+#-----------------------------------------------------------------------
+
+style vendorimport
+ scalefactor 10 nanometers
+ gridlimit 5
+
+ options ignore-unknown-layer-labels no-reconnect-labels
+
+ ignore NPC
+ ignore SEALID
+ ignore CAPID
+ ignore LDNTM
+ ignore HVNTM
+ ignore POLYMOD
+ ignore LOWTAPDENSITY
+
+ layer pnp NWELL,WELLTXT,WELLPIN
+ and PNPID
+ labels NWELL
+ labels WELLTXT port
+ labels WELLPIN port
+
+ layer nwell NWELL,WELLTXT,WELLPIN
+ and-not PNPID
+ labels NWELL
+ labels WELLTXT port
+ labels WELLPIN port
+
+ layer pwell SUBTXT,SUBPIN
+ labels SUBTXT port
+ labels SUBPIN port
+
+ # Always draw pwell under p-tap
+ layer pwell TAP
+ and-not NWELL
+
+ layer dnwell DNWELL
+ labels DNWELL
+
+ layer npn DNWELL
+ and-not NWELL
+ and NPNID
+
+ layer rpw PWRES
+ and DNWELL
+ labels PWRES
+
+ templayer ndiffarea DIFF,DIFFTXT,DIFFPIN
+ and-not POLY
+ and-not NWELL
+ and-not PPLUS
+ and-not DIODE
+ and-not DIFFRES
+ and-not THKOX
+ and NPLUS
+ copyup ndifcheck
+ labels DIFF
+ labels DIFFTXT port
+ labels DIFFPIN port
+ labels TAPPIN port
+
+ layer ndiff ndiffarea
+
+ # Copy ndiff areas up for contact checks
+ templayer xndifcheck ndifcheck
+ copyup ndifcheck
+
+ templayer mvndiffarea DIFF,DIFFTXT,DIFFPIN
+ and-not POLY
+ and-not NWELL
+ and-not PPLUS
+ and-not DIODE
+ and-not DIFFRES
+ and THKOX
+ and NPLUS
+ copyup ndifcheck
+ labels DIFF
+ labels DIFFTXT port
+ labels DIFFPIN port
+
+ layer mvndiff mvndiffarea
+
+ # Copy ndiff areas up for contact checks
+ templayer mvxndifcheck mvndifcheck
+ copyup mvndifcheck
+
+ layer ndiode DIFF
+ and NPLUS
+ and DIODE
+ and-not NWELL
+ and-not POLY
+ and-not PPLUS
+ and-not THKOX
+ and-not LVTN
+ labels DIFF
+
+ layer ndiodelvt DIFF
+ and NPLUS
+ and DIODE
+ and-not NWELL
+ and-not POLY
+ and-not PPLUS
+ and-not THKOX
+ and LVTN
+ labels DIFF
+
+ templayer ndiodearea DIODE
+ and NPLUS
+ and-not THKOX
+ and-not NWELL
+ copyup DIODE,NPLUS
+
+ layer ndiffres DIFFRES
+ and NPLUS
+ and-not THKOX
+ labels DIFF
+
+ templayer pdiffarea DIFF,DIFFTXT,DIFFPIN
+ and-not POLY
+ and NWELL
+ and-not NPLUS
+ and-not DIODE
+ and-not THKOX
+ and PPLUS
+ copyup pdifcheck
+ labels DIFF
+ labels DIFFTXT port
+ labels DIFFPIN port
+
+ layer pdiff pdiffarea
+
+ layer mvndiode DIFF
+ and NPLUS
+ and DIODE
+ and THKOX
+ and-not POLY
+ and-not PPLUS
+ and-not LVTN
+ labels DIFF
+
+ layer nndiode DIFF
+ and NPLUS
+ and DIODE
+ and THKOX
+ and-not POLY
+ and-not PPLUS
+ and LVTN
+ labels DIFF
+
+ templayer mvndiodearea DIODE
+ and NPLUS
+ and THKOX
+ and-not NWELL
+ copyup DIODE,NPLUS
+
+ layer mvndiffres DIFFRES
+ and NPLUS
+ and THKOX
+ labels DIFF
+
+ templayer mvpdiffarea DIFF,DIFFTXT,DIFFPIN
+ and-not POLY
+ and NWELL
+ and-not NPLUS
+ and THKOX
+ and-not DIODE
+ and-not DIFFRES
+ and PPLUS
+ copyup mvpdifcheck
+ labels DIFF
+ labels DIFFTXT port
+ labels DIFFPIN port
+
+ layer mvpdiff mvpdiffarea
+
+ # Copy pdiff areas up for contact checks
+ templayer xpdifcheck pdifcheck
+ copyup pdifcheck
+
+ layer pdiode DIFF
+ and PPLUS
+ and-not POLY
+ and-not NPLUS
+ and-not THKOX
+ and-not LVTN
+ and-not HVTP
+ and DIODE
+ labels DIFF
+
+ layer pdiodelvt DIFF
+ and PPLUS
+ and-not POLY
+ and-not NPLUS
+ and-not THKOX
+ and LVTN
+ and-not HVTP
+ and DIODE
+ labels DIFF
+
+ layer pdiodehvt DIFF
+ and PPLUS
+ and-not POLY
+ and-not NPLUS
+ and-not THKOX
+ and-not LVTN
+ and HVTP
+ and DIODE
+ labels DIFF
+
+ templayer pdiodearea DIODE
+ and PPLUS
+ and-not THKOX
+ copyup DIODE,PPLUS
+
+ # Define pfet areas as known pdiff, regardless of the presence of a well.
+
+ templayer pfetarea DIFF
+ and-not NPLUS
+ and-not THKOX
+ and POLY
+
+ layer pfet pfetarea
+ and-not LVTN
+ and-not HVTP
+ and-not STDCELL
+ and-not COREID
+ labels DIFF
+
+ layer scpfet pfetarea
+ and-not LVTN
+ and-not HVTP
+ and STDCELL
+ labels DIFF
+
+ layer scpfethvt pfetarea
+ and-not LVTN
+ and HVTP
+ and STDCELL
+ labels DIFF
+
+ layer ppu pfetarea
+ and-not LVTN
+ and HVTP
+ and COREID
+ labels DIFF
+
+ layer pfetlvt pfetarea
+ and LVTN
+ labels DIFF
+
+ layer pfetmvt pfetarea
+ and HVTR
+ labels DIFF
+
+ layer pfethvt pfetarea
+ and HVTP
+ and-not STDCELL
+ and-not COREID
+ labels DIFF
+
+ # Always force nwell under pfet (nwell encloses pdiff by 0.18)
+ layer nwell pfetarea
+ grow 180
+
+ # Copy mvpdiff areas up for contact checks
+ templayer mvxpdifcheck mvpdifcheck
+ copyup mvpdifcheck
+
+ layer mvpdiode DIFF
+ and PPLUS
+ and-not POLY
+ and-not NPLUS
+ and THKOX
+ and DIODE
+ labels DIFF
+
+ templayer mvpdiodearea DIODE
+ and PPLUS
+ and THKOX
+ copyup DIODE,PPLUS
+
+ # Define pfet areas as known pdiff,
+ # regardless of the presence of a
+ # well.
+
+ templayer mvpfetarea DIFF
+ and-not NPLUS
+ and THKOX
+ and POLY
+
+ layer mvpfet mvpfetarea
+ labels DIFF
+
+ layer pdiff DIFF,DIFFTXT,DIFFPIN
+ and-not NPLUS
+ and-not POLY
+ and-not THKOX
+ and-not DIODE
+ and-not DIFFRES
+ labels DIFF
+ labels DIFFTXT port
+ labels DIFFPIN port
+
+ layer pdiffres DIFFRES
+ and PPLUS
+ and NWELL
+ and-not THKOX
+ labels DIFF
+
+ layer nfet DIFF
+ and POLY
+ and-not PPLUS
+ and NPLUS
+ and-not THKOX
+ and-not LVTN
+ and-not SONOS
+ and-not STDCELL
+ labels DIFF
+
+ layer scnfet DIFF
+ and POLY
+ and-not PPLUS
+ and NPLUS
+ and-not NWELL
+ and-not THKOX
+ and-not LVTN
+ and-not SONOS
+ and STDCELL
+ labels DIFF
+
+ layer npass DIFF
+ and POLY
+ and-not PPLUS
+ and NPLUS
+ and-not NWELL
+ and COREID
+ labels DIFF
+
+ layer npd DIFF
+ and POLY
+ and-not PPLUS
+ and NPLUS
+ and-not NWELL
+ and COREID
+ # Shrink-grow operation eliminates the smaller npass device
+ shrink 70
+ grow 70
+ labels DIFF
+
+ layer nfetlvt DIFF
+ and POLY
+ and-not PPLUS
+ and NPLUS
+ and-not THKOX
+ and LVTN
+ and-not SONOS
+ labels DIFF
+
+ layer nsonos DIFF
+ and POLY
+ and-not PPLUS
+ and NPLUS
+ and-not THKOX
+ and LVTN
+ and SONOS
+ labels DIFF
+
+ templayer nsdarea TAP
+ and NPLUS
+ and NWELL
+ and-not POLY
+ and-not PPLUS
+ and-not THKOX
+ copyup nsubcheck
+
+ layer nsd nsdarea
+ labels TAP
+
+ layer nsd TAP,TAPPIN
+ and NPLUS
+ and-not POLY
+ and-not THKOX
+ labels TAP
+ labels TAPPIN port
+
+ layer corenvar TAP
+ and NPLUS
+ and POLY
+ and COREID
+ labels TAP
+
+ templayer nsdexpand nsdarea
+ grow 500
+
+ # Copy nsub areas up for contact checks
+ templayer xnsubcheck nsubcheck
+ copyup nsubcheck
+
+ templayer psdarea TAP
+ and PPLUS
+ and-not NWELL
+ and-not POLY
+ and-not NPLUS
+ and-not THKOX
+ and-not pfetexpand
+ copyup psubcheck
+
+ layer psd psdarea
+ labels TAP
+
+ layer psd TAP,TAPPIN
+ and PPLUS
+ and-not POLY
+ and-not THKOX
+ labels TAP
+ labels TAPPIN port
+
+ layer corepvar TAP
+ and PPLUS
+ and POLY
+ and COREID
+ labels TAP
+
+ templayer psdexpand psdarea
+ grow 500
+
+ layer mvpdiff DIFF,DIFFTXT,DIFFPIN
+ and-not NPLUS
+ and-not POLY
+ and THKOX
+ and mvpfetexpand
+ labels DIFF
+ labels DIFFTXT port
+ labels DIFFPIN port
+
+ layer mvpdiffres DIFFRES
+ and PPLUS
+ and NWELL
+ and THKOX
+ and-not mvrdpioedge
+ labels DIFF
+
+ templayer mvnfetarea DIFF
+ and POLY
+ and-not PPLUS
+ and NPLUS
+ and-not LVTN
+ and THKOX
+ grow 1000
+
+ templayer mvnnfetarea DIFF,TAP
+ and POLY
+ and-not PPLUS
+ and NPLUS
+ and LVTN
+ and THKOX
+ and-not mvnfetarea
+
+ layer mvnfet DIFF
+ and POLY
+ and-not PPLUS
+ and NPLUS
+ and THKOX
+ and-not mvnnfetarea
+ labels DIFF
+
+ layer mvnnfet mvnnfetarea
+ labels DIFF
+
+ templayer mvnsdarea TAP
+ and NPLUS
+ and NWELL
+ and-not POLY
+ and-not PPLUS
+ and THKOX
+ copyup mvnsubcheck
+
+ layer mvnsd mvnsdarea
+ labels TAP
+
+ layer mvnsd TAP,TAPPIN
+ and NPLUS
+ and THKOX
+ labels TAP
+ labels TAPPIN port
+
+ templayer mvnsdexpand mvnsdarea
+ grow 500
+
+ # Copy nsub areas up for contact checks
+ templayer mvxnsubcheck mvnsubcheck
+ copyup mvnsubcheck
+
+ templayer mvpsdarea DIFF
+ and PPLUS
+ and-not NWELL
+ and-not POLY
+ and-not NPLUS
+ and THKOX
+ and-not mvpfetexpand
+ copyup mvpsubcheck
+
+ layer mvpsd mvpsdarea
+ labels DIFF
+
+ layer mvpsd TAP,TAPPIN
+ and PPLUS
+ and THKOX
+ labels TAP
+ labels TAPPIN port
+
+ templayer mvpsdexpand mvpsdarea
+ grow 500
+
+ # Copy psub areas up for contact checks
+ templayer xpsubcheck psubcheck
+ copyup psubcheck
+
+ templayer mvxpsubcheck mvpsubcheck
+ copyup mvpsubcheck
+
+ layer psd TAP
+ and-not PPLUS
+ and-not NPLUS
+ and-not POLY
+ and-not THKOX
+ and-not pfetexpand
+ and psdexpand
+
+ layer nsd TAP
+ and-not PPLUS
+ and-not NPLUS
+ and-not POLY
+ and-not THKOX
+ and nsdexpand
+
+ layer mvpsd TAP
+ and-not PPLUS
+ and-not NPLUS
+ and-not POLY
+ and THKOX
+ and-not mvpfetexpand
+ and mvpsdexpand
+
+ layer mvnsd TAP
+ and-not PPLUS
+ and-not NPLUS
+ and-not POLY
+ and THKOX
+ and mvnsdexpand
+
+ templayer hresarea POLY
+ and RPM
+ grow 3000
+
+ templayer uresarea POLY
+ and URPM
+ grow 3000
+
+ templayer diffresarea DIFFRES
+ and-not THKOX
+ grow 3000
+
+ templayer mvdiffresarea DIFFRES
+ and THKOX
+ grow 3000
+
+ templayer resarea diffresarea,mvdiffresarea,hresarea,uresarea
+
+ layer pfet POLY
+ and DIFF
+ and diffresarea
+ and-not NPLUS
+ and-not STDCELL
+
+ layer scpfet POLY
+ and DIFF
+ and diffresarea
+ and-not HVTP
+ and-not NPLUS
+ and STDCELL
+
+ layer scpfethvt POLY
+ and DIFF
+ and diffresarea
+ and HVTP
+ and-not NPLUS
+ and STDCELL
+
+ templayer xpolyterm RPM,URPM
+ and POLY
+ and-not POLYRES
+ # add back the 0.06um contact surround in the direction of the resistor
+ grow 60
+ and POLY
+
+ layer xpc xpolyterm
+
+ templayer polyarea POLY
+ and-not POLYRES
+ and-not POLYSHORT
+ and-not DIFF
+ and-not TAP
+ and-not RPM
+ and-not URPM
+ copyup polycheck
+
+ layer poly polyarea,POLYTXT,POLYPIN
+ labels POLY
+ labels POLYTXT port
+ labels POLYPIN port
+
+ # Copy (non-resistor) poly areas up for contact checks
+ templayer xpolycheck polycheck
+ copyup polycheck
+
+ layer mrp1 POLY
+ and POLYRES
+ and-not RPM
+ and-not URPM
+ labels POLY
+
+ layer rmp POLY
+ and POLYSHORT
+ labels POLY
+
+ layer xhrpoly POLY
+ and POLYRES
+ and RPM
+ and-not URPM
+ and PPLUS
+ and NPC
+ and-not xpolyterm
+ labels POLY
+
+ layer uhrpoly POLY
+ and POLYRES
+ and URPM
+ and-not RPM
+ and NPC
+ and-not xpolyterm
+ labels POLY
+
+ templayer ndcbase CONT
+ and DIFF
+ and NPLUS
+ and-not NWELL
+ and LI
+ and-not THKOX
+
+ layer ndc ndcbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or ndcbase
+ labels CONT
+
+ templayer nscbase CONT
+ and DIFF,TAP
+ and NPLUS
+ and NWELL
+ and LI
+ and-not THKOX
+
+ layer nsc nscbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or nscbase
+ labels CONT
+
+ templayer pdcbase CONT
+ and DIFF
+ and PPLUS
+ and NWELL
+ and LI
+ and-not THKOX
+
+ layer pdc pdcbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pdcbase
+ labels CONT
+
+ templayer pdcnowell CONT
+ and DIFF
+ and PPLUS
+ and pfetexpand
+ and LI
+ and-not THKOX
+
+ layer pdc pdcnowell
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pdcnowell
+ labels CONT
+
+ templayer pscbase CONT
+ and DIFF,TAP
+ and PPLUS
+ and-not NWELL
+ and-not pfetexpand
+ and LI
+ and-not THKOX
+
+ layer psc pscbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pscbase
+ labels CONT
+
+ templayer pcbase CONT
+ and POLY
+ and-not DIFF
+ and-not RPM,URPM
+ and LI
+
+ layer pc pcbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pcbase
+ labels CONT
+
+ templayer ndicbase CONT
+ and DIFF
+ and NPLUS
+ and DIODE
+ and-not POLY
+ and-not PPLUS
+ and-not THKOX
+ and-not LVTN
+
+ layer ndic ndicbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or ndicbase
+ labels CONT
+
+ templayer ndilvtcbase CONT
+ and DIFF
+ and NPLUS
+ and DIODE
+ and-not POLY
+ and-not PPLUS
+ and-not THKOX
+ and LVTN
+
+ layer ndilvtc ndilvtcbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or ndilvtcbase
+ labels CONT
+
+ templayer pdicbase CONT
+ and DIFF
+ and PPLUS
+ and DIODE
+ and-not POLY
+ and-not NPLUS
+ and-not THKOX
+ and-not LVTN
+ and-not HVTP
+
+ layer pdic pdicbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pdicbase
+ labels CONT
+
+ templayer pdilvtcbase CONT
+ and DIFF
+ and PPLUS
+ and DIODE
+ and-not POLY
+ and-not NPLUS
+ and-not THKOX
+ and LVTN
+ and-not HVTP
+
+ layer pdilvtc pdilvtcbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pdilvtcbase
+ labels CONT
+
+ templayer pdihvtcbase CONT
+ and DIFF
+ and PPLUS
+ and DIODE
+ and-not POLY
+ and-not NPLUS
+ and-not THKOX
+ and-not LVTN
+ and HVTP
+
+ layer pdihvtc pdihvtcbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pdihvtcbase
+ labels CONT
+
+ templayer mvndcbase CONT
+ and DIFF
+ and NPLUS
+ and-not NWELL
+ and LI
+ and THKOX
+
+ layer mvndc mvndcbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvndcbase
+ labels CONT
+
+ templayer mvnscbase CONT
+ and DIFF,TAP
+ and NPLUS
+ and NWELL
+ and LI
+ and THKOX
+
+ layer mvnsc mvnscbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvnscbase
+ labels CONT
+
+ templayer mvpdcbase CONT
+ and DIFF
+ and PPLUS
+ and NWELL
+ and LI
+ and THKOX
+
+ layer mvpdc mvpdcbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvpdcbase
+ labels CONT
+
+ templayer mvpdcnowell CONT
+ and DIFF
+ and PPLUS
+ and mvpfetexpand
+ and MET1
+ and THKOX
+
+ layer mvpdc mvpdcnowell
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvpdcnowell
+ labels CONT
+
+ templayer mvpscbase CONT
+ and DIFF,TAP
+ and PPLUS
+ and-not NWELL
+ and-not mvpfetexpand
+ and LI
+ and THKOX
+
+ layer mvpsc mvpscbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvpscbase
+ labels CONT
+
+ templayer mvndicbase CONT
+ and DIFF
+ and NPLUS
+ and DIODE
+ and-not POLY
+ and-not PPLUS
+ and-not LVTN
+ and THKOX
+
+ layer mvndic mvndicbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvndicbase
+ labels CONT
+
+ templayer nndicbase CONT
+ and DIFF
+ and NPLUS
+ and DIODE
+ and-not POLY
+ and-not PPLUS
+ and LVTN
+ and THKOX
+
+ layer nndic nndicbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or nndicbase
+ labels CONT
+
+ templayer mvpdicbase CONT
+ and DIFF
+ and PPLUS
+ and DIODE
+ and-not POLY
+ and-not NPLUS
+ and THKOX
+
+ layer mvpdic mvpdicbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvpdicbase
+ labels CONT
+
+ layer coreli LI,LITXT,LIPIN
+ and-not LIRES,LISHORT
+ and COREID
+ labels LI
+ labels LITXT port
+ labels LIPIN port
+
+ layer locali LI,LITXT,LIPIN
+ and-not LIRES,LISHORT
+ and-not COREID
+ labels LI
+ labels LITXT port
+ labels LIPIN port
+
+ layer rli LI
+ and LIRES,LISHORT
+ labels LIRES,LISHORT
+
+ layer lic MCON
+ grow 95
+ shrink 95
+ shrink 85
+ grow 85
+ or MCON
+ labels MCON
+
+ layer m1 MET1,MET1TXT,MET1PIN
+ and-not MET1RES,MET1SHORT
+ labels MET1
+ labels MET1TXT port
+ labels MET1PIN port
+
+ layer rm1 MET1
+ and MET1RES,MET1SHORT
+ labels MET1RES,MET1SHORT
+
+ layer m1fill MET1FILL
+ labels MET1FILL
+
+ layer mimcap MET3
+ and CAPM
+ labels CAPM
+
+ layer mimcc VIA3
+ and CAPM
+ grow 60
+ grow 40
+ shrink 40
+ labels CAPM
+
+ layer mimcap2 MET4
+ and CAPM2
+ labels CAPM2
+
+ layer mim2cc VIA4
+ and CAPM2
+ grow 190
+ grow 210
+ shrink 210
+ labels CAPM2
+
+
+ templayer m2cbase VIA1
+ grow 55
+
+ layer m2c m2cbase
+ grow 30
+ shrink 30
+ shrink 130
+ grow 130
+ or m2cbase
+
+ layer m2 MET2,MET2TXT,MET2PIN
+ and-not MET2RES,MET2SHORT
+ labels MET2
+ labels MET2TXT port
+ labels MET2PIN port
+
+ layer rm2 MET2
+ and MET2RES,MET2SHORT
+ labels MET2RES,MET2SHORT
+
+ layer m2fill MET2FILL
+ labels MET2FILL
+
+ templayer m3cbase VIA2
+ grow 40
+
+ layer m3c m3cbase
+ grow 60
+ shrink 60
+ shrink 140
+ grow 140
+ or m3cbase
+
+ layer m3 MET3,MET3TXT,MET3PIN
+ and-not MET3RES,MET3SHORT
+ and-not CAPM
+ labels MET3
+ labels MET3TXT port
+ labels MET3PIN port
+
+ layer rm3 MET3
+ and MET3RES,MET3SHORT
+ labels MET3RES,MET3SHORT
+
+ layer m3fill MET3FILL
+ labels MET3FILL
+
+
+ templayer via3base VIA3
+ and-not CAPM
+ grow 60
+
+ layer via3 via3base
+ grow 40
+ shrink 40
+ shrink 160
+ grow 160
+ or via3base
+
+ layer m4 MET4,MET4TXT,MET4PIN
+ and-not MET4RES,MET4SHORT
+ and-not CAPM2
+ labels MET4
+ labels MET4TXT port
+ labels MET4PIN port
+
+ layer rm4 MET4
+ and MET4RES,MET4SHORT
+ labels MET4RES,MET4SHORT
+
+ layer m4fill MET4FILL
+ labels MET4FILL
+
+ layer m5 MET5,MET5TXT,MET5PIN
+ and-not MET5RES,MET5SHORT
+ labels MET5
+ labels MET5TXT port
+ labels MET5PIN port
+
+ layer rm5 MET5
+ and MET5RES,MET5SHORT
+ labels MET5RES,MET5SHORT
+
+ layer m5fill MET5FILL
+ labels MET5FILL
+
+ templayer via4base VIA4
+ and-not CAPM2
+ grow 190
+
+ layer via4 via4base
+ grow 210
+ shrink 210
+ shrink 590
+ grow 590
+ or via4base
+
+ layer metrdl RDL,RDLTXT,RDLPIN
+ labels RDL
+ labels RDLTXT port
+ labels RDLPIN port
+
+ # Find diffusion not covered in
+ # NPLUS or PPLUS and pull it into
+ # the next layer up
+
+ templayer gentrans DIFF
+ and-not PPLUS
+ and-not NPLUS
+ and POLY
+ copyup DIFF,POLY
+
+ templayer gendiff DIFF,TAP
+ and-not PPLUS
+ and-not NPLUS
+ and-not POLY
+ copyup DIFF
+
+ # Handle contacts found by copyup
+
+ templayer ndiccopy CONT
+ and LI
+ and DIODE
+ and NPLUS
+ and-not THKOX
+
+ layer ndic ndiccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or ndiccopy
+ labels CONT
+
+ templayer mvndiccopy CONT
+ and LI
+ and DIODE
+ and NPLUS
+ and THKOX
+
+ layer mvndic mvndiccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvndiccopy
+ labels CONT
+
+ templayer pdiccopy CONT
+ and LI
+ and DIODE
+ and PPLUS
+ and-not THKOX
+
+ layer pdic pdiccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pdiccopy
+ labels CONT
+
+ templayer mvpdiccopy CONT
+ and LI
+ and DIODE
+ and PPLUS
+ and THKOX
+
+ layer mvpdic mvpdiccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvpdiccopy
+ labels CONT
+
+ templayer ndccopy CONT
+ and ndifcheck
+
+ layer ndc ndccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or ndccopy
+ labels CONT
+
+ templayer mvndccopy CONT
+ and mvndifcheck
+
+ layer mvndc mvndccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvndccopy
+ labels CONT
+
+ templayer pdccopy CONT
+ and pdifcheck
+
+ layer pdc pdccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pdccopy
+ labels CONT
+
+ templayer mvpdccopy CONT
+ and mvpdifcheck
+
+ layer mvpdc mvpdccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvpdccopy
+ labels CONT
+
+ templayer pccopy CONT
+ and polycheck
+
+ layer pc pccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pccopy
+ labels CONT
+
+ templayer nsccopy CONT
+ and nsubcheck
+
+ layer nsc nsccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or nsccopy
+ labels CONT
+
+ templayer mvnsccopy CONT
+ and mvnsubcheck
+
+ layer mvnsc mvnsccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvnsccopy
+ labels CONT
+
+ templayer psccopy CONT
+ and psubcheck
+
+ layer psc psccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or psccopy
+ labels CONT
+
+ templayer mvpsccopy CONT
+ and mvpsubcheck
+
+ layer mvpsc mvpsccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvpsccopy
+ labels CONT
+
+ # Find contacts not covered in
+ # metal and pull them into the
+ # next layer up
+
+ templayer gencont CONT
+ and LI
+ and-not DIFF,TAP
+ and-not POLY
+ and-not DIODE
+ and-not nsubcheck
+ and-not psubcheck
+ and-not mvnsubcheck
+ and-not mvpsubcheck
+ copyup CONT,LI
+
+ templayer barecont CONT
+ and-not LI
+ and-not nsubcheck
+ and-not psubcheck
+ and-not mvnsubcheck
+ and-not mvpsubcheck
+ copyup CONT
+
+ layer glass GLASS,PADTXT,PADPIN
+ labels GLASS
+ labels PADTXT port
+ labels PADPIN port
+
+ templayer boundary BOUND,STDCELL,PADCELL
+ boundary
+
+ layer comment LVSTEXT
+ labels LVSTEXT text
+
+ layer comment TTEXT
+ labels TTEXT text
+
+ layer fillblock FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4
+ labels FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4
+
+# MOS Varactor
+
+ layer var POLY
+ and TAP
+ and NPLUS
+ and NWELL
+ and-not THKOX
+ and-not HVTP
+ # NOTE: Else forms a varactor that is not in the vendor netlist.
+ and-not COREID
+ labels POLY
+
+ layer varhvt POLY
+ and TAP
+ and NPLUS
+ and NWELL
+ and-not THKOX
+ and HVTP
+ labels POLY
+
+ layer mvvar POLY
+ and TAP
+ and NPLUS
+ and NWELL
+ and THKOX
+ labels POLY
+
+ calma NWELL 64 20
+ calma DIFF 65 20
+ calma DNWELL 64 18
+ calma PWRES 64 13
+ calma TAP 65 44
+ # LVTN
+ calma LVTN 125 44
+ # HVTR
+ calma HVTR 18 20
+ # HVTP
+ calma HVTP 78 44
+ # SONOS (TUNM)
+ calma SONOS 80 20
+ # NPLUS = NSDM
+ calma NPLUS 93 44
+ # PPLUS = PSDM
+ calma PPLUS 94 20
+ # HVI
+ calma THKOX 75 20
+ # NPC
+ calma NPC 95 20
+ # P+ POLY MASK
+ calma RPM 86 20
+ calma URPM 79 20
+ calma LDNTM 11 44
+ calma HVNTM 125 20
+ # Poly resistor ID mark
+ calma POLYRES 66 13
+ # Diffusion resistor ID mark
+ calma DIFFRES 65 13
+ calma POLY 66 20
+ calma POLYMOD 66 83
+ # Diode ID mark
+ calma DIODE 81 23
+ # Bipolar NPN mark
+ calma NPNID 82 20
+ # Bipolar PNP mark
+ calma PNPID 82 44
+ # Capacitor ID
+ calma CAPID 82 64
+ # Core area ID mark
+ calma COREID 81 2
+ # Standard cell ID mark
+ calma STDCELL 81 4
+ # Padframe cell ID mark
+ calma PADCELL 81 3
+ # Seal ring ID mark
+ calma SEALID 81 1
+ # Low tap density ID mark
+ calma LOWTAPDENSITY 81 14
+
+ # LICON
+ calma CONT 66 44
+ calma LI 67 20
+ calma MCON 67 44
+
+ calma MET1 68 20
+ calma VIA1 68 44
+ calma MET2 69 20
+ calma VIA2 69 44
+ calma MET3 70 20
+ calma VIA3 70 44
+ calma MET4 71 20
+ calma VIA4 71 44
+ calma MET5 72 20
+ calma RDL 74 20
+ calma GLASS 76 20
+
+ calma SUBPIN 64 59
+ calma PADPIN 76 5
+ calma DIFFPIN 65 6
+ calma TAPPIN 65 5
+ calma WELLPIN 64 5
+ calma LIPIN 67 5
+ calma POLYPIN 66 5
+ calma MET1PIN 68 5
+ calma MET2PIN 69 5
+ calma MET3PIN 70 5
+ calma MET4PIN 71 5
+ calma MET5PIN 72 5
+ calma RDLPIN 74 5
+
+ calma LIRES 67 13
+ calma MET1RES 68 13
+ calma MET2RES 69 13
+ calma MET3RES 70 13
+ calma MET4RES 71 13
+ calma MET5RES 72 13
+
+ calma MET1FILL 68 28
+ calma MET2FILL 69 28
+ calma MET3FILL 70 28
+ calma MET4FILL 71 28
+ calma MET5FILL 72 28
+
+ calma POLYSHORT 66 15
+ calma LISHORT 67 15
+ calma MET1SHORT 68 15
+ calma MET2SHORT 69 15
+ calma MET3SHORT 70 15
+ calma MET4SHORT 71 15
+ calma MET5SHORT 72 15
+
+ calma SUBTXT 122 16
+ calma PADTXT 76 16
+ calma DIFFTXT 65 16
+ calma POLYTXT 66 16
+ calma WELLTXT 64 16
+ calma LITXT 67 16
+ calma MET1TXT 68 16
+ calma MET2TXT 69 16
+ calma MET3TXT 70 16
+ calma MET4TXT 71 16
+ calma MET5TXT 72 16
+ calma RDLPIN 74 16
+
+ calma BOUND 235 4
+
+ calma LVSTEXT 83 44
+
+ calma CAPM 89 44
+ calma CAPM2 97 44
+
+ calma FILLOBSM1 62 24
+ calma FILLOBSM2 105 52
+ calma FILLOBSM3 107 24
+ calma FILLOBSM4 112 4
+
+style waffleimport
+ # This style is for reading back and validating shapes
+ # generated by the "wafflefill" cifoutput style.
+
+ scalefactor 10 nanometers
+ gridlimit 5
+
+ options ignore-unknown-layer-labels no-reconnect-labels
+
+ layer ndiff FOMMASK
+ layer poly POLYMASK
+ layer metal1 MET1MASK
+ layer metal2 MET2MASK
+ layer metal3 MET3MASK
+ layer metal4 MET4MASK
+ layer metal5 MET5MASK
+
+ calma FOMMASK 23 0
+ calma POLYMASK 28 0
+ calma MET1MASK 36 0
+ calma MET2MASK 41 0
+ calma MET3MASK 34 0
+ calma MET4MASK 51 0
+ calma MET5MASK 59 0
+
+style rdlimport
+ # This style is for reading shapes generated with the RDL layers
+
+ scalefactor 10 nanometers
+ gridlimit 5
+
+ options ignore-unknown-layer-labels no-reconnect-labels
+
+ layer mrdl RDL
+ layer mrdlc RDLC
+
+ calma RDL 10 0
+ calma RDLC 20 0
+
+end
+
+#-----------------------------------------------------
+# Digital flow maze router cost parameters
+#-----------------------------------------------------
+
+mzrouter
+end
+
+#-----------------------------------------------------
+# Vendor DRC rules
+#-----------------------------------------------------
+
+drc
+
+ style drc variants (fast),(full),(routing)
+ scalefactor 10
+ cifstyle drc
+
+ variants (fast),(full)
+
+#-----------------------------
+# DNWELL
+#-----------------------------
+
+ width dnwell 3000 "Deep N-well width < %d (dnwell.2)"
+ spacing dnwell dnwell 6300 touching_ok "Deep N-well spacing < %d (dnwell.3)"
+ spacing dnwell allnwell 4500 surround_ok \
+ "Deep N-well spacing to N-well < %d (nwell.7)"
+
+ variants (full)
+ cifmaxwidth nwell_missing 0 bend_illegal \
+ "N-well overlap of Deep N-well < 0.4um outside, 1.03um inside (nwell.5a, 7)"
+ cifmaxwidth dnwell_missing 0 bend_illegal \
+ "SONOS nFET must be in Deep N-well (tunm.6a)"
+
+ cifmaxwidth pdiff_crosses_dnwell 0 bend_illegal \
+ "P+ diff cannot straddle Deep N-well (dnwell.5)"
+ variants (fast),(full)
+
+#-----------------------------
+# NWELL
+#-----------------------------
+
+ width allnwell 840 "N-well width < %d (nwell.1)"
+ spacing allnwell allnwell 1270 touching_ok "N-well spacing < %d (nwell.2a)"
+
+ variants (full)
+ cifmaxwidth nwell_missing_tap 0 bend_illegal \
+ "All nwells must contain metal-connected N+ taps (nwell.4)"
+
+ cifspacing mvnwell lvnwell 2000 touching_illegal \
+ "Spacing of HV nwell to LV nwell < 2.0um (nwell.8)"
+ cifspacing mvnwell mvnwell 2000 touching_ok \
+ "Spacing of HV nwell to HV nwell < 2.0um (nwell.8)"
+ variants (fast),(full)
+
+#-----------------------------
+# DIFF
+#-----------------------------
+
+ width *ndiff,nfet,scnfet,npd,npass,*nsd,*ndiode,ndiffres,*pdiff,pfet,scpfet,scpfethvt,ppu,*psd,*pdiode,pdiffres \
+ 150 "Diffusion width < %d (diff/tap.1)"
+ width *mvndiff,mvnfet,mvnnfet,*mvndiode,*nndiode,mvndiffres,*mvpdiff,mvpfet,*mvpdiode,mvpdiffres 290 \
+ "MV Diffusion width < %d (diff/tap.14)"
+
+ width *mvnsd,*mvpsd 150 "MV Tap width < %d (diff/tap.1)"
+ extend *mvpsd *mvndiff 700 "MV Butting tap length < %d (diff/tap.16)"
+ extend *mvnsd *mvpdiff 700 "MV Butting tap length < %d (diff/tap.16)"
+ extend *psd *ndiff 290 "Butting tap length < %d (diff/tap.4)"
+ extend *nsd *pdiff 290 "Butting tap length < %d (diff/tap.4)"
+ width mvpdiffres 150 "MV P-Diffusion resistor width < %d (diff/tap.14a)"
+ spacing alldifflv,var,varhvt alldifflv,var,varhvt 270 touching_ok \
+ "Diffusion spacing < %d (diff/tap.3)"
+ spacing alldiffmvnontap,mvvar alldiffmvnontap,mvvar 300 touching_ok \
+ "MV Diffusion spacing < %d (diff/tap.15a)"
+ spacing alldiffmv *mvnsd,*mvpsd 270 touching_ok \
+ "MV Diffusion to MV tap spacing < %d (diff/tap.3)"
+ spacing *mvndiff,mvnfet,mvnnfet,*mvndiode,*nndiode,mvndiffres,mvvar *mvpsd 370 \
+ touching_ok "MV P-Diffusion to MV N-tap spacing < %d (diff/tap.15b)"
+ spacing *mvnsd,*mvpdiff,mvpfet,mvvar,*mvpdiode *mvpsd,*psd 760 touching_illegal \
+ "MV Diffusion in N-well to P-tap spacing < %d (diff/tap.20 + diff/tap.17,19)"
+ spacing *ndiff,*ndiode,nfet allnwell 340 touching_illegal \
+ "N-Diffusion spacing to N-well < %d (diff/tap.9)"
+ spacing *mvndiff,*mvndiode,mvnfet,mvnnfet allnwell 340 touching_illegal \
+ "N-Diffusion spacing to N-well < %d (diff/tap.9)"
+ spacing *psd allnwell 130 touching_illegal \
+ "P-tap spacing to N-well < %d (diff/tap.11)"
+ spacing *mvpsd allnwell 130 touching_illegal \
+ "P-tap spacing to N-well < %d (diff/tap.11)"
+ surround *nsd allnwell 180 absence_illegal \
+ "N-well overlap of N-tap < %d (diff/tap.10)"
+ surround *mvnsd allnwell 330 absence_illegal \
+ "N-well overlap of MV N-tap < %d (diff/tap.19)"
+ surround *pdiff,*pdiode,pfet,scpfet,ppu allnwell 180 absence_illegal \
+ "N-well overlap of P-Diffusion < %d (diff/tap.8)"
+ surround *mvpdiff,*mvpdiode,mvpfet allnwell 330 absence_illegal \
+ "N-well overlap of P-Diffusion < %d (diff/tap.17)"
+ surround mvvar allnwell 560 absence_illegal \
+ "N-well overlap of MV varactor < %d (lvtn.10 + lvtn.4b)"
+ spacing *mvndiode *mvndiode 1070 touching_ok \
+ "MV N-diode spacing < %d (hvntm.2 + 2 * hvntm.3)"
+
+variants (full)
+ cifspacing allmvdiffnowell lvnwell 825 touching_illegal \
+ "MV diffusion to LV nwell spacing < %d (hvi.5 + nsd/psd.5)"
+variants (fast),(full)
+
+ spacing allnfets allpactivenonfet 270 touching_illegal \
+ "nFET cannot abut P-diffusion (diff/tap.3)"
+ spacing allpfets allnactivenonfet 270 touching_illegal \
+ "pFET cannot abut N-diffusion (diff/tap.3)"
+
+ # Butting junction rules
+ edge4way (*psd)/a ~(*ndiff,*psd)/a 125 ~(*ndiff)/a (*ndiff)/a 125 \
+ "N-Diffusion to P-tap spacing < %d across butted junction (psd.5b)"
+ edge4way (*ndiff)/a ~(*ndiff,*psd)/a 125 ~(*psd)/a (*psd)/a 125 \
+ "N-Diffusion to P-tap spacing < %d across butted junction (psd.5a)"
+ edge4way (*nsd)/a ~(*pdiff,*nsd)/a 125 ~(*pdiff)/a (*pdiff)/a 125 \
+ "P-Diffusion to N-tap spacing < %d across butted junction (nsd.5b)"
+ edge4way (*pdiff)/a ~(*pdiff,*nsd)/a 125 ~(*nsd)/a (*nsd)/a 125 \
+ "P-Diffusion to N-tap spacing < %d across butted junction (nsd.5a)"
+
+ edge4way (*mvpsd)/a ~(*mvndiff,*mvpsd)/a 125 ~(*mvndiff)/a (*mvndiff)/a 125 \
+ "MV N-Diffusion to MV P-tap spacing < %d across butted junction (psd.5b)"
+ edge4way (*mvndiff)/a ~(*mvndiff,*mvpsd)/a 125 ~(*mvpsd)/a (*mvpsd)/a 125 \
+ "MV N-Diffusion to MV P-tap spacing < %d across butted junction (psd.5a)"
+ edge4way (*mvnsd)/a ~(*mvpdiff,*mvnsd)/a 125 ~(*mvpdiff)/a (*mvpdiff)/a 125 \
+ "MV P-Diffusion to MV N-tap spacing < %d across butted junction (nsd.5b)"
+ edge4way (*mvpdiff)/a ~(*mvpdiff,*mvnsd)/a 125 ~(*mvnsd)/a (*mvnsd)/a 125 \
+ "MV P-Diffusion to MV N-tap spacing < %d across butted junction (nsd.5a)"
+
+ # Sandwiched butting junction restrictions
+ edge4way (*pdiff)/a (*nsd)/a 400 ~(*pdiff)/a 0 0 "NSDM width < %d (diff/tap.5)"
+ edge4way (*ndiff)/a (*psd)/a 400 ~(*ndiff)/a 0 0 "PSDM width < %d (diff/tap.5)"
+
+ area *nsd,*mvnsd 70110 150 "N-tap minimum area < 0.07011um^2 (nsd.10b)"
+ area *psd,*mvpsd 70110 150 "P-tap minimum area < 0.07011um^2 (psd.10b)"
+
+ angles allactive 90 "Only 90 degree angles permitted on diff and tap (x.2)"
+
+ variants (full)
+ cifmaxwidth tap_missing_licon 0 bend_illegal "All taps must be contacted (licon.16)"
+
+ # Latchup rules
+ cifmaxwidth ptap_missing 0 bend_illegal \
+ "N-diff distance to P-tap must be < 15.0um (LU.2)"
+ cifmaxwidth dptap_missing 0 bend_illegal \
+ "N-diff distance to P-tap in deep nwell.must be < 15.0um (LU.2.1)"
+ cifmaxwidth ntap_missing 0 bend_illegal \
+ "P-diff distance to N-tap must be < 15.0um (LU.3)"
+
+ variants (fast),(full)
+
+#-----------------------------
+# POLY
+#-----------------------------
+
+ width allpoly 150 "poly width < %d (poly.1a)"
+ spacing allpoly allpoly 210 touching_ok "poly spacing < %d (poly.2)"
+
+ spacing allpolynonfet \
+ *ndiff,*mvndiff,*ndiode,*nndiode,ndiffres,*ndiodelvt,*pdiff,*mvpdiff,*pdiode,pdiffres,*pdiodelvt,*pdiodehvt \
+ 75 corner_ok allfets \
+ "poly spacing to Diffusion < %d (poly.4)"
+ spacing npres *nsd 480 touching_illegal \
+ "poly resistor spacing to N-tap < %d (poly.9)"
+ overhang *ndiff,rndiff nfet,scnfet,npd,npass 250 "N-Diffusion overhang of nFET < %d (poly.7)"
+ overhang *mvndiff,mvrndiff mvnfet,mvnnfet 250 \
+ "N-Diffusion overhang of nFET < %d (poly.7)"
+ overhang *pdiff,rpdiff pfet,scpfet,ppu 250 "P-Diffusion overhang of pmos < %d (poly.7)"
+ overhang *mvpdiff,mvrpdiff mvpfet 250 "P-Diffusion overhang of pmos < %d (poly.7)"
+ overhang *poly allfetsstd,allfetsspecial 130 "poly overhang of transistor < %d (poly.8)"
+ overhang *poly allfetscore 110 "poly overhang of SRAM core transistor < %d (poly.8)"
+ rect_only allfets "No bends in transistors (poly.11)"
+ rect_only xhrpoly,uhrpoly "No bends in poly resistors (poly.11)"
+ extend xpc/a xhrpoly,uhrpoly 2160 \
+ "poly contact extends poly resistor by < %d (licon.1c + li.5)"
+ spacing xhrpoly,uhrpoly,xpc xhrpoly,uhrpoly,xpc 1240 touching_illegal \
+ "Distance between precision resistors < %d (rpm.2 + 2 * rpm.3)"
+
+ spacing xhrpoly,uhrpoly,xpc allndifflv,allndiffmv 780 touching_illegal \
+ "Distance from precision resistor to N+ diffusion < %d (rpm.3 + rpm.6 + nsd.5a)"
+ spacing xhrpoly,uhrpoly,xpc *poly 400 touching_illegal \
+ "Distance from precision resistor to unrelated poly < %d (rpm.3 + rpm.7)"
+ spacing xhrpoly,uhrpoly,xpc allndiffmvnontap 830 touching_illegal \
+ "Distance from precision resistor to MV N+ diffusion < %d (rpm.3 + rpm.9)"
+
+ angles allpoly 90 "Only 90 degree angles permitted on poly (x.2)"
+
+#--------------------------------------------------------------------
+# HVTP
+#--------------------------------------------------------------------
+
+ spacing pfethvt,pdiodehvt,varactorhvt pfet,ppu,scpfet,mvpfet,pfetlvt,pfetmvt \
+ 360 touching_illegal \
+ "Min. spacing between pFET and HVTP < %d (hvtp.4)"
+
+ spacing pfethvt,pdiodehvt,varactorhvt varactor 360 touching_illegal \
+ "Min. spacing between varactor and HVTP < %d (hvtp.4 + varac.3)"
+
+#--------------------------------------------------------------------
+# LVTN
+#--------------------------------------------------------------------
+
+ spacing pfetlvt,nfetlvt,pdiodelvt,ndiodelvt \
+ allfetsnolvt 360 touching_illegal \
+ "Min. spacing between FET and LVTN < %d (lvtn.3a)"
+
+ spacing pfetlvt,nfetlvt,pdiodelvt,ndiodelvt scpfethvt,pfethvt,pdiodehvt,varactorhvt \
+ 740 touching_illegal \
+ "Min. spacing between LVTN and HVTP < %d (lvtn.9)"
+
+ # Spacing across S/D direction requires edge rule
+ edge4way allfetsnolvt allactivenonfet 415 \
+ ~(pfetlvt,nfetlvt,pdiodelvt,ndiodelvt)/a allfetsnolvt 415 \
+ "Min. spacing between FET and LVTN in S/D direction < %d (lvtn.3b)"
+
+#--------------------------------------------------------------------
+# NPC (Nitride poly Cut)
+#--------------------------------------------------------------------
+
+# Layer NPC is defined automatically around poly contacts (grow 0.1um)
+
+#--------------------------------------------------------------------
+# CONT (LICON, contact between poly/diff and LI)
+#--------------------------------------------------------------------
+
+ width ndc/li 170 "N-diffusion contact width < %d (licon.1)"
+ width nsc/li 170 "N-tap contact width < %d (licon.1)"
+ width pdc/li 170 "P-diffusion contact width < %d (licon.1)"
+ width psc/li 170 "P-tap contact width < %d (licon.1)"
+ width ndic/li 170 "N-diode contact width < %d (licon.1)"
+ width pdic/li 170 "P-diode contact width < %d (licon.1)"
+ width pc/li 170 "poly contact width < %d (licon.1)"
+
+ width xpc/li 350 "poly resistor contact width < %d (licon.1b + 2 * li.5)"
+ area xpc/li 700000 350 "poly resistor contact length < 2.0um (licon.1c)"
+ area allli,*obsli 56100 170 "Local interconnect minimum area < %a (li.6)"
+
+ width mvndc/li 170 "N-diffusion contact width < %d (licon.1)"
+ width mvnsc/li 170 "N-tap contact width < %d (licon.1)"
+ width mvpdc/li 170 "P-diffusion contact width < %d (licon.1)"
+ width mvpsc/li 170 "P-tap contact width < %d (licon.1)"
+ width mvndic/li 170 "N-diode contact width < %d (licon.1)"
+ width mvpdic/li 170 "P-diode contact width < %d (licon.1)"
+
+ spacing allpdiffcont allndiffcont 170 touching_illegal \
+ "Diffusion contact spacing < %d (licon.2)"
+ spacing allndiffcont allndiffcont 170 touching_ok \
+ "Diffusion contact spacing < %d (licon.2)"
+ spacing allpdiffcont allpdiffcont 170 touching_ok \
+ "Diffusion contact spacing < %d (licon.2)"
+ spacing pc pc 170 touching_ok "Poly1 contact spacing < %d (licon.2)"
+
+ spacing pc alldiff 190 touching_illegal \
+ "poly contact spacing to diffusion < %d (licon.14)"
+ spacing pc allpdifflv,allpdiffmv 235 touching_illegal \
+ "poly contact spacing to P-diffusion < %d (licon.9 + psdm.5a)"
+
+ spacing ndc,pdc nfet,nfetlvt,pfet,pfethvt,pfetlvt,pfetmvt 55 touching_illegal \
+ "Diffusion contact to gate < %d (licon.11)"
+ spacing ndc,pdc scnfet,scpfet,scpfethvt 50 touching_illegal \
+ "Diffusion contact to standard cell gate < %d (licon.11)"
+ spacing ndc,pdc npd,npass,ppu 40 touching_illegal \
+ "Diffusion contact to SRAM gate < %d (licon.11)"
+ spacing mvndc,mvpdc mvnfet,mvnnfet,mvpfet 55 touching_illegal \
+ "Diffusion contact to gate < %d (licon.11)"
+ spacing nsc varactor,varhvt 250 touching_illegal \
+ "Diffusion contact to varactor gate < %d (licon.10)"
+ spacing mvnsc mvvar 250 touching_illegal \
+ "Diffusion contact to varactor gate < %d (licon.10)"
+
+ surround ndc/a *ndiff,nfet,scnfet,npd,npass,nfetlvt,rnd 40 absence_illegal \
+ "N-diffusion overlap of N-diffusion contact < %d (licon.5a)"
+ surround pdc/a *pdiff,pfet,scpfet,scpfethvt,ppu,pfethvt,pfetmvt,pfetlvt,rpd \
+ 40 absence_illegal \
+ "P-diffusion overlap of P-diffusion contact < %d (licon.5a)"
+ surround ndic/a *ndi 40 absence_illegal \
+ "N-diode overlap of N-diode contact < %d (licon.5a)"
+ surround pdic/a *pdi 40 absence_illegal \
+ "P-diode overlap of N-diode contact < %d (licon.5a)"
+
+ spacing psc/a allnactivenontap 60 touching_illegal \
+ "Min. space between P-tap contact and butting N diffusion < %d (licon.5b)"
+ spacing nsc/a allpactivenontap 60 touching_illegal \
+ "Min. space between N-tap contact and butting P diffusion < %d (licon.5b)"
+
+ surround ndc/a *ndiff,nfet,scnfet,npd,npass,nfetlvt,rnd 60 directional \
+ "N-diffusion overlap of N-diffusion contact < %d in one direction (licon.5c)"
+ surround pdc/a *pdiff,pfet,scpfet,scpfethvt,ppu,pfethvt,pfetmvt,pfetlvt,rpd \
+ 60 directional \
+ "P-diffusion overlap of P-diffusion contact < %d in one direction (licon.5c)"
+ surround ndic/a *ndi 60 directional \
+ "N-diode overlap of N-diode contact < %d in one direction (licon.5c)"
+ surround pdic/a *pdi 60 directional \
+ "P-diode overlap of N-diode contact < %d in one direction (licon.5c)"
+
+ surround nsc/a *nsd 120 directional \
+ "N-tap overlap of N-tap contact < %d in one direction (licon.7)"
+ surround psc/a *psd 120 directional \
+ "P-tap overlap of P-tap contact < %d in one direction (licon.7)"
+
+ surround mvndc/a *mvndiff,mvnfet,mvrnd 40 absence_illegal \
+ "N-diffusion overlap of N-diffusion contact < %d (licon.5a)"
+ surround mvpdc/a *mvpdiff,mvpfet,mvrpd 40 absence_illegal \
+ "P-diffusion overlap of P-diffusion contact < %d (licon.5a)"
+ surround mvndic/a *mvndi 40 absence_illegal \
+ "N-diode overlap of N-diode contact < %d (licon.5a)"
+ surround mvpdic/a *mvpdi 40 absence_illegal \
+ "P-diode overlap of N-diode contact < %d (licon.5a)"
+
+ spacing mvpsc/a allndiffmvnontap 60 touching_illegal \
+ "Min. space between P-tap contact and butting N diffusion < %d (licon.5b)"
+ spacing mvnsc/a allpdiffmvnontap 60 touching_illegal \
+ "Min. space between N-tap contact and butting P diffusion < %d (licon.5b)"
+
+ surround mvndc/a *mvndiff,mvnfet,mvrnd 60 directional \
+ "N-diffusion overlap of N-diffusion contact < %d in one direction (licon.5c)"
+ surround mvpdc/a *mvpdiff,mvpfet,mvrpd 60 directional \
+ "P-diffusion overlap of P-diffusion contact < %d in one direction (licon.5c)"
+ surround mvndic/a *mvndi 60 directional \
+ "N-diode overlap of N-diode contact < %d in one direction (licon.5c)"
+ surround mvpdic/a *mvpdi 60 directional \
+ "P-diode overlap of N-diode contact < %d in one direction (licon.5c)"
+
+ surround mvnsc/a *mvnsd 120 directional \
+ "N-tap overlap of N-tap contact < %d in one direction (licon.7)"
+ surround mvpsc/a *mvpsd 120 directional \
+ "P-tap overlap of P-tap contact < %d in one direction (licon.7)"
+
+ surround pc/a *poly,mrp1,xhrpoly,uhrpoly 50 absence_illegal \
+ "poly overlap of poly contact < %d (licon.8)"
+ surround pc/a *poly,mrp1,xhrpoly,uhrpoly 80 directional \
+ "poly overlap of poly contact < %d in one direction (licon.8a)"
+
+ exact_overlap (allcont)/a
+
+#-------------------------------------------------------------
+# LI - Local interconnect layer
+#-------------------------------------------------------------
+
+variants *
+
+ width *li 170 "Local interconnect width < %d (li.1)"
+ width rli 290 "Local interconnect width < %d (li.7)"
+
+ spacing *locali,rli *locali,rli,*obsli 170 touching_ok \
+ "Local interconnect spacing < %d (li.3)"
+
+ # Local interconnect in core (SRAM) cells has more relaxed rules. There are
+ # no special layers for the contacts in core cells, so they must be included
+ # in the rule.
+ width coreli,pc,ndc,nsc,pdc,psc,allli,*obsli 140 \
+ "Core local interconnect width < %d (li.c1)"
+
+ spacing coreli,pc,ndc,nsc,pdc,psc,lic allli,*obsli 140 touching_ok \
+ "Core local interconnect spacing < %d (li.c2)"
+
+ surround pc/li *li,coreli 80 directional \
+ "Local interconnect overlap of poly contact < %d in one direction (li.5)"
+
+ surround ndc/li,nsc/li,pdc/li,psc/li,ndic/li,pdic/li,mvndc/li,mvnsc/li,mvpdc/li,mvpsc/li,mvndic/li,mvpdic/li \
+ *li,rli,coreli 80 directional \
+ "Local interconnect overlap of diffusion contact < %d in one direction (li.5)"
+
+ area allli,*obsli,coreli 56100 170 "Local interconnect minimum area < %a (li.6)"
+
+ angles *locali,rli 90 "Only 90 degree angles permitted on local interconnect (x.2)"
+ angles coreli 45 \
+ "Only 45 degree angles permitted on local interconnect in SRAM cell (x.2)"
+
+#-------------------------------------------------------------
+# MCON - Contact between local interconnect and metal1
+#-------------------------------------------------------------
+
+ width lic/m1 170 "mcon.width < %d (mcon.1)"
+ spacing lic/m1 lic/m1,obslic/m1 190 touching_ok "mcon.spacing < %d (mcon.2)"
+
+ exact_overlap lic/li
+
+#-------------------------------------------------------------
+# METAL1 -
+#-------------------------------------------------------------
+
+ width *m1,rm1 140 "Metal1 width < %d (met1.1)"
+ spacing allm1 allm1,*obsm1 140 touching_ok "Metal1 spacing < %d (met1.2)"
+ area allm1,*obsm1 83000 140 "Metal1 minimum area < %a (met1.6)"
+
+ surround lic/m1 *met1 30 absence_illegal \
+ "Metal1 overlap of local interconnect contact < %d (met1.4)"
+ surround lic/m1 *met1 60 directional \
+ "Metal1 overlap of local interconnect contact < %d in one direction (met1.5)"
+
+ angles allm1 45 "Only 45 and 90 degree angles permitted on metal1 (x.3a)"
+
+variants (fast),(full)
+ widespacing allm1 3000 allm1,*obsm1 280 touching_ok \
+ "Metal1 > 3um spacing to unrelated m1 < %d (met1.3b)"
+ widespacing *obsm1 3000 allm1 280 touching_ok \
+ "Metal1 > 3um spacing to unrelated m1 < %d (met1.3b)"
+
+variants (full)
+ cifmaxwidth m1_hole_empty 0 bend_illegal \
+ "Min area of metal1 holes > 0.14um^2 (met1.7)"
+
+ cifspacing m1_large_halo m1_large_halo 280 touching_ok \
+ "Spacing of metal1 features attached to and within 0.28um of large metal1 < %d (met1.3a)"
+variants *
+
+#--------------------------------------------------
+# VIA1
+#--------------------------------------------------
+
+ width v1/m1 260 "Via1 width < %d (via.1a + 2 * via.4a)"
+ spacing v1 v1 60 touching_ok "Via1 spacing < %d (via.2 - 2 * via.4a)"
+ surround v1/m1 *m1 30 directional \
+ "Metal1 overlap of Via1 < %d in one direction (via.5a - via.4a)"
+ surround v1/m2 *m2 30 directional \
+ "Metal2 overlap of Via1 < %d in one direction (met2.5 - met2.4)"
+
+ exact_overlap v1/m1
+
+#--------------------------------------------------
+# METAL2 -
+#--------------------------------------------------
+
+ width allm2 140 "Metal2 width < %d (met2.1)"
+ spacing allm2 allm2,obsm2 140 touching_ok "Metal2 spacing < %d (met2.2)"
+ area allm2,obsm2 67600 140 "Metal2 minimum area < %a (met2.6)"
+
+ angles allm2 45 "Only 45 and 90 degree angles permitted on metal2 (x.3a)"
+
+variants (fast),(full)
+ widespacing allm2 3000 allm2,obsm2 280 touching_ok \
+ "Metal2 > 3um spacing to unrelated m2 < %d (met2.3b)"
+ widespacing obsm2 3000 allm2 280 touching_ok \
+ "Metal2 > 3um spacing to unrelated m2 < %d (met2.3b)"
+
+variants (full)
+ cifmaxwidth m2_hole_empty 0 bend_illegal \
+ "Min area of metal2 holes > 0.14um^2 (met2.7)"
+
+ cifspacing m2_large_halo m2_large_halo 280 touching_ok \
+ "Spacing of metal2 features attached to and within 0.28um of large metal2 < %d (met2.3a)"
+variants *
+
+#--------------------------------------------------
+# VIA2
+#--------------------------------------------------
+
+ width v2/m2 280 "via2.width < %d (via2.1a + 2 * via2.4)"
+
+ spacing v2 v2 120 touching_ok "via2.spacing < 0.24um (via2.2 - 2 * via2.4)"
+
+ surround v2/m2 *m2 45 directional \
+ "Metal2 overlap of via2.< %d in one direction (via2.4a - via2.4)"
+ surround v2/m3 *m3 25 absence_illegal "Metal3 overlap of via2.< %d (met3.4)"
+
+ exact_overlap v2/m2
+
+#--------------------------------------------------
+# METAL3 -
+#--------------------------------------------------
+
+ width allm3 300 "Metal3 width < %d (met3.1)"
+ spacing allm3 allm3,obsm3 300 touching_ok "Metal3 spacing < %d (met3.2)"
+ area allm3,obsm3 240000 300 "Metal3 minimum area < %a (met3.6)"
+
+ angles allm3 45 "Only 45 and 90 degree angles permitted on metal3 (x.3a)"
+
+variants (fast),(full)
+ widespacing allm3 3000 allm3,obsm3 400 touching_ok \
+ "Metal3 > 3um spacing to unrelated m3 < %d (met3.3d)"
+ widespacing obsm3 3000 allm3 400 touching_ok \
+ "Metal3 > 3um spacing to unrelated m3 < %d (met3.3d)"
+variants (full)
+ cifspacing m3_large_halo m3_large_halo 400 touching_ok \
+ "Spacing of metal3 features attached to and within 0.40um of large metal3 < %d (met3.3c)"
+variants *
+
+
+#--------------------------------------------------
+# VIA3 - Requires METAL5 Module
+#--------------------------------------------------
+
+ width v3/m3 320 "via3.width < %d (via3.1 + 2 * via3.4)"
+ spacing v3 v3 80 touching_ok "via3.spacing < %d (via3.2 - 2 * via3.4)"
+ surround v3/m3 *m3 30 directional \
+ "Metal3 overlap of via3.in one direction < %d (via3.5 - via3.4)"
+ surround v3/m4 *m4 5 absence_illegal \
+ "Metal4 overlap of via3.< %d (met4.3 - via3.4)"
+
+ exact_overlap v3/m3
+
+#-----------------------------
+# METAL4 - METAL4 Module
+#-----------------------------
+
+variants *
+
+ width allm4 300 "Metal4 width < %d (met4.1)"
+ spacing allm4 allm4,obsm4 300 touching_ok "Metal4 spacing < %d (met4.2)"
+ area allm4,obsm4 240000 300 "Metal4 minimum area < %a (met4.4a)"
+
+ angles allm4 45 "Only 45 and 90 degree angles permitted on metal4 (x.3a)"
+
+variants (fast),(full)
+ widespacing allm4 3000 allm4,obsm4 400 touching_ok \
+ "Metal4 > 3um spacing to unrelated m4 < %d (met4.5b)"
+ widespacing obsm4 3000 allm4 400 touching_ok \
+ "Metal4 > 3um spacing to unrelated m4 < %d (met4.5b)"
+variants (full)
+ cifspacing m4_large_halo m4_large_halo 400 touching_ok \
+ "Spacing of metal4 features attached to and within 0.40um of large metal4 < %d (met4.5a)"
+variants *
+
+#--------------------------------------------------
+# VIA4 - Requires METAL5 Module
+#--------------------------------------------------
+
+ width v4/m4 1180 "via4.width < %d (via4.1 + 2 * via4.4)"
+ spacing v4 v4 420 touching_ok "via4.spacing < %d (via4.2 - 2 * via4.4)"
+ surround v4/m5 *m5 120 absence_illegal \
+ "Metal5 overlap of via4.< %d (met5.3 - via4.4)"
+
+ exact_overlap v4/m4
+
+#-----------------------------
+# METAL5 - METAL5 Module
+#-----------------------------
+
+ width allm5 1600 "Metal5 width < %d (met5.1)"
+ spacing allm5 allm5,obsm5 1600 touching_ok "Metal5 spacing < %d (met5.2)"
+ area allm5,obsm5 4000000 1600 "Metal5 minimum area < %a (met5.4)"
+
+ angles allm5 45 "Only 45 and 90 degree angles permitted on metal5 (x.3a)"
+
+
+
+variants (full)
+
+ width metrdl 10000 "RDL width < %d (rdl.1)"
+ spacing metrdl metrdl 10000 touching_ok "RDL spacing < %d (rdl.2)"
+ surround glass metrdl 10750 absence_ok "RDL must surround glass cut by %d (rdl.3)"
+ spacing metrdl padl 19660 surround_ok "RDL spacing to unrelated pad < %d (rdl.6)"
+
+variants (fast),(full)
+
+
+#--------------------------------------------------
+# NMOS, PMOS
+#--------------------------------------------------
+
+ edge4way *poly allfetsstd 420 allfets 0 0 \
+ "Transistor width < %d (diff/tap.2)"
+ edge4way *poly allfetsspecial 360 allfets 0 0 \
+ "Transistor in standard cell width < %d (diff/tap.2)"
+ edge4way *poly npass,npd,nsonos 210 allfets 0 0 \
+ "N-Transistor in SRAM core width < %d (diff/tap.2)"
+ edge4way *poly ppu 140 allfets 0 0 \
+ "P-Transistor in SRAM core width < %d (diff/tap.2)"
+
+ # Except: Note that standard cells allow transistor width minimum 0.36um
+ width pfetlvt 350 "LVT PMOS gate length < %d (poly.1b)"
+
+ spacing allpolynonfet *nsd 55 corner_ok varactor \
+ "poly spacing to diffusion tap < %d (poly.5)"
+ spacing allpolynonfet *mvnsd 55 corner_ok mvvaractor \
+ "poly spacing to diffusion tap < %d (poly.5)"
+
+ edge4way *psd *ndiff 300 ~(nfet,npass,npd,scnfet,nfetlvt,nsonos)/a *psd 300 \
+ "Butting P-tap spacing to NMOS gate < %d (poly.6)"
+ edge4way *nsd *pdiff 300 ~(pfet,ppu,scpfet,scpfethvt,pfetlvt,pfetmvt)/a *nsd 300 \
+ "Butting N-tap spacing to PMOS gate < %d (poly.6)"
+ edge4way *mvpsd *mvndiff 300 ~(mvnfet,mvnnfet)/a *mvpsd 300 \
+ "Butting MV P-tap spacing to MV NMOS gate < %d (poly.6)"
+ edge4way *mvnsd *mvpdiff 300 ~mvpfet/a *mvnsd 300 \
+ "Butting MV N-tap spacing to MV PMOS gate < %d (poly.6)"
+
+ # No LV FETs in HV diff
+ spacing pfet,scpfet,scpfethvt,ppu,pfetlvt,pfetmvt,pfethvt,*pdiff *mvpdiff 360 touching_illegal \
+ "LV P-diffusion to MV P-diffusion < %d (diff/tap.23 + diff/tap.22)"
+
+ spacing nfet,scnfet,npd,npass,nfetlvt,varactor,varhvt,*ndiff *mvndiff 360 touching_illegal \
+ "LV N-diffusion to MV N-diffusion < %d (diff/tap.23 + diff/tap.22)"
+
+ # No HV FETs in LV diff
+ spacing mvpfet,*mvpdiff *pdiff 360 touching_illegal \
+ "MV P-diffusion to LV P-diffusion < %d (diff/tap.23 + diff/tap.22)"
+
+ spacing mvnfet,mvvaractor,*mvndiff *ndiff 360 touching_illegal \
+ "MV N-diffusion to LV N-diffusion < %d (diff/tap.23 + diff/tap.22)"
+
+ # Minimum length of MV FETs. Note that this is larger than the minimum
+ # width (0.29um), so an edge rule is required
+
+ edge4way mvndiff mvnfet 500 mvnfet 0 0 \
+ "MV NMOS minimum length < %d (poly.13)"
+
+ edge4way mvnsd mvvaractor 500 mvvaractor 0 0 \
+ "MV Varactor minimum length < %d (poly.13)"
+
+ edge4way mvpdiff mvpfet 500 mvpfet 0 0 \
+ "MV PMOS minimum length < %d (poly.13)"
+
+#--------------------------------------------------
+# mrp1 (N+ poly resistor)
+#--------------------------------------------------
+
+ width mrp1 330 "mrp1 resistor width < %d (poly.3)"
+
+#--------------------------------------------------
+# xhrpoly (P+ poly resistor)
+# uhrpoly (P+ poly resistor, 2kOhm/sq)
+#--------------------------------------------------
+
+ # NOTE: u/xhrpoly resistor requires discrete widths 0.35, 0.69, ... up to 1.27.
+ width xhrpoly 350 "xhrpoly resistor width < %d (P+ poly.1a)"
+ width uhrpoly 350 "uhrpoly resistor width < %d (P+ poly.1a)"
+
+ spacing xhrpoly,uhrpoly,xpc alldiff 480 touching_illegal \
+ "xhrpoly/uhrpoly resistor spacing to diffusion < %d (poly.9)"
+
+ spacing mrp1,xhrpoly,uhrpoly,xpc allfets 480 touching_illegal \
+ "Poly resistor spacing to poly < %d (poly.9)"
+
+ spacing xhrpoly,uhrpoly,xpc *poly 480 touching_illegal \
+ "Poly resistor spacing to poly < %d (poly.9)"
+
+ spacing mrp1 *poly 480 touching_ok \
+ "Poly resistor spacing to poly < %d (poly.9)"
+
+ spacing mrp1,xhrpoly,uhrpoly,xpc alldiff 480 touching_illegal \
+ "Poly resistor spacing to diffusion < %d (poly.9)"
+
+#------------------------------------
+# nsonos
+#------------------------------------
+
+variants (full)
+ cifmaxwidth bbox_missing 0 bend_illegal \
+ "SONOS transistor must be in cell with abutment box (tunm.8)"
+variants (fast),(full)
+
+#------------------------------------
+# MOS Varactor device rules
+#------------------------------------
+
+ overhang *nsd var,varhvt 250 \
+ "N-Tap overhang of Varactor < %d (var.4)"
+
+ overhang *mvnsd mvvar 250 \
+ "N-Tap overhang of Varactor < %d (var.4)"
+
+ width var,varhvt,mvvar 180 "Varactor length < %d (var.1)"
+ extend var,varhvt,mvvar *poly 1000 "Varactor width < %d (var.2)"
+
+variants (full)
+ cifmaxwidth var_poly_no_nwell 0 bend_illegal \
+ "N-well overlap of varactor poly < 0.15um (varac.5)"
+
+ cifmaxwidth pdiff_in_varactor_well 0 bend_illegal \
+ "Varactor N-well must not contain P+ diffusion (varac.7)"
+variants (fast),(full)
+
+#-----------------------------------------------------------
+# MiM CAP (CAPM) -
+#-----------------------------------------------------------
+
+ width *mimcap 1000 "MiM cap width < %d (capm.1)"
+ spacing *mimcap *mimcap 840 touching_ok "MiM cap spacing < %d (capm.2a)"
+ spacing *mimcap via3/m3 80 touching_illegal \
+ "MiM cap spacing to via3 < %d (capm.5 - via3.4)"
+ surround *mimcc *mimcap 80 absence_illegal \
+ "MiM cap must surround MiM cap contact by %d (capm.4 - via3.4)"
+ rect_only *mimcap "MiM cap must be rectangular (capm.7)
+
+ surround *mimcap *metal3/m3 140 absence_illegal \
+ "Metal3 must surround MiM cap by %d (capm.3)"
+ spacing via2 *mimcap 100 touching_illegal \
+ "MiM cap spacing to via2 < %d (capm.8 - via2.4)"
+ spacing *mimcap *metal3/m3 500 surround_ok \
+ "MiM cap spacing to unrelated metal3 < %d (capm.11)"
+
+variants (full)
+ cifspacing mim_bottom mim_bottom 1200 touching_ok \
+ "MiM cap bottom plate spacing < %d (capm.2b)"
+variants (fast),(full)
+
+ # MiM cap contact rules (VIA3)
+
+ width mimcc/c1 320 "MiM cap contact width < %d (via3.1 + 2 * via3.4)"
+ spacing mimcc mimcc 80 touching_ok "MiM cap contact spacing < %d (via3.2 - 2 * via3.4)"
+ surround mimcc/m4 *m4 5 directional \
+ "Metal4 overlap of MiM cap contact in one direction < %d (met4.3 - via3.4)"
+ exact_overlap mimcc/c1
+
+ width *mimcap2 1000 "MiM2 cap width < %d (cap2m.1)"
+ spacing *mimcap2 *mimcap2 840 touching_ok "MiM2 cap spacing < %d (cap2m.2a)"
+ spacing *mimcap2 via4/m4 10 touching_illegal \
+ "MiM2 cap spacing to via4 < %d (cap2m.5 - via4.4)"
+ surround *mim2cc *mimcap2 10 absence_illegal \
+ "MiM2 cap must surround MiM cap 2 contact by %d (cap2m.4 - via4.4)"
+ rect_only *mimcap2 "MiM2 cap must be rectangular (cap2m.7)
+
+ surround *mimcap2 *metal4/m4 140 absence_illegal \
+ "Metal4 must surround MiM2 cap by %d (cap2m.3)"
+ spacing via3,mimcc *mimcap2 80 touching_illegal \
+ "MiM2 cap spacing to via3 < %d (cap2m.8 - via3.4)"
+ spacing *mimcap2 *metal4/m4 500 surround_ok \
+ "MiM2 cap spacing to unrelated metal4 < %d (cap2m.11)"
+
+variants (full)
+ cifspacing mim2_bottom mim2_bottom 1200 touching_ok \
+ "MiM2 cap bottom plate spacing < %d (cap2m.2b)"
+variants (fast),(full)
+
+ # MiM cap contact rules (VIA4)
+
+ width mim2cc/c2 1180 "MiM2 cap contact width < %d (via4.1 + 2 * via4.4)"
+ spacing mim2cc mim2cc 420 touching_ok \
+ "MiM2 cap contact spacing < %d (via4.2 - 2 * via4.4)"
+ surround mim2cc/m5 *m5 120 absence_illegal \
+ "Metal5 overlap of MiM2 cap contact < %d (met5.3 - via4.4)"
+ exact_overlap mim2cc/c2
+
+
+#----------------------------
+# HVNTM
+#----------------------------
+variants (full)
+ cifspacing hvntm_generate hvntm_generate 700 touching_ok \
+ "HVNTM spacing < %d (hvntm.2)"
+variants (fast),(full)
+
+#----------------------------
+# End DRC style
+#----------------------------
+
+end
+
+#----------------------------
+# LEF format definitions
+#----------------------------
+
+lef
+
+ masterslice pwell pwell PWELL substrate
+ masterslice nwell nwell NWELL
+
+ routing li li1 LI1 LI li
+
+ routing m1 met1 MET1 m1
+ routing m2 met2 MET2 m2
+ routing m3 met3 MET3 m3
+ routing m4 met4 MET4 m4
+ routing m5 met5 MET5 m5
+ routing mrdl met6 MET6 m6 MRDL METRDL
+
+ cut lic mcon MCON Mcon
+ cut m2c via via1 VIA VIA1 cont2 via12
+ cut m3c via2 VIA2 cont3 via23
+ cut via3 via3 VIA3 cont4 via34
+ cut via4 via4 VIA4 cont5 via45
+
+ obs obsli li1
+ obs obsm1 met1
+ obs obsm2 met2
+ obs obsm3 met3
+
+ obs obsm4 met4
+ obs obsm5 met5
+ obs obsmrdl met6
+
+ # NOTE: obslic only used with li1, not obsli.
+ obs obslic mcon
+
+ # Vias on obstruction layers should be ignored, so cast to obstruction metal.
+ obs obsm1 via
+ obs obsm2 via2
+ obs obsm3 via3
+ obs obsm4 via4
+
+end
+
+#-----------------------------------------------------
+# Device and Parasitic extraction
+#-----------------------------------------------------
+
+
+extract
+ style ngspice variants (),(orig),(si)
+ cscale 1
+ # NOTE: SkyWater SPICE libraries use .option scale 1E6 so all
+ # dimensions must be in units of microns in the extract file.
+ # Use extract style "ngspice(si)" to override this and produce
+ # a file with SI units for length/area.
+
+ variants (),(orig)
+ lambda 1E6
+ variants (si)
+ lambda 1.0
+ variants *
+
+ units microns
+ step 7
+ sidehalo 2
+
+ # NOTE: MiM cap layers have been purposely put out of order,
+ # may want to reconsider.
+
+ planeorder dwell 0
+ planeorder well 1
+ planeorder active 2
+ planeorder locali 3
+ planeorder metal1 4
+ planeorder metal2 5
+ planeorder metal3 6
+ planeorder metal4 7
+ planeorder metal5 8
+ planeorder metali 9
+ planeorder block 10
+ planeorder comment 11
+ planeorder cap1 12
+ planeorder cap2 13
+
+ height dnwell -0.1 0.1
+ height nwell,pwell 0.0 0.2062
+ height alldiff 0.2062 0.12
+ height allpoly 0.3262 0.18
+ height alldiffcont 0.3262 0.61
+ height pc 0.5062 0.43
+ height allli 0.9361 0.10
+ height lic 1.0361 0.34
+ height allm1 1.3761 0.36
+ height v1 1.7361 0.27
+ height allm2 2.0061 0.36
+ height v2 2.3661 0.42
+ height allm3 2.7861 0.845
+ height v3 3.6311 0.39
+ height allm4 4.0211 0.845
+ height v4 4.8661 0.505
+ height allm5 5.3711 1.26
+ height mimcap 2.4661 0.2
+ height mimcap2 3.7311 0.2
+ height mimcc 2.6661 0.12
+ height mim2cc 3.9311 0.09
+ height mrdlc 6.6311 5.2523
+ height mrdl 11.8834 4.0
+
+ # Antenna check parameters
+ # Note that checks w/diode diffusion are not modeled
+ model partial
+ antenna poly sidewall 50 none
+ antenna allcont surface 3 none
+ antenna li sidewall 75 0 450
+ antenna lic surface 3 0 18
+ antenna m1,m2,m3 sidewall 400 2600 400
+ antenna v1 surface 3 0 18
+ antenna v2 surface 6 0 36
+ antenna m4,m5 sidewall 400 2600 400
+ antenna v3,v4 surface 6 0 36
+
+ tiedown alldiffnonfet
+
+ substrate *ppdiff,*mvppdiff,space/w,pwell well $SUB -dnwell
+
+# Layer resistance: Use document xp018-PDS-v4_2_1.pdf
+
+# Resistances are in milliohms per square
+# Optional 3rd argument is the corner adjustment fraction
+# Device values come from trtc.cor (typical corner)
+ resist (dnwell)/dwell 2200000
+ resist (pwell)/well 3050000
+ resist (nwell)/well 1700000
+ resist (rpw)/well 3050000 0.5
+ resist (*ndiff,nsd)/active 120000
+ resist (*pdiff,*psd)/active 197000
+ resist (*mvndiff,mvnsd)/active 114000
+ resist (*mvpdiff,*mvpsd)/active 191000
+
+ resist ndiffres/active 120000 0.5
+ resist pdiffres/active 197000 0.5
+ resist mvndiffres/active 114000 0.5
+ resist mvpdiffres/active 191000 0.5
+ resist mrp1/active 48200 0.5
+ resist xhrpoly/active 319800 0.5
+ resist uhrpoly/active 2000000 0.5
+
+ resist (allpolynonres)/active 48200
+ resist rmp/active 48200
+
+ resist (allli)/locali 12200
+ resist (allm1)/metal1 125
+ resist (allm2)/metal2 125
+ resist (allm3)/metal3 47
+ resist (allm4)/metal4 47
+ resist (allm5)/metal5 29
+ resist mrdl/metali 5
+
+ contact ndc,nsc 15000
+ contact pdc,psc 15000
+ contact mvndc,mvnsc 15000
+ contact mvpdc,mvpsc 15000
+ contact pc 15000
+ contact lic 152000
+ contact m2c 4500
+ contact m3c 3410
+ contact mimcc 4500
+ contact mim2cc 3410
+ contact via3 3410
+ contact via4 380
+ contact mrdlc 6
+
+#-------------------------------------------------------------------------
+# Parasitic capacitance values: Use document (...)
+#-------------------------------------------------------------------------
+# This uses the new "default" definitions that determine the intervening
+# planes from the planeorder stack, take care of the reflexive sideoverlap
+# definitions, and generally clean up the section and make it more readable.
+#
+# Also uses "units microns" statement. All values are taken from the
+# document PEX/xRC/cap_models. Fringe capacitance values are approximated.
+# Units are aF/um^2 for area caps and aF/um for perimeter and sidewall caps.
+#-------------------------------------------------------------------------
+# Remember that device capacitances to substrate are taken care of by the
+# models. Thus, active and poly definitions ignore all "fet" types.
+# fet types are excluded when computing parasitic capacitance to
+# active from layers above them because poly is a shield; fet types are
+# included for parasitics from layers above to poly. Resistor types
+# should be removed from all parasitic capacitance calculations, or else
+# they just create floating caps. Technically, the capacitance probably
+# should be split between the two terminals. Unsure of the correct model.
+#-------------------------------------------------------------------------
+
+#n-well
+# NOTE: This value not found in PEX files
+defaultareacap nwell well 120
+
+#n-active
+# Rely on device models to capture *ndiff area cap
+# Do not extract parasitics from resistors
+# defaultareacap allnactivenonfet active 790
+# defaultperimeter allnactivenonfet active 280
+
+#p-active
+# Rely on device models to capture *pdiff area cap
+# Do not extract parasitics from resistors
+# defaultareacap allpactivenonfet active 810
+# defaultperimeter allpactivenonfet active 300
+
+#poly
+# Do not extract parasitics from resistors
+# defaultsidewall allpolynonfet active 22
+# defaultareacap allpolynonfet active 106
+# defaultperimeter allpolynonfet active 57
+
+ defaultsidewall *poly active 23
+ defaultareacap *poly active nwell,obswell,pwell well 106
+ defaultperimeter *poly active nwell,obswell,pwell well 55
+
+#locali
+ defaultsidewall allli locali 33
+ defaultareacap allli locali nwell,obswell,pwell well 37
+ defaultperimeter allli locali nwell,obswell,pwell well 55
+ defaultoverlap allli locali nwell well 37
+
+#locali->diff
+ defaultoverlap allli locali allactivenonfet active 37
+ defaultsideoverlap allli locali allactivenonfet active 55
+
+#locali->poly
+ defaultoverlap allli locali allpolynonres active 94
+ defaultsideoverlap allli locali allpolynonres active 52
+ defaultsideoverlap *poly active allli locali 25
+
+#metal1
+ defaultsidewall allm1 metal1 45
+ defaultareacap allm1 metal1 nwell,obswell,pwell well 26
+ defaultperimeter allm1 metal1 nwell,obswell,pwell well 41
+ defaultoverlap allm1 metal1 nwell well 26
+
+#metal1->diff
+ defaultoverlap allm1 metal1 allactivenonfet active 26
+ defaultsideoverlap allm1 metal1 allactivenonfet active 41
+
+#metal1->poly
+ defaultoverlap allm1 metal1 allpolynonres active 45
+ defaultsideoverlap allm1 metal1 allpolynonres active 47
+ defaultsideoverlap *poly active allm1 metal1 17
+
+#metal1->locali
+ defaultoverlap allm1 metal1 allli locali 114
+ defaultsideoverlap allm1 metal1 allli locali 59
+ defaultsideoverlap allli locali allm1 metal1 35
+
+#metal2
+ defaultsidewall allm2 metal2 50
+ defaultareacap allm2 metal2 nwell,obswell,pwell well 17
+ defaultperimeter allm2 metal2 nwell,obswell,pwell well 41
+ defaultoverlap allm2 metal2 nwell well 38
+
+#metal2->diff
+ defaultoverlap allm2 metal2 allactivenonfet active 17
+ defaultsideoverlap allm2 metal2 allactivenonfet active 41
+
+#metal2->poly
+ defaultoverlap allm2 metal2 allpolynonres active 24
+ defaultsideoverlap allm2 metal2 allpolynonres active 41
+ defaultsideoverlap *poly active allm2 metal2 11
+
+#metal2->locali
+ defaultoverlap allm2 metal2 allli locali 38
+ defaultsideoverlap allm2 metal2 allli locali 46
+ defaultsideoverlap allli locali allm2 metal2 22
+
+#metal2->metal1
+ defaultoverlap allm2 metal2 allm1 metal1 134
+ defaultsideoverlap allm2 metal2 allm1 metal1 67
+ defaultsideoverlap allm1 metal1 allm2 metal2 48
+
+#metal3
+ defaultsidewall allm3 metal3 63
+ defaultoverlap allm3 metal3 nwell well 12
+ defaultareacap allm3 metal3 nwell,obswell,pwell well 12
+ defaultperimeter allm3 metal3 nwell,obswell,pwell well 41
+
+#metal3->diff
+ defaultoverlap allm3 metal3 allactive active 12
+ defaultsideoverlap allm3 metal3 allactive active 41
+
+#metal3->poly
+ defaultoverlap allm3 metal3 allpolynonres active 16
+ defaultsideoverlap allm3 metal3 allpolynonres active 44
+ defaultsideoverlap *poly active allm3 metal3 9
+
+#metal3->locali
+ defaultoverlap allm3 metal3 allli locali 21
+ defaultsideoverlap allm3 metal3 allli locali 47
+ defaultsideoverlap allli locali allm3 metal3 15
+
+#metal3->metal1
+ defaultoverlap allm3 metal3 allm1 metal1 35
+ defaultsideoverlap allm3 metal3 allm1 metal1 55
+ defaultsideoverlap allm1 metal1 allm3 metal3 27
+
+#metal3->metal2
+ defaultoverlap allm3 metal3 allm2 metal2 86
+ defaultsideoverlap allm3 metal3 allm2 metal2 70
+ defaultsideoverlap allm2 metal2 allm3 metal3 44
+
+#metal4
+ defaultsidewall allm4 metal4 67
+# defaultareacap alltopm metal4 well 6
+ areacap allm4/m4 8
+ defaultoverlap allm4 metal4 nwell well 8
+ defaultperimeter allm4 metal4 well 37
+
+#metal4->diff
+ defaultoverlap allm4 metal4 allactivenonfet active 8
+ defaultsideoverlap allm4 metal4 allactivenonfet active 37
+
+#metal4->poly
+ defaultoverlap allm4 metal4 allpolynonres active 10
+ defaultsideoverlap allm4 metal4 allpolynonres active 38
+ defaultsideoverlap *poly active allm4 metal4 6
+
+#metal4->locali
+ defaultoverlap allm4 metal4 allli locali 12
+ defaultsideoverlap allm4 metal4 allli locali 40
+ defaultsideoverlap allli locali allm4 metal4 10
+
+#metal4->metal1
+ defaultoverlap allm4 metal4 allm1 metal1 15
+ defaultsideoverlap allm4 metal4 allm1 metal1 43
+ defaultsideoverlap allm1 metal1 allm4 metal4 16
+
+#metal4->metal2
+ defaultoverlap allm4 metal4 allm2 metal2 20
+ defaultsideoverlap allm4 metal4 allm2 metal2 46
+ defaultsideoverlap allm2 metal2 allm4 metal4 22
+
+#metal4->metal3
+ defaultoverlap allm4 metal4 allm3 metal3 84
+ defaultsideoverlap allm4 metal4 allm3 metal3 71
+ defaultsideoverlap allm3 metal3 allm4 metal4 43
+
+#metal5
+ defaultsidewall allm5 metal5 127
+# defaultareacap allm5 metal5 well 6
+ areacap allm5/m5 6
+ defaultoverlap allm5 metal5 nwell well 6
+ defaultperimeter allm5 metal5 well 39
+
+#metal5->diff
+ defaultoverlap allm5 metal5 allactivenonfet active 6
+ defaultsideoverlap allm5 metal5 allactivenonfet active 39
+
+#metal5->poly
+ defaultoverlap allm5 metal5 allpolynonres active 7
+ defaultsideoverlap allm5 metal5 allpolynonres active 40
+ defaultsideoverlap *poly active allm5 metal5 6
+
+#metal5->locali
+ defaultoverlap allm5 metal5 allli locali 8
+ defaultsideoverlap allm5 metal5 allli locali 41
+ defaultsideoverlap allli locali allm5 metal5 8
+
+#metal5->metal1
+ defaultoverlap allm5 metal5 allm1 metal1 9
+ defaultsideoverlap allm5 metal5 allm1 metal1 43
+ defaultsideoverlap allm1 metal1 allm5 metal5 12
+
+#metal5->metal2
+ defaultoverlap allm5 metal5 allm2 metal2 11
+ defaultsideoverlap allm5 metal5 allm2 metal2 46
+ defaultsideoverlap allm2 metal2 allm5 metal5 16
+
+#metal5->metal3
+ defaultoverlap allm5 metal5 allm3 metal3 20
+ defaultsideoverlap allm5 metal5 allm3 metal3 54
+ defaultsideoverlap allm3 metal3 allm5 metal5 28
+
+#metal5->metal4
+ defaultoverlap allm5 metal5 allm4 metal4 68
+ defaultsideoverlap allm5 metal5 allm4 metal4 83
+ defaultsideoverlap allm4 metal4 allm5 metal5 47
+
+
+# Devices: Base models (not subcircuit wrappers)
+
+variants (),(si)
+
+ device msubcircuit sky130_fd_pr__pfet_01v8 pfet,scpfet \
+ *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w
+ device msubcircuit sky130_fd_pr__special_pfet_pass ppu \
+ *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w
+ device msubcircuit sky130_fd_pr__pfet_01v8_lvt pfetlvt \
+ *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w
+ device msubcircuit sky130_fd_pr__pfet_01v8_mvt pfetmvt \
+ *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w
+ device msubcircuit sky130_fd_pr__pfet_01v8_hvt pfethvt,scpfethvt \
+ *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w
+
+ device msubcircuit sky130_fd_pr__nfet_01v8 nfet,scnfet \
+ *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w
+ device msubcircuit sky130_fd_pr__special_nfet_latch npd \
+ *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w
+ device msubcircuit sky130_fd_pr__special_nfet_pass npass \
+ *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w
+ device msubcircuit sky130_fd_pr__nfet_01v8_lvt nfetlvt \
+ *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w
+ device msubcircuit sky130_fd_bs_flash__special_sonosfet_star nsonos \
+ *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w
+ device subcircuit sky130_fd_pr__cap_var_lvt varactor \
+ *nndiff nwell error l=l w=w
+ device subcircuit sky130_fd_pr__cap_var_hvt varhvt \
+ *nndiff nwell error l=l w=w
+ device subcircuit sky130_fd_pr__cap_var mvvaractor \
+ *mvnndiff nwell error l=l w=w
+
+ # Bipolars
+ device msubcircuit sky130_fd_pr__npn_05v0 npn dnwell *ndiff space/w error a2=area
+ device msubcircuit sky130_fd_pr__pnp_05v0 pnp pwell,space/w *pdiff a2=area
+ device msubcircuit sky130_fd_pr__npn_11v0 npn dnwell *mvndiff space/w error a2=area
+
+ # Ignore the extended-drain FET geometry that forms part of the high-voltage
+ # bipolar devices.
+ device msubcircuit Ignore mvnfet *mvndiff,mvndiffres dnwell pwell,space/w error +npn,pnp
+ device msubcircuit Ignore mvpfet *mvpdiff,mvpdiffres pwell,space/w nwell error +npn,pnp
+
+ # Extended drain devices (must appear before the regular devices)
+ device msubcircuit sky130_fd_pr__nfet_20v0_nvt mvnnfet *mvndiff,mvndiffres \
+ dnwell pwell,space/w error l=l w=w
+ device msubcircuit sky130_fd_pr__nfet_20v0 mvnfet *mvndiff,mvndiffres \
+ dnwell pwell,space/w error l=l w=w
+ device msubcircuit sky130_fd_pr__pfet_20v0 mvpfet *mvpdiff,mvpdiffres \
+ pwell,space/w nwell error l=l w=w
+
+ device msubcircuit sky130_fd_pr__pfet_g5v0d10v5 mvpfet \
+ *mvpdiff,mvpdiffres *mvpdiff,mvpdiffres nwell error l=l w=w
+ device msubcircuit sky130_fd_pr__nfet_g5v0d10v5 mvnfet \
+ *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w
+ device msubcircuit sky130_fd_pr__nfet_05v0_nvt mvnnfet \
+ *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w
+
+ device resistor sky130_fd_pr__res_generic_l1 rli1 *li,coreli
+ device resistor sky130_fd_pr__res_generic_m1 rmetal1 *metal1
+ device resistor sky130_fd_pr__res_generic_m2 rmetal2 *metal2
+ device resistor sky130_fd_pr__res_generic_m3 rmetal3 *metal3
+ device resistor sky130_fd_pr__res_generic_m4 rm4 *m4
+ device resistor sky130_fd_pr__res_generic_m5 rm5 *m5
+
+ device rsubcircuit sky130_fd_pr__res_high_po_0p35 xhrpoly \
+ xpc pwell,space/w error +res0p35 l=l
+ device rsubcircuit sky130_fd_pr__res_high_po_0p69 xhrpoly \
+ xpc pwell,space/w error +res0p69 l=l
+ device rsubcircuit sky130_fd_pr__res_high_po_1p41 xhrpoly \
+ xpc pwell,space/w error +res1p41 l=l
+ device rsubcircuit sky130_fd_pr__res_high_po_2p85 xhrpoly \
+ xpc pwell,space/w error +res2p85 l=l
+ device rsubcircuit sky130_fd_pr__res_high_po_5p73 xhrpoly \
+ xpc pwell,space/w error +res5p73 l=l
+ device rsubcircuit sky130_fd_pr__res_high_po xhrpoly \
+ xpc pwell,space/w error l=l w=w
+ device rsubcircuit sky130_fd_pr__res_xhigh_po_0p35 uhrpoly \
+ xpc pwell,space/w error +res0p35 l=l
+ device rsubcircuit sky130_fd_pr__res_xhigh_po_0p69 uhrpoly \
+ xpc pwell,space/w error +res0p69 l=l
+ device rsubcircuit sky130_fd_pr__res_xhigh_po_1p41 uhrpoly \
+ xpc pwell,space/w error +res1p41 l=l
+ device rsubcircuit sky130_fd_pr__res_xhigh_po_2p85 uhrpoly \
+ xpc pwell,space/w error +res2p85 l=l
+ device rsubcircuit sky130_fd_pr__res_xhigh_po_5p73 uhrpoly \
+ xpc pwell,space/w error +res5p73 l=l
+ device rsubcircuit sky130_fd_pr__res_xhigh_po uhrpoly \
+ xpc pwell,space/w error l=l w=w
+
+ device rsubcircuit sky130_fd_pr__res_generic_nd ndiffres \
+ *ndiff pwell,space/w error l=l w=w
+ device rsubcircuit sky130_fd_pr__res_generic_pd pdiffres \
+ *pdiff nwell error l=l w=w
+ device rsubcircuit sky130_fd_pr__res_iso_pw rpw \
+ pwell dnwell error l=l w=w
+ device rsubcircuit sky130_fd_pr__res_generic_nd__hv mvndiffres \
+ *mvndiff pwell,space/w error l=l w=w
+ device rsubcircuit sky130_fd_pr__res_generic_pd__hv mvpdiffres \
+ *mvpdiff nwell error l=l w=w
+
+ device resistor sky130_fd_pr__res_generic_po rmp *poly
+ device resistor sky130_fd_pr__res_generic_po mrp1 *poly
+
+ device subcircuit sky130_fd_pr__diode_pd2nw_05v5 *pdiode \
+ nwell a=area
+ device subcircuit sky130_fd_pr__diode_pd2nw_05v5_lvt *pdiodelvt \
+ nwell a=area
+ device subcircuit sky130_fd_pr__diode_pd2nw_05v5_hvt *pdiodehvt \
+ nwell a=area
+ device subcircuit sky130_fd_pr__diode_pd2nw_11v0 *mvpdiode \
+ nwell a=area
+
+ device msubcircuit sky130_fd_pr__diode_pw2nd_05v5 *ndiode \
+ pwell,space/w a=area
+ device msubcircuit sky130_fd_pr__diode_pw2nd_05v5_lvt *ndiodelvt \
+ pwell,space/w a=area
+ device msubcircuit sky130_fd_pr__diode_pw2nd_05v5_nvt *nndiode \
+ pwell,space/w a=area
+ device msubcircuit sky130_fd_pr__diode_pw2nd_11v0 *mvndiode \
+ pwell,space/w a=area
+
+
+ device csubcircuit sky130_fd_pr__cap_mim_m3_1 *mimcap *m3 w=w l=l
+ device csubcircuit sky130_fd_pr__cap_mim_m3_2 *mimcap2 *m4 w=w l=l
+
+ variants (orig)
+
+ device mosfet sky130_fd_pr__pfet_01v8 scpfet,pfet pdiff,pdiffres,pdc nwell
+ device mosfet sky130_fd_pr__special_pfet_pass ppu pdiff,pdiffres,pdc nwell
+ device mosfet sky130_fd_pr__pfet_01v8_lvt pfetlvt pdiff,pdiffres,pdc nwell
+ device mosfet sky130_fd_pr__pfet_01v8_mvt pfetmvt pdiff,pdiffres,pdc nwell
+ device mosfet sky130_fd_pr__pfet_01v8_hvt scpfethvt,pfethvt pdiff,pdiffres,pdc nwell
+ device mosfet sky130_fd_pr__nfet_01v8 scnfet,nfet ndiff,ndiffres,ndc pwell,space/w
+ device mosfet sky130_fd_pr__special_nfet_pass npass ndiff,ndiffres,ndc pwell,space/w
+ device mosfet sky130_fd_pr__special_nfet_latch npd ndiff,ndiffres,ndc pwell,space/w
+ device mosfet sky130_fd_pr__special_nfet_latch npd ndiff,ndiffres,ndc pwell,space/w
+ device mosfet sky130_fd_pr__nfet_01v8_lvt nfetlvt ndiff,ndiffres,ndc pwell,space/w
+ device mosfet sky130_fd_bs_flash__special_sonosfet_star nsonos ndiff,ndiffres,ndc \
+ pwell,space/w
+
+ # Note that corenvar, corepvar are not considered devices, and extract as
+ # parasitic capacitance instead (but cap values need to be added).
+
+ # Extended drain devices (must appear before the regular devices)
+ device mosfet sky130_fd_pr__nfet_20v0_nvt mvnnfet *mvndiff,mvndiffres \
+ dnwell pwell,space/w error
+ device mosfet sky130_fd_pr__nfet_20v0 mvnfet *mvndiff,mvndiffres \
+ dnwell pwell,space/w error
+ device mosfet sky130_fd_pr__pfet_20v0 mvpfet *mvpdiff,mvpdiffres \
+ pwell,space/w nwell error
+
+ device mosfet sky130_fd_pr__pfet_g5v0d10v5 mvpfet mvpdiff,mvpdiffres,mvpdc nwell
+ device mosfet sky130_fd_pr__nfet_g5v0d10v5 mvnfet mvndiff,mvndiffres,mvndc pwell,space/w
+ device mosfet sky130_fd_pr__nfet_05v0_nvt mvnnfet *mvndiff,mvndiffres pwell,space/w
+
+ # These devices always extract as subcircuits
+ device subcircuit sky130_fd_pr__cap_var_lvt varactor *nndiff nwell error l=l w=w
+ device subcircuit sky130_fd_pr__cap_var_hvt varhvt *nndiff nwell error l=l w=w
+ device subcircuit sky130_fd_pr__cap_var mvvaractor *mvnndiff nwell error l=l w=w
+
+ device resistor sky130_fd_pr__res_generic_po rmp *poly
+ device resistor sky130_fd_pr__res_generic_l1 rli1 *li,coreli
+ device resistor sky130_fd_pr__res_generic_m1 rmetal1 *metal1
+ device resistor sky130_fd_pr__res_generic_m2 rmetal2 *metal2
+ device resistor sky130_fd_pr__res_generic_m3 rmetal3 *metal3
+ device resistor sky130_fd_pr__res_generic_m4 rm4 *m4
+ device resistor sky130_fd_pr__res_generic_m5 rm5 *m5
+
+ device resistor sky130_fd_pr__res_high_po_0p35 xhrpoly xpc +res0p35
+ device resistor sky130_fd_pr__res_high_po_0p69 xhrpoly xpc +res0p69
+ device resistor sky130_fd_pr__res_high_po_1p41 xhrpoly xpc +res1p41
+ device resistor sky130_fd_pr__res_high_po_2p85 xhrpoly xpc +res2p85
+ device resistor sky130_fd_pr__res_high_po_5p73 xhrpoly xpc +res5p73
+ device resistor sky130_fd_pr__res_high_po xhrpoly xpc
+ device resistor sky130_fd_pr__res_xhigh_po_0p35 uhrpoly xpc +res0p35
+ device resistor sky130_fd_pr__res_xhigh_po_0p69 uhrpoly xpc +res0p69
+ device resistor sky130_fd_pr__res_xhigh_po_1p41 uhrpoly xpc +res1p41
+ device resistor sky130_fd_pr__res_xhigh_po_2p85 uhrpoly xpc +res2p85
+ device resistor sky130_fd_pr__res_xhigh_po_5p73 uhrpoly xpc +res5p73
+ device resistor sky130_fd_pr__res_xhigh_po uhrpoly xpc
+ device resistor sky130_fd_pr__res_generic_po mrp1 *poly
+ device resistor sky130_fd_pr__res_generic_nd ndiffres *ndiff
+ device resistor sky130_fd_pr__res_generic_pd pdiffres *pdiff
+ device resistor mrdn_hv mvndiffres *mvndiff
+ device resistor mrdp_hv mvpdiffres *mvpdiff
+ device resistor sky130_fd_pr__res_iso_pw rpw pwell
+
+ device ndiode sky130_fd_pr__diode_pw2nd_05v5 *ndiode pwell,space/w a=area
+ device ndiode sky130_fd_pr__diode_pw2nd_05v5_lvt *ndiodelvt pwell,space/w a=area
+ device ndiode sky130_fd_pr__diode_pw2nd_05v5_nvt *nndiode pwell,space/w a=area
+ device ndiode sky130_fd_pr__diode_pw2nd_11v0 *mvndiode pwell,space/w a=area
+
+ device pdiode sky130_fd_pr__diode_pd2nw_05v5 *pdiode nwell a=area
+ device pdiode sky130_fd_pr__diode_pd2nw_05v5_lvt *pdiodelvt nwell a=area
+ device pdiode sky130_fd_pr__diode_pd2nw_05v5_hvt *pdiodehvt nwell a=area
+ device pdiode sky130_fd_pr__diode_pd2nw_11v0 *mvpdiode nwell a=area
+
+ device bjt sky130_fd_pr__npn_05v5 npn dnwell *ndiff space/w error a2=area
+ device bjt sky130_fd_pr__pnp_05v5 pnp pwell,space/w *pdiff a2=area
+ device bjt sky130_fd_pr__npn_11v0 npn dnwell *mvndiff space/w error a2=area
+
+ device capacitor sky130_fd_pr__cap_mim_m3_1 *mimcap *m3 1
+ device capacitor sky130_fd_pr__cap_mim_m3_2 *mimcap2 *m4 1
+
+end
+
+#-----------------------------------------------------
+# Wiring tool definitions
+#-----------------------------------------------------
+
+wiring
+ # All wiring values are in nanometers
+ scalefactor 10
+
+ contact lic 170 li 0 0 m1 30 60
+ contact v1 260 m1 0 30 m2 0 30
+ contact v2 280 m2 0 45 m3 25 0
+ contact v3 320 m3 0 30 m4 5 5
+ contact v4 1180 m4 0 m5 120
+
+ contact pc 170 poly 50 80 li 0 80
+ contact pdc 170 pdiff 40 60 li 0 80
+ contact ndc 170 ndiff 40 60 li 0 80
+ contact psc 170 psd 40 60 li 0 80
+ contact nsc 170 nsd 40 60 li 0 80
+
+end
+
+#-----------------------------------------------------
+# Plain old router. . .
+#-----------------------------------------------------
+
+router
+end
+
+#------------------------------------------------------------
+# Plowing (restored in magic 8.2, need to fill this section)
+#------------------------------------------------------------
+
+plowing
+end
+
+#-----------------------------------------------------------------
+# No special plot layers defined (use default PNM color choices)
+#-----------------------------------------------------------------
+
+plot
+ style pnm
+ default
+ draw fillblock no_color_at_all
+ draw nwell cwell
+end
+
diff --git a/mag/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.mag b/mag/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.mag
new file mode 100644
index 0000000..1684eb0
--- /dev/null
+++ b/mag/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.mag
@@ -0,0 +1,315 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1608587411
+<< viali >>
+rect 1663 2610 1697 2644
+rect 1951 2610 1985 2644
+rect 2431 1944 2465 1978
+<< metal1 >>
+rect 480 3282 3456 3307
+rect 480 3230 2122 3282
+rect 2174 3230 2186 3282
+rect 2238 3230 3456 3282
+rect 480 3205 3456 3230
+rect 1651 2644 1709 2650
+rect 1651 2610 1663 2644
+rect 1697 2641 1709 2644
+rect 1939 2644 1997 2650
+rect 1939 2641 1951 2644
+rect 1697 2613 1951 2641
+rect 1697 2610 1709 2613
+rect 1651 2604 1709 2610
+rect 1939 2610 1951 2613
+rect 1985 2641 1997 2644
+rect 3184 2641 3190 2653
+rect 1985 2613 3190 2641
+rect 1985 2610 1997 2613
+rect 1939 2604 1997 2610
+rect 3184 2601 3190 2613
+rect 3242 2601 3248 2653
+rect 480 2468 3456 2493
+rect 480 2416 822 2468
+rect 874 2416 886 2468
+rect 938 2416 3456 2468
+rect 480 2391 3456 2416
+rect 1536 2286 2110 2289
+rect 1536 2232 1670 2286
+rect 1664 2226 1670 2232
+rect 1854 2232 2110 2286
+rect 1854 2226 1860 2232
+rect 1664 2222 1860 2226
+rect 592 1935 598 1987
+rect 650 1975 656 1987
+rect 2419 1978 2477 1984
+rect 2419 1975 2431 1978
+rect 650 1947 2431 1975
+rect 650 1935 656 1947
+rect 2419 1944 2431 1947
+rect 2465 1944 2477 1978
+rect 2419 1938 2477 1944
+rect 480 1654 3456 1679
+rect 480 1602 2122 1654
+rect 2174 1602 2186 1654
+rect 2238 1602 3456 1654
+rect 480 1577 3456 1602
+rect 480 840 3456 865
+rect 480 788 822 840
+rect 874 788 886 840
+rect 938 788 3456 840
+rect 480 763 3456 788
+<< via1 >>
+rect 2122 3230 2174 3282
+rect 2186 3230 2238 3282
+rect 3190 2601 3242 2653
+rect 822 2416 874 2468
+rect 886 2416 938 2468
+rect 1670 2226 1854 2286
+rect 598 1935 650 1987
+rect 2122 1602 2174 1654
+rect 2186 1602 2238 1654
+rect 822 788 874 840
+rect 886 788 938 840
+<< metal2 >>
+rect 2112 3284 2248 3307
+rect 2168 3282 2192 3284
+rect 2174 3230 2186 3282
+rect 2168 3228 2192 3230
+rect 2112 3205 2248 3228
+rect 3190 2653 3242 2659
+rect 3284 2604 3340 3800
+rect 3242 2601 3340 2604
+rect 3190 2600 3340 2601
+rect 3190 2595 3326 2600
+rect 3202 2576 3326 2595
+rect 812 2470 948 2493
+rect 868 2468 892 2470
+rect 874 2416 886 2468
+rect 868 2414 892 2416
+rect 812 2391 948 2414
+rect 1660 2286 1864 2296
+rect 1660 2226 1670 2286
+rect 1854 2226 1864 2286
+rect 1660 2214 1864 2226
+rect 598 1987 650 1993
+rect 598 1929 650 1935
+rect 610 800 638 1929
+rect 2112 1656 2248 1679
+rect 2168 1654 2192 1656
+rect 2174 1602 2186 1654
+rect 2168 1600 2192 1602
+rect 2112 1577 2248 1600
+rect 812 842 948 865
+rect 868 840 892 842
+rect 596 -400 652 800
+rect 874 788 886 840
+rect 868 786 892 788
+rect 812 763 948 786
+<< via2 >>
+rect 2112 3282 2168 3284
+rect 2192 3282 2248 3284
+rect 2112 3230 2122 3282
+rect 2122 3230 2168 3282
+rect 2192 3230 2238 3282
+rect 2238 3230 2248 3282
+rect 2112 3228 2168 3230
+rect 2192 3228 2248 3230
+rect 812 2468 868 2470
+rect 892 2468 948 2470
+rect 812 2416 822 2468
+rect 822 2416 868 2468
+rect 892 2416 938 2468
+rect 938 2416 948 2468
+rect 812 2414 868 2416
+rect 892 2414 948 2416
+rect 1670 2226 1854 2286
+rect 2112 1654 2168 1656
+rect 2192 1654 2248 1656
+rect 2112 1602 2122 1654
+rect 2122 1602 2168 1654
+rect 2192 1602 2238 1654
+rect 2238 1602 2248 1654
+rect 2112 1600 2168 1602
+rect 2192 1600 2248 1602
+rect 812 840 868 842
+rect 892 840 948 842
+rect 812 788 822 840
+rect 822 788 868 840
+rect 892 788 938 840
+rect 938 788 948 840
+rect 812 786 868 788
+rect 892 786 948 788
+<< metal3 >>
+rect 2090 3288 2270 3289
+rect 2090 3224 2108 3288
+rect 2172 3224 2188 3288
+rect 2252 3224 2270 3288
+rect 2090 3223 2270 3224
+rect 790 2474 970 2475
+rect 790 2410 808 2474
+rect 872 2410 888 2474
+rect 952 2410 970 2474
+rect 790 2409 970 2410
+rect 1660 2290 1864 2296
+rect 1660 2226 1670 2290
+rect 1854 2226 1864 2290
+rect 1660 2214 1864 2226
+rect 2090 1660 2270 1661
+rect 2090 1596 2108 1660
+rect 2172 1596 2188 1660
+rect 2252 1596 2270 1660
+rect 2090 1595 2270 1596
+rect 790 846 970 847
+rect 790 782 808 846
+rect 872 782 888 846
+rect 952 782 970 846
+rect 790 781 970 782
+<< via3 >>
+rect 2108 3284 2172 3288
+rect 2108 3228 2112 3284
+rect 2112 3228 2168 3284
+rect 2168 3228 2172 3284
+rect 2108 3224 2172 3228
+rect 2188 3284 2252 3288
+rect 2188 3228 2192 3284
+rect 2192 3228 2248 3284
+rect 2248 3228 2252 3284
+rect 2188 3224 2252 3228
+rect 808 2470 872 2474
+rect 808 2414 812 2470
+rect 812 2414 868 2470
+rect 868 2414 872 2470
+rect 808 2410 872 2414
+rect 888 2470 952 2474
+rect 888 2414 892 2470
+rect 892 2414 948 2470
+rect 948 2414 952 2470
+rect 888 2410 952 2414
+rect 1670 2286 1854 2290
+rect 1670 2226 1854 2286
+rect 2108 1656 2172 1660
+rect 2108 1600 2112 1656
+rect 2112 1600 2168 1656
+rect 2168 1600 2172 1656
+rect 2108 1596 2172 1600
+rect 2188 1656 2252 1660
+rect 2188 1600 2192 1656
+rect 2192 1600 2248 1656
+rect 2248 1600 2252 1656
+rect 2188 1596 2252 1600
+rect 808 842 872 846
+rect 808 786 812 842
+rect 812 786 868 842
+rect 868 786 872 842
+rect 808 782 872 786
+rect 888 842 952 846
+rect 888 786 892 842
+rect 892 786 948 842
+rect 948 786 952 842
+rect 888 782 952 786
+<< metal4 >>
+rect 790 2474 970 3307
+rect 2090 3288 2270 3307
+rect 790 2410 808 2474
+rect 872 2410 888 2474
+rect 952 2410 970 2474
+rect 790 846 970 2410
+rect 1670 2296 1850 3256
+rect 2090 3224 2108 3288
+rect 2172 3224 2188 3288
+rect 2252 3224 2270 3288
+rect 1660 2290 1860 2296
+rect 1660 2226 1670 2290
+rect 1854 2226 1860 2290
+rect 1660 2216 1860 2226
+rect 790 782 808 846
+rect 872 782 888 846
+rect 952 782 970 846
+rect 1670 814 1850 2216
+rect 2090 1660 2270 3224
+rect 2090 1596 2108 1660
+rect 2172 1596 2188 1660
+rect 2252 1596 2270 1660
+rect 790 763 970 782
+rect 2090 763 2270 1596
+rect 2970 814 3150 3256
+use sky130_fd_sc_hvl__decap_8 FILLER_0_0 $PDKPATH/libs.ref/sky130_fd_sc_hvl/mag
+timestamp 1608587411
+transform 1 0 480 0 -1 1628
+box -66 -23 834 897
+use sky130_fd_sc_hvl__decap_8 FILLER_0_8
+timestamp 1608587411
+transform 1 0 1248 0 -1 1628
+box -66 -23 834 897
+use sky130_fd_sc_hvl__decap_8 FILLER_1_0
+timestamp 1608587411
+transform 1 0 480 0 1 1628
+box -66 -23 834 897
+use sky130_fd_sc_hvl__decap_4 FILLER_1_8 $PDKPATH/libs.ref/sky130_fd_sc_hvl/mag
+timestamp 1608587411
+transform 1 0 1248 0 1 1628
+box -66 -23 450 897
+use sky130_fd_sc_hvl__decap_8 FILLER_0_16
+timestamp 1608587411
+transform 1 0 2016 0 -1 1628
+box -66 -23 834 897
+use sky130_fd_sc_hvl__fill_1 FILLER_1_12 $PDKPATH/libs.ref/sky130_fd_sc_hvl/mag
+timestamp 1608587411
+transform 1 0 1632 0 1 1628
+box -66 -23 162 897
+use sky130_fd_sc_hvl__decap_4 FILLER_0_24
+timestamp 1608587411
+transform 1 0 2784 0 -1 1628
+box -66 -23 450 897
+use sky130_fd_sc_hvl__fill_2 FILLER_0_28 $PDKPATH/libs.ref/sky130_fd_sc_hvl/mag
+timestamp 1608587411
+transform 1 0 3168 0 -1 1628
+box -66 -23 258 897
+use sky130_fd_sc_hvl__fill_1 FILLER_0_30
+timestamp 1608587411
+transform 1 0 3360 0 -1 1628
+box -66 -23 162 897
+use sky130_fd_sc_hvl__fill_1 FILLER_1_30
+timestamp 1608587411
+transform 1 0 3360 0 1 1628
+box -66 -23 162 897
+use sky130_fd_sc_hvl__diode_2 ANTENNA_lvlshiftdown_A $PDKPATH/libs.ref/sky130_fd_sc_hvl/mag
+timestamp 1608587411
+transform 1 0 1536 0 -1 3256
+box -66 -23 258 897
+use sky130_fd_sc_hvl__decap_8 FILLER_2_0
+timestamp 1608587411
+transform 1 0 480 0 -1 3256
+box -66 -23 834 897
+use sky130_fd_sc_hvl__fill_2 FILLER_2_8
+timestamp 1608587411
+transform 1 0 1248 0 -1 3256
+box -66 -23 258 897
+use sky130_fd_sc_hvl__fill_1 FILLER_2_10
+timestamp 1608587411
+transform 1 0 1440 0 -1 3256
+box -66 -23 162 897
+use sky130_fd_sc_hvl__fill_1 FILLER_2_30
+timestamp 1608587411
+transform 1 0 3360 0 -1 3256
+box -66 -23 162 897
+use sky130_fd_sc_hvl__lsbufhv2lv_1 lvlshiftdown $PDKPATH/libs.ref/sky130_fd_sc_hvl/mag
+timestamp 1608587411
+transform 1 0 1728 0 1 1628
+box -66 -23 1698 1651
+<< labels >>
+rlabel metal2 s 3284 2600 3340 3800 6 A
+port 0 nsew signal input
+rlabel metal2 s 596 -400 652 800 6 X
+port 1 nsew signal tristate
+rlabel metal4 s 790 763 970 3307 6 VPWR
+port 2 nsew power bidirectional
+rlabel metal4 s 2090 763 2270 3307 6 VGND
+port 3 nsew ground bidirectional
+rlabel metal4 s 1670 814 1850 3256 6 LVPWR
+port 4 nsew power bidirectional
+rlabel metal4 s 2970 814 3150 3256 6 LVGND
+port 5 nsew ground bidirectional
+<< properties >>
+string FIXED_BBOX 0 0 4000 3400
+<< end >>
diff --git a/mag/sram_1rw1r_32_256_8_sky130.mag b/mag/sram_1rw1r_32_256_8_sky130.mag
new file mode 100644
index 0000000..a24a7aa
--- /dev/null
+++ b/mag/sram_1rw1r_32_256_8_sky130.mag
@@ -0,0 +1,426 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1613304635
+<< obsactive >>
+rect 1000 1000 76296 90247
+<< obsli1 >>
+rect 1000 1000 76356 90307
+<< obsm1 >>
+rect 1000 1000 76356 90307
+<< obsm2 >>
+rect 1000 1000 76356 90307
+<< metal3 >>
+rect 71856 90307 72204 90428
+rect 76208 90410 77260 90428
+rect 76208 90307 76944 90410
+rect 0 86557 920 86617
+rect 0 85429 920 85489
+rect 0 83729 920 83789
+rect 0 82601 920 82661
+rect 0 80901 920 80961
+rect 0 79773 920 79833
+rect 0 78073 920 78133
+rect 0 20225 920 20285
+rect 0 18525 920 18585
+rect 76356 90088 76944 90307
+rect 77248 90088 77260 90410
+rect 76356 90080 77260 90088
+rect 76436 89653 77296 89713
+rect 76356 88926 76810 88932
+rect 76356 88724 76500 88926
+rect 76804 88724 76810 88926
+rect 76356 88720 76810 88724
+rect 76436 29382 77296 29442
+rect 76436 27682 77296 27742
+rect 76436 26554 77296 26614
+rect 76436 24854 77296 24914
+rect 76436 23726 77296 23786
+rect 76436 22026 77296 22086
+rect 76436 20898 77296 20958
+<< obsm3 >>
+rect 1000 1000 76356 90307
+<< via3 >>
+rect 76944 90088 77248 90410
+rect 76500 88724 76804 88926
+<< metal4 >>
+rect 18805 90407 18865 91247
+rect 20053 90407 20113 91247
+rect 21301 90407 21361 91247
+rect 22549 90407 22609 91247
+rect 23797 90407 23857 91247
+rect 25045 90407 25105 91247
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+rect 77248 90088 77262 90410
+rect 76494 88926 76814 88936
+rect 76494 88724 76500 88926
+rect 76804 88724 76814 88926
+rect 3803 0 3863 920
+rect 6802 0 6862 920
+rect 7970 0 8030 920
+rect 9138 0 9198 920
+rect 10306 0 10366 920
+rect 11474 0 11534 920
+rect 12642 0 12702 920
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+rect 13810 0 13870 920
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+rect 14978 0 15038 920
+rect 15102 0 15162 920
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+rect 18606 0 18666 920
+rect 19650 0 19710 920
+rect 19774 0 19834 920
+rect 20818 0 20878 920
+rect 20942 0 21002 920
+rect 21986 0 22046 920
+rect 22110 0 22170 920
+rect 23154 0 23214 920
+rect 23278 0 23338 920
+rect 24322 0 24382 920
+rect 24446 0 24506 920
+rect 25490 0 25550 920
+rect 25614 0 25674 920
+rect 26658 0 26718 920
+rect 26782 0 26842 920
+rect 27826 0 27886 920
+rect 27950 0 28010 920
+rect 28994 0 29054 920
+rect 29118 0 29178 920
+rect 30162 0 30222 920
+rect 30286 0 30346 920
+rect 31330 0 31390 920
+rect 31454 0 31514 920
+rect 32498 0 32558 920
+rect 32622 0 32682 920
+rect 33666 0 33726 920
+rect 33790 0 33850 920
+rect 34834 0 34894 920
+rect 34958 0 35018 920
+rect 36002 0 36062 920
+rect 36126 0 36186 920
+rect 37170 0 37230 920
+rect 37294 0 37354 920
+rect 38338 0 38398 920
+rect 38462 0 38522 920
+rect 39506 0 39566 920
+rect 39630 0 39690 920
+rect 40674 0 40734 920
+rect 40798 0 40858 920
+rect 41842 0 41902 920
+rect 41966 0 42026 920
+rect 43010 0 43070 920
+rect 43134 0 43194 920
+rect 44178 0 44238 920
+rect 44302 0 44362 920
+rect 45346 0 45406 920
+rect 45470 0 45530 920
+rect 46514 0 46574 920
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+rect 47682 0 47742 920
+rect 47806 0 47866 920
+rect 48850 0 48910 920
+rect 48974 0 49034 920
+rect 76494 734 76814 88724
+rect 76938 812 77262 90088
+<< obsm4 >>
+rect 1000 1000 76356 90307
+<< labels >>
+rlabel metal4 s 12642 0 12702 920 6 din0[0]
+port 1 nsew default input
+rlabel metal4 s 13810 0 13870 920 6 din0[1]
+port 2 nsew default input
+rlabel metal4 s 14978 0 15038 920 6 din0[2]
+port 3 nsew default input
+rlabel metal4 s 16146 0 16206 920 6 din0[3]
+port 4 nsew default input
+rlabel metal4 s 17314 0 17374 920 6 din0[4]
+port 5 nsew default input
+rlabel metal4 s 18482 0 18542 920 6 din0[5]
+port 6 nsew default input
+rlabel metal4 s 19650 0 19710 920 6 din0[6]
+port 7 nsew default input
+rlabel metal4 s 20818 0 20878 920 6 din0[7]
+port 8 nsew default input
+rlabel metal4 s 21986 0 22046 920 6 din0[8]
+port 9 nsew default input
+rlabel metal4 s 23154 0 23214 920 6 din0[9]
+port 10 nsew default input
+rlabel metal4 s 24322 0 24382 920 6 din0[10]
+port 11 nsew default input
+rlabel metal4 s 25490 0 25550 920 6 din0[11]
+port 12 nsew default input
+rlabel metal4 s 26658 0 26718 920 6 din0[12]
+port 13 nsew default input
+rlabel metal4 s 27826 0 27886 920 6 din0[13]
+port 14 nsew default input
+rlabel metal4 s 28994 0 29054 920 6 din0[14]
+port 15 nsew default input
+rlabel metal4 s 30162 0 30222 920 6 din0[15]
+port 16 nsew default input
+rlabel metal4 s 31330 0 31390 920 6 din0[16]
+port 17 nsew default input
+rlabel metal4 s 32498 0 32558 920 6 din0[17]
+port 18 nsew default input
+rlabel metal4 s 33666 0 33726 920 6 din0[18]
+port 19 nsew default input
+rlabel metal4 s 34834 0 34894 920 6 din0[19]
+port 20 nsew default input
+rlabel metal4 s 36002 0 36062 920 6 din0[20]
+port 21 nsew default input
+rlabel metal4 s 37170 0 37230 920 6 din0[21]
+port 22 nsew default input
+rlabel metal4 s 38338 0 38398 920 6 din0[22]
+port 23 nsew default input
+rlabel metal4 s 39506 0 39566 920 6 din0[23]
+port 24 nsew default input
+rlabel metal4 s 40674 0 40734 920 6 din0[24]
+port 25 nsew default input
+rlabel metal4 s 41842 0 41902 920 6 din0[25]
+port 26 nsew default input
+rlabel metal4 s 43010 0 43070 920 6 din0[26]
+port 27 nsew default input
+rlabel metal4 s 44178 0 44238 920 6 din0[27]
+port 28 nsew default input
+rlabel metal4 s 45346 0 45406 920 6 din0[28]
+port 29 nsew default input
+rlabel metal4 s 46514 0 46574 920 6 din0[29]
+port 30 nsew default input
+rlabel metal4 s 47682 0 47742 920 6 din0[30]
+port 31 nsew default input
+rlabel metal4 s 48850 0 48910 920 6 din0[31]
+port 32 nsew default input
+rlabel metal4 s 6802 0 6862 920 6 addr0[0]
+port 33 nsew default input
+rlabel metal3 s 0 78073 920 78133 6 addr0[1]
+port 34 nsew default input
+rlabel metal3 s 0 79773 920 79833 6 addr0[2]
+port 35 nsew default input
+rlabel metal3 s 0 80901 920 80961 6 addr0[3]
+port 36 nsew default input
+rlabel metal3 s 0 82601 920 82661 6 addr0[4]
+port 37 nsew default input
+rlabel metal3 s 0 83729 920 83789 6 addr0[5]
+port 38 nsew default input
+rlabel metal3 s 0 85429 920 85489 6 addr0[6]
+port 39 nsew default input
+rlabel metal3 s 0 86557 920 86617 6 addr0[7]
+port 40 nsew default input
+rlabel metal4 s 68578 90407 68638 91247 6 addr1[0]
+port 41 nsew default input
+rlabel metal3 s 76436 29382 77296 29442 6 addr1[1]
+port 42 nsew default input
+rlabel metal3 s 76436 27682 77296 27742 6 addr1[2]
+port 43 nsew default input
+rlabel metal3 s 76436 26554 77296 26614 6 addr1[3]
+port 44 nsew default input
+rlabel metal3 s 76436 24854 77296 24914 6 addr1[4]
+port 45 nsew default input
+rlabel metal3 s 76436 23726 77296 23786 6 addr1[5]
+port 46 nsew default input
+rlabel metal3 s 76436 22026 77296 22086 6 addr1[6]
+port 47 nsew default input
+rlabel metal3 s 76436 20898 77296 20958 6 addr1[7]
+port 48 nsew default input
+rlabel metal3 s 0 18525 920 18585 6 csb0
+port 49 nsew default input
+rlabel metal3 s 76436 89653 77296 89713 6 csb1
+port 50 nsew default input
+rlabel metal3 s 0 20225 920 20285 6 web0
+port 51 nsew default input
+rlabel metal4 s 3803 0 3863 920 6 clk0
+port 52 nsew default input
+rlabel metal4 s 73573 90407 73633 91247 6 clk1
+port 53 nsew default input
+rlabel metal4 s 7970 0 8030 920 6 wmask0[0]
+port 54 nsew default input
+rlabel metal4 s 9138 0 9198 920 6 wmask0[1]
+port 55 nsew default input
+rlabel metal4 s 10306 0 10366 920 6 wmask0[2]
+port 56 nsew default input
+rlabel metal4 s 11474 0 11534 920 6 wmask0[3]
+port 57 nsew default input
+rlabel metal4 s 12766 0 12826 920 6 dout0[0]
+port 58 nsew default output
+rlabel metal4 s 13934 0 13994 920 6 dout0[1]
+port 59 nsew default output
+rlabel metal4 s 15102 0 15162 920 6 dout0[2]
+port 60 nsew default output
+rlabel metal4 s 16270 0 16330 920 6 dout0[3]
+port 61 nsew default output
+rlabel metal4 s 17438 0 17498 920 6 dout0[4]
+port 62 nsew default output
+rlabel metal4 s 18606 0 18666 920 6 dout0[5]
+port 63 nsew default output
+rlabel metal4 s 19774 0 19834 920 6 dout0[6]
+port 64 nsew default output
+rlabel metal4 s 20942 0 21002 920 6 dout0[7]
+port 65 nsew default output
+rlabel metal4 s 22110 0 22170 920 6 dout0[8]
+port 66 nsew default output
+rlabel metal4 s 23278 0 23338 920 6 dout0[9]
+port 67 nsew default output
+rlabel metal4 s 24446 0 24506 920 6 dout0[10]
+port 68 nsew default output
+rlabel metal4 s 25614 0 25674 920 6 dout0[11]
+port 69 nsew default output
+rlabel metal4 s 26782 0 26842 920 6 dout0[12]
+port 70 nsew default output
+rlabel metal4 s 27950 0 28010 920 6 dout0[13]
+port 71 nsew default output
+rlabel metal4 s 29118 0 29178 920 6 dout0[14]
+port 72 nsew default output
+rlabel metal4 s 30286 0 30346 920 6 dout0[15]
+port 73 nsew default output
+rlabel metal4 s 31454 0 31514 920 6 dout0[16]
+port 74 nsew default output
+rlabel metal4 s 32622 0 32682 920 6 dout0[17]
+port 75 nsew default output
+rlabel metal4 s 33790 0 33850 920 6 dout0[18]
+port 76 nsew default output
+rlabel metal4 s 34958 0 35018 920 6 dout0[19]
+port 77 nsew default output
+rlabel metal4 s 36126 0 36186 920 6 dout0[20]
+port 78 nsew default output
+rlabel metal4 s 37294 0 37354 920 6 dout0[21]
+port 79 nsew default output
+rlabel metal4 s 38462 0 38522 920 6 dout0[22]
+port 80 nsew default output
+rlabel metal4 s 39630 0 39690 920 6 dout0[23]
+port 81 nsew default output
+rlabel metal4 s 40798 0 40858 920 6 dout0[24]
+port 82 nsew default output
+rlabel metal4 s 41966 0 42026 920 6 dout0[25]
+port 83 nsew default output
+rlabel metal4 s 43134 0 43194 920 6 dout0[26]
+port 84 nsew default output
+rlabel metal4 s 44302 0 44362 920 6 dout0[27]
+port 85 nsew default output
+rlabel metal4 s 45470 0 45530 920 6 dout0[28]
+port 86 nsew default output
+rlabel metal4 s 46638 0 46698 920 6 dout0[29]
+port 87 nsew default output
+rlabel metal4 s 47806 0 47866 920 6 dout0[30]
+port 88 nsew default output
+rlabel metal4 s 48974 0 49034 920 6 dout0[31]
+port 89 nsew default output
+rlabel metal4 s 18805 90407 18865 91247 6 dout1[0]
+port 90 nsew default output
+rlabel metal4 s 20053 90407 20113 91247 6 dout1[1]
+port 91 nsew default output
+rlabel metal4 s 21301 90407 21361 91247 6 dout1[2]
+port 92 nsew default output
+rlabel metal4 s 22549 90407 22609 91247 6 dout1[3]
+port 93 nsew default output
+rlabel metal4 s 23797 90407 23857 91247 6 dout1[4]
+port 94 nsew default output
+rlabel metal4 s 25045 90407 25105 91247 6 dout1[5]
+port 95 nsew default output
+rlabel metal4 s 26293 90407 26353 91247 6 dout1[6]
+port 96 nsew default output
+rlabel metal4 s 27541 90407 27601 91247 6 dout1[7]
+port 97 nsew default output
+rlabel metal4 s 28789 90407 28849 91247 6 dout1[8]
+port 98 nsew default output
+rlabel metal4 s 30037 90407 30097 91247 6 dout1[9]
+port 99 nsew default output
+rlabel metal4 s 31285 90407 31345 91247 6 dout1[10]
+port 100 nsew default output
+rlabel metal4 s 32533 90407 32593 91247 6 dout1[11]
+port 101 nsew default output
+rlabel metal4 s 33781 90407 33841 91247 6 dout1[12]
+port 102 nsew default output
+rlabel metal4 s 35029 90407 35089 91247 6 dout1[13]
+port 103 nsew default output
+rlabel metal4 s 36277 90407 36337 91247 6 dout1[14]
+port 104 nsew default output
+rlabel metal4 s 37525 90407 37585 91247 6 dout1[15]
+port 105 nsew default output
+rlabel metal4 s 38773 90407 38833 91247 6 dout1[16]
+port 106 nsew default output
+rlabel metal4 s 40021 90407 40081 91247 6 dout1[17]
+port 107 nsew default output
+rlabel metal4 s 41269 90407 41329 91247 6 dout1[18]
+port 108 nsew default output
+rlabel metal4 s 42517 90407 42577 91247 6 dout1[19]
+port 109 nsew default output
+rlabel metal4 s 43765 90407 43825 91247 6 dout1[20]
+port 110 nsew default output
+rlabel metal4 s 45013 90407 45073 91247 6 dout1[21]
+port 111 nsew default output
+rlabel metal4 s 46261 90407 46321 91247 6 dout1[22]
+port 112 nsew default output
+rlabel metal4 s 47509 90407 47569 91247 6 dout1[23]
+port 113 nsew default output
+rlabel metal4 s 48757 90407 48817 91247 6 dout1[24]
+port 114 nsew default output
+rlabel metal4 s 50005 90407 50065 91247 6 dout1[25]
+port 115 nsew default output
+rlabel metal4 s 51253 90407 51313 91247 6 dout1[26]
+port 116 nsew default output
+rlabel metal4 s 52501 90407 52561 91247 6 dout1[27]
+port 117 nsew default output
+rlabel metal4 s 53749 90407 53809 91247 6 dout1[28]
+port 118 nsew default output
+rlabel metal4 s 54997 90407 55057 91247 6 dout1[29]
+port 119 nsew default output
+rlabel metal4 s 56245 90407 56305 91247 6 dout1[30]
+port 120 nsew default output
+rlabel metal4 s 57493 90407 57553 91247 6 dout1[31]
+port 121 nsew default output
+rlabel metal4 s 76494 734 76814 88936 6 vdd
+port 122 nsew power bidirectional
+rlabel via3 s 76500 88724 76804 88926 6 vdd
+port 122 nsew power bidirectional
+rlabel metal3 s 76208 88720 76810 88932 6 vdd
+port 122 nsew power bidirectional
+rlabel metal3 s 71856 90216 72204 90428 6 gnd
+port 123 nsew ground bidirectional
+rlabel metal4 s 76938 812 77262 90428 6 gnd
+port 123 nsew ground bidirectional
+rlabel via3 s 76944 90088 77248 90410 6 gnd
+port 123 nsew ground bidirectional
+rlabel metal3 s 76208 90080 77260 90428 6 gnd
+port 123 nsew ground bidirectional
+<< properties >>
+string LEFclass BLOCK
+string FIXED_BBOX 0 0 77296 91247
+string LEFsymmetry X Y R90
+string LEFview TRUE
+string GDS_FILE ../gds/sram_1rw1r_32_256_8_sky130.gds
+string GDS_END 13299042
+string GDS_START 13275442
+<< end >>
diff --git a/mag/switch_layout.mag b/mag/switch_layout.mag
new file mode 100644
index 0000000..09c5aa5
--- /dev/null
+++ b/mag/switch_layout.mag
@@ -0,0 +1,231 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624221218
+<< checkpaint >>
+rect -1220 -1088 3720 2440
+<< nwell >>
+rect 506 622 602 1172
+rect 1166 654 1548 1100
+rect 1816 172 2200 624
+<< nmos >>
+rect 2010 820 2040 940
+rect 1350 340 1380 460
+<< pmos >>
+rect 1350 700 1380 942
+rect 2010 330 2040 570
+<< ndiff >>
+rect 1920 898 2010 940
+rect 1920 864 1938 898
+rect 1972 864 2010 898
+rect 1920 820 2010 864
+rect 2040 898 2130 940
+rect 2040 864 2078 898
+rect 2112 864 2130 898
+rect 2040 820 2130 864
+rect 1260 417 1350 460
+rect 1260 383 1277 417
+rect 1311 383 1350 417
+rect 1260 340 1350 383
+rect 1380 417 1470 460
+rect 1380 383 1418 417
+rect 1452 383 1470 417
+rect 1380 340 1470 383
+<< pdiff >>
+rect 1270 868 1350 942
+rect 1270 834 1283 868
+rect 1317 834 1350 868
+rect 1270 800 1350 834
+rect 1270 766 1283 800
+rect 1317 766 1350 800
+rect 1270 700 1350 766
+rect 1380 871 1462 942
+rect 1380 837 1413 871
+rect 1447 837 1462 871
+rect 1380 803 1462 837
+rect 1380 769 1413 803
+rect 1447 769 1462 803
+rect 1380 700 1462 769
+rect 1930 499 2010 570
+rect 1930 465 1943 499
+rect 1977 465 2010 499
+rect 1930 431 2010 465
+rect 1930 397 1943 431
+rect 1977 397 2010 431
+rect 1930 330 2010 397
+rect 2040 501 2122 570
+rect 2040 467 2073 501
+rect 2107 467 2122 501
+rect 2040 433 2122 467
+rect 2040 399 2073 433
+rect 2107 399 2122 433
+rect 2040 330 2122 399
+<< ndiffc >>
+rect 1938 864 1972 898
+rect 2078 864 2112 898
+rect 1277 383 1311 417
+rect 1418 383 1452 417
+<< pdiffc >>
+rect 1283 834 1317 868
+rect 1283 766 1317 800
+rect 1413 837 1447 871
+rect 1413 769 1447 803
+rect 1943 465 1977 499
+rect 1943 397 1977 431
+rect 2073 467 2107 501
+rect 2073 399 2107 433
+<< poly >>
+rect 1350 942 1380 970
+rect 2010 940 2040 970
+rect 2010 790 2040 820
+rect 2170 815 2230 840
+rect 2170 790 2183 815
+rect 2008 781 2183 790
+rect 2217 781 2230 815
+rect 2008 760 2230 781
+rect 920 580 984 582
+rect 730 557 984 580
+rect 730 542 935 557
+rect 920 523 935 542
+rect 969 523 984 557
+rect 920 504 984 523
+rect 1190 576 1248 582
+rect 1350 576 1380 700
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+rect 2010 570 2040 760
+rect 1190 523 1201 557
+rect 1235 540 1380 557
+rect 1235 523 1248 540
+rect 1190 504 1248 523
+rect 1350 460 1380 540
+rect 1350 310 1380 340
+rect 2010 298 2040 330
+<< polycont >>
+rect 2183 781 2217 815
+rect 935 523 969 557
+rect 1201 523 1235 557
+<< locali >>
+rect 492 992 612 1142
+rect 1230 1010 2280 1070
+rect 1270 868 1320 1010
+rect 1270 834 1283 868
+rect 1317 834 1320 868
+rect 1270 800 1320 834
+rect 1270 766 1283 800
+rect 1317 766 1320 800
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+rect 842 680 844 682
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+rect 810 667 870 670
+rect 810 648 813 667
+rect 790 633 813 648
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+rect 790 630 870 633
+rect 40 518 196 612
+rect 790 610 834 630
+rect 840 622 870 630
+rect 1410 622 1462 769
+rect 1920 898 1980 940
+rect 1920 864 1938 898
+rect 1972 864 1980 898
+rect 1920 730 1980 864
+rect 2070 898 2130 1010
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+rect 2112 864 2130 898
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+rect 2170 830 2230 840
+rect 2170 815 2350 830
+rect 2170 781 2183 815
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+rect 2170 779 2304 781
+rect 2338 779 2350 813
+rect 2170 760 2350 779
+rect 1408 610 1462 622
+rect 1718 726 1980 730
+rect 1718 692 1932 726
+rect 1966 692 1980 726
+rect 1718 678 1980 692
+rect 1718 610 1780 678
+rect 414 542 570 580
+rect 920 557 1248 582
+rect 920 523 935 557
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+rect 1408 552 1780 610
+rect 1408 550 1470 552
+rect 1718 550 1780 552
+rect 920 504 1248 523
+rect 1260 417 1320 460
+rect 1260 383 1277 417
+rect 1311 383 1320 417
+rect 502 192 622 312
+rect 1260 260 1320 383
+rect 1410 417 1470 550
+rect 1410 383 1418 417
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+rect 1930 499 1980 678
+rect 1930 465 1943 499
+rect 1977 465 1980 499
+rect 1930 431 1980 465
+rect 1930 397 1943 431
+rect 1977 397 1980 431
+rect 1930 330 1980 397
+rect 2070 501 2122 570
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+rect 2107 467 2122 501
+rect 2070 433 2122 467
+rect 2070 399 2073 433
+rect 2107 399 2122 433
+rect 2070 260 2122 399
+rect 1250 200 2300 260
+<< viali >>
+rect 813 633 847 667
+rect 2304 779 2338 813
+rect 1932 692 1966 726
+<< metal1 >>
+rect 502 980 602 1150
+rect 1038 1148 2330 1180
+rect 1038 1138 2332 1148
+rect 1040 920 1080 1138
+rect 920 880 1080 920
+rect 920 680 960 880
+rect 2292 830 2332 1138
+rect 2292 813 2350 830
+rect 2292 779 2304 813
+rect 2338 779 2350 813
+rect 2292 770 2350 779
+rect 1920 726 2460 740
+rect 1920 692 1932 726
+rect 1966 692 2460 726
+rect 1920 680 2460 692
+rect 790 667 960 680
+rect 790 633 813 667
+rect 847 633 960 667
+rect 790 622 960 633
+rect 512 182 612 324
+use INV INV_0
+timestamp 1624221218
+transform 1 0 224 0 1 622
+box -88 -440 290 550
+use INV INV_1
+timestamp 1624221218
+transform 1 0 602 0 1 622
+box -88 -440 290 550
+<< labels >>
+rlabel metal1 s 544 1068 544 1068 4 vdd!
+rlabel metal1 s 540 216 540 216 4 gnd!
+rlabel locali s 1576 220 1576 220 4 inp2
+rlabel locali s 1778 1032 1778 1032 4 inp1
+rlabel locali s 100 566 100 566 4 din
+rlabel locali s 470 556 470 556 4 dinb
+rlabel poly s 2116 776 2116 776 4 dd
+rlabel metal1 s 2112 702 2112 702 4 vout
+<< end >>
diff --git a/mag/user_analog_project_wrapper.mag b/mag/user_analog_project_wrapper.mag
new file mode 100644
index 0000000..2f81a79
--- /dev/null
+++ b/mag/user_analog_project_wrapper.mag
@@ -0,0 +1,2332 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624220454
+<< checkpaint >>
+rect -2114 -2060 586060 706060
+<< locali >>
+rect 46054 508408 47990 508612
+rect 1388 508124 18224 508148
+rect 1040 508082 18224 508124
+rect 34048 508082 47990 508408
+rect 1040 508050 47990 508082
+rect 1040 508016 1076 508050
+rect 1110 508016 47990 508050
+rect 1040 507948 47990 508016
+rect 1388 507936 47990 507948
+rect 17790 507870 47990 507936
+rect 34048 507680 47990 507870
+rect 41820 465164 42396 465210
+rect 12010 464980 36218 465044
+rect 41796 464980 42534 465164
+rect 1308 464958 1904 464962
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+rect 1280 464892 42534 464938
+rect 1280 464786 1317 464892
+rect 1423 464786 42534 464892
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+rect 46054 443352 47990 507680
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+rect 41660 426014 42778 426232
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+rect 45470 425825 48130 426512
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+flabel metal3 s -800 2726 480 2838 0 FreeSans 3416 0 0 0 io_out[26]
+flabel metal3 s 583520 13364 584800 13476 0 FreeSans 3416 0 0 0 io_out[2]
+flabel metal3 s 583520 18092 584800 18204 0 FreeSans 3416 0 0 0 io_out[3]
+flabel metal3 s 583520 22820 584800 22932 0 FreeSans 3416 0 0 0 io_out[4]
+flabel metal3 s 583520 49278 584800 49390 0 FreeSans 3416 0 0 0 io_out[5]
+flabel metal3 s 583520 93936 584800 94048 0 FreeSans 3416 0 0 0 io_out[6]
+flabel metal3 s 583520 273958 584800 274070 0 FreeSans 3416 0 0 0 io_out[7]
+flabel metal3 s 583520 318380 584800 318492 0 FreeSans 3416 0 0 0 io_out[8]
+flabel metal3 s 583520 363602 584800 363714 0 FreeSans 3416 0 0 0 io_out[9]
+flabel metal2 s 125816 -800 125928 480 0 FreeSans 3416 90 0 0 la_data_in[0]
+flabel metal2 s 480416 -800 480528 480 0 FreeSans 3416 90 0 0 la_data_in[100]
+flabel metal2 s 483962 -800 484074 480 0 FreeSans 3416 90 0 0 la_data_in[101]
+flabel metal2 s 487508 -800 487620 480 0 FreeSans 3416 90 0 0 la_data_in[102]
+flabel metal2 s 491054 -800 491166 480 0 FreeSans 3416 90 0 0 la_data_in[103]
+flabel metal2 s 494600 -800 494712 480 0 FreeSans 3416 90 0 0 la_data_in[104]
+flabel metal2 s 498146 -800 498258 480 0 FreeSans 3416 90 0 0 la_data_in[105]
+flabel metal2 s 501692 -800 501804 480 0 FreeSans 3416 90 0 0 la_data_in[106]
+flabel metal2 s 505238 -800 505350 480 0 FreeSans 3416 90 0 0 la_data_in[107]
+flabel metal2 s 508784 -800 508896 480 0 FreeSans 3416 90 0 0 la_data_in[108]
+flabel metal2 s 512330 -800 512442 480 0 FreeSans 3416 90 0 0 la_data_in[109]
+flabel metal2 s 161276 -800 161388 480 0 FreeSans 3416 90 0 0 la_data_in[10]
+flabel metal2 s 515876 -800 515988 480 0 FreeSans 3416 90 0 0 la_data_in[110]
+flabel metal2 s 519422 -800 519534 480 0 FreeSans 3416 90 0 0 la_data_in[111]
+flabel metal2 s 522968 -800 523080 480 0 FreeSans 3416 90 0 0 la_data_in[112]
+flabel metal2 s 526514 -800 526626 480 0 FreeSans 3416 90 0 0 la_data_in[113]
+flabel metal2 s 530060 -800 530172 480 0 FreeSans 3416 90 0 0 la_data_in[114]
+flabel metal2 s 533606 -800 533718 480 0 FreeSans 3416 90 0 0 la_data_in[115]
+flabel metal2 s 537152 -800 537264 480 0 FreeSans 3416 90 0 0 la_data_in[116]
+flabel metal2 s 540698 -800 540810 480 0 FreeSans 3416 90 0 0 la_data_in[117]
+flabel metal2 s 544244 -800 544356 480 0 FreeSans 3416 90 0 0 la_data_in[118]
+flabel metal2 s 547790 -800 547902 480 0 FreeSans 3416 90 0 0 la_data_in[119]
+flabel metal2 s 164822 -800 164934 480 0 FreeSans 3416 90 0 0 la_data_in[11]
+flabel metal2 s 551336 -800 551448 480 0 FreeSans 3416 90 0 0 la_data_in[120]
+flabel metal2 s 554882 -800 554994 480 0 FreeSans 3416 90 0 0 la_data_in[121]
+flabel metal2 s 558428 -800 558540 480 0 FreeSans 3416 90 0 0 la_data_in[122]
+flabel metal2 s 561974 -800 562086 480 0 FreeSans 3416 90 0 0 la_data_in[123]
+flabel metal2 s 565520 -800 565632 480 0 FreeSans 3416 90 0 0 la_data_in[124]
+flabel metal2 s 569066 -800 569178 480 0 FreeSans 3416 90 0 0 la_data_in[125]
+flabel metal2 s 572612 -800 572724 480 0 FreeSans 3416 90 0 0 la_data_in[126]
+flabel metal2 s 576158 -800 576270 480 0 FreeSans 3416 90 0 0 la_data_in[127]
+flabel metal2 s 168368 -800 168480 480 0 FreeSans 3416 90 0 0 la_data_in[12]
+flabel metal2 s 171914 -800 172026 480 0 FreeSans 3416 90 0 0 la_data_in[13]
+flabel metal2 s 175460 -800 175572 480 0 FreeSans 3416 90 0 0 la_data_in[14]
+flabel metal2 s 179006 -800 179118 480 0 FreeSans 3416 90 0 0 la_data_in[15]
+flabel metal2 s 182552 -800 182664 480 0 FreeSans 3416 90 0 0 la_data_in[16]
+flabel metal2 s 186098 -800 186210 480 0 FreeSans 3416 90 0 0 la_data_in[17]
+flabel metal2 s 189644 -800 189756 480 0 FreeSans 3416 90 0 0 la_data_in[18]
+flabel metal2 s 193190 -800 193302 480 0 FreeSans 3416 90 0 0 la_data_in[19]
+flabel metal2 s 129362 -800 129474 480 0 FreeSans 3416 90 0 0 la_data_in[1]
+flabel metal2 s 196736 -800 196848 480 0 FreeSans 3416 90 0 0 la_data_in[20]
+flabel metal2 s 200282 -800 200394 480 0 FreeSans 3416 90 0 0 la_data_in[21]
+flabel metal2 s 203828 -800 203940 480 0 FreeSans 3416 90 0 0 la_data_in[22]
+flabel metal2 s 207374 -800 207486 480 0 FreeSans 3416 90 0 0 la_data_in[23]
+flabel metal2 s 210920 -800 211032 480 0 FreeSans 3416 90 0 0 la_data_in[24]
+flabel metal2 s 214466 -800 214578 480 0 FreeSans 3416 90 0 0 la_data_in[25]
+flabel metal2 s 218012 -800 218124 480 0 FreeSans 3416 90 0 0 la_data_in[26]
+flabel metal2 s 221558 -800 221670 480 0 FreeSans 3416 90 0 0 la_data_in[27]
+flabel metal2 s 225104 -800 225216 480 0 FreeSans 3416 90 0 0 la_data_in[28]
+flabel metal2 s 228650 -800 228762 480 0 FreeSans 3416 90 0 0 la_data_in[29]
+flabel metal2 s 132908 -800 133020 480 0 FreeSans 3416 90 0 0 la_data_in[2]
+flabel metal2 s 232196 -800 232308 480 0 FreeSans 3416 90 0 0 la_data_in[30]
+flabel metal2 s 235742 -800 235854 480 0 FreeSans 3416 90 0 0 la_data_in[31]
+flabel metal2 s 239288 -800 239400 480 0 FreeSans 3416 90 0 0 la_data_in[32]
+flabel metal2 s 242834 -800 242946 480 0 FreeSans 3416 90 0 0 la_data_in[33]
+flabel metal2 s 246380 -800 246492 480 0 FreeSans 3416 90 0 0 la_data_in[34]
+flabel metal2 s 249926 -800 250038 480 0 FreeSans 3416 90 0 0 la_data_in[35]
+flabel metal2 s 253472 -800 253584 480 0 FreeSans 3416 90 0 0 la_data_in[36]
+flabel metal2 s 257018 -800 257130 480 0 FreeSans 3416 90 0 0 la_data_in[37]
+flabel metal2 s 260564 -800 260676 480 0 FreeSans 3416 90 0 0 la_data_in[38]
+flabel metal2 s 264110 -800 264222 480 0 FreeSans 3416 90 0 0 la_data_in[39]
+flabel metal2 s 136454 -800 136566 480 0 FreeSans 3416 90 0 0 la_data_in[3]
+flabel metal2 s 267656 -800 267768 480 0 FreeSans 3416 90 0 0 la_data_in[40]
+flabel metal2 s 271202 -800 271314 480 0 FreeSans 3416 90 0 0 la_data_in[41]
+flabel metal2 s 274748 -800 274860 480 0 FreeSans 3416 90 0 0 la_data_in[42]
+flabel metal2 s 278294 -800 278406 480 0 FreeSans 3416 90 0 0 la_data_in[43]
+flabel metal2 s 281840 -800 281952 480 0 FreeSans 3416 90 0 0 la_data_in[44]
+flabel metal2 s 285386 -800 285498 480 0 FreeSans 3416 90 0 0 la_data_in[45]
+flabel metal2 s 288932 -800 289044 480 0 FreeSans 3416 90 0 0 la_data_in[46]
+flabel metal2 s 292478 -800 292590 480 0 FreeSans 3416 90 0 0 la_data_in[47]
+flabel metal2 s 296024 -800 296136 480 0 FreeSans 3416 90 0 0 la_data_in[48]
+flabel metal2 s 299570 -800 299682 480 0 FreeSans 3416 90 0 0 la_data_in[49]
+flabel metal2 s 140000 -800 140112 480 0 FreeSans 3416 90 0 0 la_data_in[4]
+flabel metal2 s 303116 -800 303228 480 0 FreeSans 3416 90 0 0 la_data_in[50]
+flabel metal2 s 306662 -800 306774 480 0 FreeSans 3416 90 0 0 la_data_in[51]
+flabel metal2 s 310208 -800 310320 480 0 FreeSans 3416 90 0 0 la_data_in[52]
+flabel metal2 s 313754 -800 313866 480 0 FreeSans 3416 90 0 0 la_data_in[53]
+flabel metal2 s 317300 -800 317412 480 0 FreeSans 3416 90 0 0 la_data_in[54]
+flabel metal2 s 320846 -800 320958 480 0 FreeSans 3416 90 0 0 la_data_in[55]
+flabel metal2 s 324392 -800 324504 480 0 FreeSans 3416 90 0 0 la_data_in[56]
+flabel metal2 s 327938 -800 328050 480 0 FreeSans 3416 90 0 0 la_data_in[57]
+flabel metal2 s 331484 -800 331596 480 0 FreeSans 3416 90 0 0 la_data_in[58]
+flabel metal2 s 335030 -800 335142 480 0 FreeSans 3416 90 0 0 la_data_in[59]
+flabel metal2 s 143546 -800 143658 480 0 FreeSans 3416 90 0 0 la_data_in[5]
+flabel metal2 s 338576 -800 338688 480 0 FreeSans 3416 90 0 0 la_data_in[60]
+flabel metal2 s 342122 -800 342234 480 0 FreeSans 3416 90 0 0 la_data_in[61]
+flabel metal2 s 345668 -800 345780 480 0 FreeSans 3416 90 0 0 la_data_in[62]
+flabel metal2 s 349214 -800 349326 480 0 FreeSans 3416 90 0 0 la_data_in[63]
+flabel metal2 s 352760 -800 352872 480 0 FreeSans 3416 90 0 0 la_data_in[64]
+flabel metal2 s 356306 -800 356418 480 0 FreeSans 3416 90 0 0 la_data_in[65]
+flabel metal2 s 359852 -800 359964 480 0 FreeSans 3416 90 0 0 la_data_in[66]
+flabel metal2 s 363398 -800 363510 480 0 FreeSans 3416 90 0 0 la_data_in[67]
+flabel metal2 s 366944 -800 367056 480 0 FreeSans 3416 90 0 0 la_data_in[68]
+flabel metal2 s 370490 -800 370602 480 0 FreeSans 3416 90 0 0 la_data_in[69]
+flabel metal2 s 147092 -800 147204 480 0 FreeSans 3416 90 0 0 la_data_in[6]
+flabel metal2 s 374036 -800 374148 480 0 FreeSans 3416 90 0 0 la_data_in[70]
+flabel metal2 s 377582 -800 377694 480 0 FreeSans 3416 90 0 0 la_data_in[71]
+flabel metal2 s 381128 -800 381240 480 0 FreeSans 3416 90 0 0 la_data_in[72]
+flabel metal2 s 384674 -800 384786 480 0 FreeSans 3416 90 0 0 la_data_in[73]
+flabel metal2 s 388220 -800 388332 480 0 FreeSans 3416 90 0 0 la_data_in[74]
+flabel metal2 s 391766 -800 391878 480 0 FreeSans 3416 90 0 0 la_data_in[75]
+flabel metal2 s 395312 -800 395424 480 0 FreeSans 3416 90 0 0 la_data_in[76]
+flabel metal2 s 398858 -800 398970 480 0 FreeSans 3416 90 0 0 la_data_in[77]
+flabel metal2 s 402404 -800 402516 480 0 FreeSans 3416 90 0 0 la_data_in[78]
+flabel metal2 s 405950 -800 406062 480 0 FreeSans 3416 90 0 0 la_data_in[79]
+flabel metal2 s 150638 -800 150750 480 0 FreeSans 3416 90 0 0 la_data_in[7]
+flabel metal2 s 409496 -800 409608 480 0 FreeSans 3416 90 0 0 la_data_in[80]
+flabel metal2 s 413042 -800 413154 480 0 FreeSans 3416 90 0 0 la_data_in[81]
+flabel metal2 s 416588 -800 416700 480 0 FreeSans 3416 90 0 0 la_data_in[82]
+flabel metal2 s 420134 -800 420246 480 0 FreeSans 3416 90 0 0 la_data_in[83]
+flabel metal2 s 423680 -800 423792 480 0 FreeSans 3416 90 0 0 la_data_in[84]
+flabel metal2 s 427226 -800 427338 480 0 FreeSans 3416 90 0 0 la_data_in[85]
+flabel metal2 s 430772 -800 430884 480 0 FreeSans 3416 90 0 0 la_data_in[86]
+flabel metal2 s 434318 -800 434430 480 0 FreeSans 3416 90 0 0 la_data_in[87]
+flabel metal2 s 437864 -800 437976 480 0 FreeSans 3416 90 0 0 la_data_in[88]
+flabel metal2 s 441410 -800 441522 480 0 FreeSans 3416 90 0 0 la_data_in[89]
+flabel metal2 s 154184 -800 154296 480 0 FreeSans 3416 90 0 0 la_data_in[8]
+flabel metal2 s 444956 -800 445068 480 0 FreeSans 3416 90 0 0 la_data_in[90]
+flabel metal2 s 448502 -800 448614 480 0 FreeSans 3416 90 0 0 la_data_in[91]
+flabel metal2 s 452048 -800 452160 480 0 FreeSans 3416 90 0 0 la_data_in[92]
+flabel metal2 s 455594 -800 455706 480 0 FreeSans 3416 90 0 0 la_data_in[93]
+flabel metal2 s 459140 -800 459252 480 0 FreeSans 3416 90 0 0 la_data_in[94]
+flabel metal2 s 462686 -800 462798 480 0 FreeSans 3416 90 0 0 la_data_in[95]
+flabel metal2 s 466232 -800 466344 480 0 FreeSans 3416 90 0 0 la_data_in[96]
+flabel metal2 s 469778 -800 469890 480 0 FreeSans 3416 90 0 0 la_data_in[97]
+flabel metal2 s 473324 -800 473436 480 0 FreeSans 3416 90 0 0 la_data_in[98]
+flabel metal2 s 476870 -800 476982 480 0 FreeSans 3416 90 0 0 la_data_in[99]
+flabel metal2 s 157730 -800 157842 480 0 FreeSans 3416 90 0 0 la_data_in[9]
+flabel metal2 s 126998 -800 127110 480 0 FreeSans 3416 90 0 0 la_data_out[0]
+flabel metal2 s 481598 -800 481710 480 0 FreeSans 3416 90 0 0 la_data_out[100]
+flabel metal2 s 485144 -800 485256 480 0 FreeSans 3416 90 0 0 la_data_out[101]
+flabel metal2 s 488690 -800 488802 480 0 FreeSans 3416 90 0 0 la_data_out[102]
+flabel metal2 s 492236 -800 492348 480 0 FreeSans 3416 90 0 0 la_data_out[103]
+flabel metal2 s 495782 -800 495894 480 0 FreeSans 3416 90 0 0 la_data_out[104]
+flabel metal2 s 499328 -800 499440 480 0 FreeSans 3416 90 0 0 la_data_out[105]
+flabel metal2 s 502874 -800 502986 480 0 FreeSans 3416 90 0 0 la_data_out[106]
+flabel metal2 s 506420 -800 506532 480 0 FreeSans 3416 90 0 0 la_data_out[107]
+flabel metal2 s 509966 -800 510078 480 0 FreeSans 3416 90 0 0 la_data_out[108]
+flabel metal2 s 513512 -800 513624 480 0 FreeSans 3416 90 0 0 la_data_out[109]
+flabel metal2 s 162458 -800 162570 480 0 FreeSans 3416 90 0 0 la_data_out[10]
+flabel metal2 s 517058 -800 517170 480 0 FreeSans 3416 90 0 0 la_data_out[110]
+flabel metal2 s 520604 -800 520716 480 0 FreeSans 3416 90 0 0 la_data_out[111]
+flabel metal2 s 524150 -800 524262 480 0 FreeSans 3416 90 0 0 la_data_out[112]
+flabel metal2 s 527696 -800 527808 480 0 FreeSans 3416 90 0 0 la_data_out[113]
+flabel metal2 s 531242 -800 531354 480 0 FreeSans 3416 90 0 0 la_data_out[114]
+flabel metal2 s 534788 -800 534900 480 0 FreeSans 3416 90 0 0 la_data_out[115]
+flabel metal2 s 538334 -800 538446 480 0 FreeSans 3416 90 0 0 la_data_out[116]
+flabel metal2 s 541880 -800 541992 480 0 FreeSans 3416 90 0 0 la_data_out[117]
+flabel metal2 s 545426 -800 545538 480 0 FreeSans 3416 90 0 0 la_data_out[118]
+flabel metal2 s 548972 -800 549084 480 0 FreeSans 3416 90 0 0 la_data_out[119]
+flabel metal2 s 166004 -800 166116 480 0 FreeSans 3416 90 0 0 la_data_out[11]
+flabel metal2 s 552518 -800 552630 480 0 FreeSans 3416 90 0 0 la_data_out[120]
+flabel metal2 s 556064 -800 556176 480 0 FreeSans 3416 90 0 0 la_data_out[121]
+flabel metal2 s 559610 -800 559722 480 0 FreeSans 3416 90 0 0 la_data_out[122]
+flabel metal2 s 563156 -800 563268 480 0 FreeSans 3416 90 0 0 la_data_out[123]
+flabel metal2 s 566702 -800 566814 480 0 FreeSans 3416 90 0 0 la_data_out[124]
+flabel metal2 s 570248 -800 570360 480 0 FreeSans 3416 90 0 0 la_data_out[125]
+flabel metal2 s 573794 -800 573906 480 0 FreeSans 3416 90 0 0 la_data_out[126]
+flabel metal2 s 577340 -800 577452 480 0 FreeSans 3416 90 0 0 la_data_out[127]
+flabel metal2 s 169550 -800 169662 480 0 FreeSans 3416 90 0 0 la_data_out[12]
+flabel metal2 s 173096 -800 173208 480 0 FreeSans 3416 90 0 0 la_data_out[13]
+flabel metal2 s 176642 -800 176754 480 0 FreeSans 3416 90 0 0 la_data_out[14]
+flabel metal2 s 180188 -800 180300 480 0 FreeSans 3416 90 0 0 la_data_out[15]
+flabel metal2 s 183734 -800 183846 480 0 FreeSans 3416 90 0 0 la_data_out[16]
+flabel metal2 s 187280 -800 187392 480 0 FreeSans 3416 90 0 0 la_data_out[17]
+flabel metal2 s 190826 -800 190938 480 0 FreeSans 3416 90 0 0 la_data_out[18]
+flabel metal2 s 194372 -800 194484 480 0 FreeSans 3416 90 0 0 la_data_out[19]
+flabel metal2 s 130544 -800 130656 480 0 FreeSans 3416 90 0 0 la_data_out[1]
+flabel metal2 s 197918 -800 198030 480 0 FreeSans 3416 90 0 0 la_data_out[20]
+flabel metal2 s 201464 -800 201576 480 0 FreeSans 3416 90 0 0 la_data_out[21]
+flabel metal2 s 205010 -800 205122 480 0 FreeSans 3416 90 0 0 la_data_out[22]
+flabel metal2 s 208556 -800 208668 480 0 FreeSans 3416 90 0 0 la_data_out[23]
+flabel metal2 s 212102 -800 212214 480 0 FreeSans 3416 90 0 0 la_data_out[24]
+flabel metal2 s 215648 -800 215760 480 0 FreeSans 3416 90 0 0 la_data_out[25]
+flabel metal2 s 219194 -800 219306 480 0 FreeSans 3416 90 0 0 la_data_out[26]
+flabel metal2 s 222740 -800 222852 480 0 FreeSans 3416 90 0 0 la_data_out[27]
+flabel metal2 s 226286 -800 226398 480 0 FreeSans 3416 90 0 0 la_data_out[28]
+flabel metal2 s 229832 -800 229944 480 0 FreeSans 3416 90 0 0 la_data_out[29]
+flabel metal2 s 134090 -800 134202 480 0 FreeSans 3416 90 0 0 la_data_out[2]
+flabel metal2 s 233378 -800 233490 480 0 FreeSans 3416 90 0 0 la_data_out[30]
+flabel metal2 s 236924 -800 237036 480 0 FreeSans 3416 90 0 0 la_data_out[31]
+flabel metal2 s 240470 -800 240582 480 0 FreeSans 3416 90 0 0 la_data_out[32]
+flabel metal2 s 244016 -800 244128 480 0 FreeSans 3416 90 0 0 la_data_out[33]
+flabel metal2 s 247562 -800 247674 480 0 FreeSans 3416 90 0 0 la_data_out[34]
+flabel metal2 s 251108 -800 251220 480 0 FreeSans 3416 90 0 0 la_data_out[35]
+flabel metal2 s 254654 -800 254766 480 0 FreeSans 3416 90 0 0 la_data_out[36]
+flabel metal2 s 258200 -800 258312 480 0 FreeSans 3416 90 0 0 la_data_out[37]
+flabel metal2 s 261746 -800 261858 480 0 FreeSans 3416 90 0 0 la_data_out[38]
+flabel metal2 s 265292 -800 265404 480 0 FreeSans 3416 90 0 0 la_data_out[39]
+flabel metal2 s 137636 -800 137748 480 0 FreeSans 3416 90 0 0 la_data_out[3]
+flabel metal2 s 268838 -800 268950 480 0 FreeSans 3416 90 0 0 la_data_out[40]
+flabel metal2 s 272384 -800 272496 480 0 FreeSans 3416 90 0 0 la_data_out[41]
+flabel metal2 s 275930 -800 276042 480 0 FreeSans 3416 90 0 0 la_data_out[42]
+flabel metal2 s 279476 -800 279588 480 0 FreeSans 3416 90 0 0 la_data_out[43]
+flabel metal2 s 283022 -800 283134 480 0 FreeSans 3416 90 0 0 la_data_out[44]
+flabel metal2 s 286568 -800 286680 480 0 FreeSans 3416 90 0 0 la_data_out[45]
+flabel metal2 s 290114 -800 290226 480 0 FreeSans 3416 90 0 0 la_data_out[46]
+flabel metal2 s 293660 -800 293772 480 0 FreeSans 3416 90 0 0 la_data_out[47]
+flabel metal2 s 297206 -800 297318 480 0 FreeSans 3416 90 0 0 la_data_out[48]
+flabel metal2 s 300752 -800 300864 480 0 FreeSans 3416 90 0 0 la_data_out[49]
+flabel metal2 s 141182 -800 141294 480 0 FreeSans 3416 90 0 0 la_data_out[4]
+flabel metal2 s 304298 -800 304410 480 0 FreeSans 3416 90 0 0 la_data_out[50]
+flabel metal2 s 307844 -800 307956 480 0 FreeSans 3416 90 0 0 la_data_out[51]
+flabel metal2 s 311390 -800 311502 480 0 FreeSans 3416 90 0 0 la_data_out[52]
+flabel metal2 s 314936 -800 315048 480 0 FreeSans 3416 90 0 0 la_data_out[53]
+flabel metal2 s 318482 -800 318594 480 0 FreeSans 3416 90 0 0 la_data_out[54]
+flabel metal2 s 322028 -800 322140 480 0 FreeSans 3416 90 0 0 la_data_out[55]
+flabel metal2 s 325574 -800 325686 480 0 FreeSans 3416 90 0 0 la_data_out[56]
+flabel metal2 s 329120 -800 329232 480 0 FreeSans 3416 90 0 0 la_data_out[57]
+flabel metal2 s 332666 -800 332778 480 0 FreeSans 3416 90 0 0 la_data_out[58]
+flabel metal2 s 336212 -800 336324 480 0 FreeSans 3416 90 0 0 la_data_out[59]
+flabel metal2 s 144728 -800 144840 480 0 FreeSans 3416 90 0 0 la_data_out[5]
+flabel metal2 s 339758 -800 339870 480 0 FreeSans 3416 90 0 0 la_data_out[60]
+flabel metal2 s 343304 -800 343416 480 0 FreeSans 3416 90 0 0 la_data_out[61]
+flabel metal2 s 346850 -800 346962 480 0 FreeSans 3416 90 0 0 la_data_out[62]
+flabel metal2 s 350396 -800 350508 480 0 FreeSans 3416 90 0 0 la_data_out[63]
+flabel metal2 s 353942 -800 354054 480 0 FreeSans 3416 90 0 0 la_data_out[64]
+flabel metal2 s 357488 -800 357600 480 0 FreeSans 3416 90 0 0 la_data_out[65]
+flabel metal2 s 361034 -800 361146 480 0 FreeSans 3416 90 0 0 la_data_out[66]
+flabel metal2 s 364580 -800 364692 480 0 FreeSans 3416 90 0 0 la_data_out[67]
+flabel metal2 s 368126 -800 368238 480 0 FreeSans 3416 90 0 0 la_data_out[68]
+flabel metal2 s 371672 -800 371784 480 0 FreeSans 3416 90 0 0 la_data_out[69]
+flabel metal2 s 148274 -800 148386 480 0 FreeSans 3416 90 0 0 la_data_out[6]
+flabel metal2 s 375218 -800 375330 480 0 FreeSans 3416 90 0 0 la_data_out[70]
+flabel metal2 s 378764 -800 378876 480 0 FreeSans 3416 90 0 0 la_data_out[71]
+flabel metal2 s 382310 -800 382422 480 0 FreeSans 3416 90 0 0 la_data_out[72]
+flabel metal2 s 385856 -800 385968 480 0 FreeSans 3416 90 0 0 la_data_out[73]
+flabel metal2 s 389402 -800 389514 480 0 FreeSans 3416 90 0 0 la_data_out[74]
+flabel metal2 s 392948 -800 393060 480 0 FreeSans 3416 90 0 0 la_data_out[75]
+flabel metal2 s 396494 -800 396606 480 0 FreeSans 3416 90 0 0 la_data_out[76]
+flabel metal2 s 400040 -800 400152 480 0 FreeSans 3416 90 0 0 la_data_out[77]
+flabel metal2 s 403586 -800 403698 480 0 FreeSans 3416 90 0 0 la_data_out[78]
+flabel metal2 s 407132 -800 407244 480 0 FreeSans 3416 90 0 0 la_data_out[79]
+flabel metal2 s 151820 -800 151932 480 0 FreeSans 3416 90 0 0 la_data_out[7]
+flabel metal2 s 410678 -800 410790 480 0 FreeSans 3416 90 0 0 la_data_out[80]
+flabel metal2 s 414224 -800 414336 480 0 FreeSans 3416 90 0 0 la_data_out[81]
+flabel metal2 s 417770 -800 417882 480 0 FreeSans 3416 90 0 0 la_data_out[82]
+flabel metal2 s 421316 -800 421428 480 0 FreeSans 3416 90 0 0 la_data_out[83]
+flabel metal2 s 424862 -800 424974 480 0 FreeSans 3416 90 0 0 la_data_out[84]
+flabel metal2 s 428408 -800 428520 480 0 FreeSans 3416 90 0 0 la_data_out[85]
+flabel metal2 s 431954 -800 432066 480 0 FreeSans 3416 90 0 0 la_data_out[86]
+flabel metal2 s 435500 -800 435612 480 0 FreeSans 3416 90 0 0 la_data_out[87]
+flabel metal2 s 439046 -800 439158 480 0 FreeSans 3416 90 0 0 la_data_out[88]
+flabel metal2 s 442592 -800 442704 480 0 FreeSans 3416 90 0 0 la_data_out[89]
+flabel metal2 s 155366 -800 155478 480 0 FreeSans 3416 90 0 0 la_data_out[8]
+flabel metal2 s 446138 -800 446250 480 0 FreeSans 3416 90 0 0 la_data_out[90]
+flabel metal2 s 449684 -800 449796 480 0 FreeSans 3416 90 0 0 la_data_out[91]
+flabel metal2 s 453230 -800 453342 480 0 FreeSans 3416 90 0 0 la_data_out[92]
+flabel metal2 s 456776 -800 456888 480 0 FreeSans 3416 90 0 0 la_data_out[93]
+flabel metal2 s 460322 -800 460434 480 0 FreeSans 3416 90 0 0 la_data_out[94]
+flabel metal2 s 463868 -800 463980 480 0 FreeSans 3416 90 0 0 la_data_out[95]
+flabel metal2 s 467414 -800 467526 480 0 FreeSans 3416 90 0 0 la_data_out[96]
+flabel metal2 s 470960 -800 471072 480 0 FreeSans 3416 90 0 0 la_data_out[97]
+flabel metal2 s 474506 -800 474618 480 0 FreeSans 3416 90 0 0 la_data_out[98]
+flabel metal2 s 478052 -800 478164 480 0 FreeSans 3416 90 0 0 la_data_out[99]
+flabel metal2 s 158912 -800 159024 480 0 FreeSans 3416 90 0 0 la_data_out[9]
+flabel metal2 s 128180 -800 128292 480 0 FreeSans 3416 90 0 0 la_oenb[0]
+flabel metal2 s 482780 -800 482892 480 0 FreeSans 3416 90 0 0 la_oenb[100]
+flabel metal2 s 486326 -800 486438 480 0 FreeSans 3416 90 0 0 la_oenb[101]
+flabel metal2 s 489872 -800 489984 480 0 FreeSans 3416 90 0 0 la_oenb[102]
+flabel metal2 s 493418 -800 493530 480 0 FreeSans 3416 90 0 0 la_oenb[103]
+flabel metal2 s 496964 -800 497076 480 0 FreeSans 3416 90 0 0 la_oenb[104]
+flabel metal2 s 500510 -800 500622 480 0 FreeSans 3416 90 0 0 la_oenb[105]
+flabel metal2 s 504056 -800 504168 480 0 FreeSans 3416 90 0 0 la_oenb[106]
+flabel metal2 s 507602 -800 507714 480 0 FreeSans 3416 90 0 0 la_oenb[107]
+flabel metal2 s 511148 -800 511260 480 0 FreeSans 3416 90 0 0 la_oenb[108]
+flabel metal2 s 514694 -800 514806 480 0 FreeSans 3416 90 0 0 la_oenb[109]
+flabel metal2 s 163640 -800 163752 480 0 FreeSans 3416 90 0 0 la_oenb[10]
+flabel metal2 s 518240 -800 518352 480 0 FreeSans 3416 90 0 0 la_oenb[110]
+flabel metal2 s 521786 -800 521898 480 0 FreeSans 3416 90 0 0 la_oenb[111]
+flabel metal2 s 525332 -800 525444 480 0 FreeSans 3416 90 0 0 la_oenb[112]
+flabel metal2 s 528878 -800 528990 480 0 FreeSans 3416 90 0 0 la_oenb[113]
+flabel metal2 s 532424 -800 532536 480 0 FreeSans 3416 90 0 0 la_oenb[114]
+flabel metal2 s 535970 -800 536082 480 0 FreeSans 3416 90 0 0 la_oenb[115]
+flabel metal2 s 539516 -800 539628 480 0 FreeSans 3416 90 0 0 la_oenb[116]
+flabel metal2 s 543062 -800 543174 480 0 FreeSans 3416 90 0 0 la_oenb[117]
+flabel metal2 s 546608 -800 546720 480 0 FreeSans 3416 90 0 0 la_oenb[118]
+flabel metal2 s 550154 -800 550266 480 0 FreeSans 3416 90 0 0 la_oenb[119]
+flabel metal2 s 167186 -800 167298 480 0 FreeSans 3416 90 0 0 la_oenb[11]
+flabel metal2 s 553700 -800 553812 480 0 FreeSans 3416 90 0 0 la_oenb[120]
+flabel metal2 s 557246 -800 557358 480 0 FreeSans 3416 90 0 0 la_oenb[121]
+flabel metal2 s 560792 -800 560904 480 0 FreeSans 3416 90 0 0 la_oenb[122]
+flabel metal2 s 564338 -800 564450 480 0 FreeSans 3416 90 0 0 la_oenb[123]
+flabel metal2 s 567884 -800 567996 480 0 FreeSans 3416 90 0 0 la_oenb[124]
+flabel metal2 s 571430 -800 571542 480 0 FreeSans 3416 90 0 0 la_oenb[125]
+flabel metal2 s 574976 -800 575088 480 0 FreeSans 3416 90 0 0 la_oenb[126]
+flabel metal2 s 578522 -800 578634 480 0 FreeSans 3416 90 0 0 la_oenb[127]
+flabel metal2 s 170732 -800 170844 480 0 FreeSans 3416 90 0 0 la_oenb[12]
+flabel metal2 s 174278 -800 174390 480 0 FreeSans 3416 90 0 0 la_oenb[13]
+flabel metal2 s 177824 -800 177936 480 0 FreeSans 3416 90 0 0 la_oenb[14]
+flabel metal2 s 181370 -800 181482 480 0 FreeSans 3416 90 0 0 la_oenb[15]
+flabel metal2 s 184916 -800 185028 480 0 FreeSans 3416 90 0 0 la_oenb[16]
+flabel metal2 s 188462 -800 188574 480 0 FreeSans 3416 90 0 0 la_oenb[17]
+flabel metal2 s 192008 -800 192120 480 0 FreeSans 3416 90 0 0 la_oenb[18]
+flabel metal2 s 195554 -800 195666 480 0 FreeSans 3416 90 0 0 la_oenb[19]
+flabel metal2 s 131726 -800 131838 480 0 FreeSans 3416 90 0 0 la_oenb[1]
+flabel metal2 s 199100 -800 199212 480 0 FreeSans 3416 90 0 0 la_oenb[20]
+flabel metal2 s 202646 -800 202758 480 0 FreeSans 3416 90 0 0 la_oenb[21]
+flabel metal2 s 206192 -800 206304 480 0 FreeSans 3416 90 0 0 la_oenb[22]
+flabel metal2 s 209738 -800 209850 480 0 FreeSans 3416 90 0 0 la_oenb[23]
+flabel metal2 s 213284 -800 213396 480 0 FreeSans 3416 90 0 0 la_oenb[24]
+flabel metal2 s 216830 -800 216942 480 0 FreeSans 3416 90 0 0 la_oenb[25]
+flabel metal2 s 220376 -800 220488 480 0 FreeSans 3416 90 0 0 la_oenb[26]
+flabel metal2 s 223922 -800 224034 480 0 FreeSans 3416 90 0 0 la_oenb[27]
+flabel metal2 s 227468 -800 227580 480 0 FreeSans 3416 90 0 0 la_oenb[28]
+flabel metal2 s 231014 -800 231126 480 0 FreeSans 3416 90 0 0 la_oenb[29]
+flabel metal2 s 135272 -800 135384 480 0 FreeSans 3416 90 0 0 la_oenb[2]
+flabel metal2 s 234560 -800 234672 480 0 FreeSans 3416 90 0 0 la_oenb[30]
+flabel metal2 s 238106 -800 238218 480 0 FreeSans 3416 90 0 0 la_oenb[31]
+flabel metal2 s 241652 -800 241764 480 0 FreeSans 3416 90 0 0 la_oenb[32]
+flabel metal2 s 245198 -800 245310 480 0 FreeSans 3416 90 0 0 la_oenb[33]
+flabel metal2 s 248744 -800 248856 480 0 FreeSans 3416 90 0 0 la_oenb[34]
+flabel metal2 s 252290 -800 252402 480 0 FreeSans 3416 90 0 0 la_oenb[35]
+flabel metal2 s 255836 -800 255948 480 0 FreeSans 3416 90 0 0 la_oenb[36]
+flabel metal2 s 259382 -800 259494 480 0 FreeSans 3416 90 0 0 la_oenb[37]
+flabel metal2 s 262928 -800 263040 480 0 FreeSans 3416 90 0 0 la_oenb[38]
+flabel metal2 s 266474 -800 266586 480 0 FreeSans 3416 90 0 0 la_oenb[39]
+flabel metal2 s 138818 -800 138930 480 0 FreeSans 3416 90 0 0 la_oenb[3]
+flabel metal2 s 270020 -800 270132 480 0 FreeSans 3416 90 0 0 la_oenb[40]
+flabel metal2 s 273566 -800 273678 480 0 FreeSans 3416 90 0 0 la_oenb[41]
+flabel metal2 s 277112 -800 277224 480 0 FreeSans 3416 90 0 0 la_oenb[42]
+flabel metal2 s 280658 -800 280770 480 0 FreeSans 3416 90 0 0 la_oenb[43]
+flabel metal2 s 284204 -800 284316 480 0 FreeSans 3416 90 0 0 la_oenb[44]
+flabel metal2 s 287750 -800 287862 480 0 FreeSans 3416 90 0 0 la_oenb[45]
+flabel metal2 s 291296 -800 291408 480 0 FreeSans 3416 90 0 0 la_oenb[46]
+flabel metal2 s 294842 -800 294954 480 0 FreeSans 3416 90 0 0 la_oenb[47]
+flabel metal2 s 298388 -800 298500 480 0 FreeSans 3416 90 0 0 la_oenb[48]
+flabel metal2 s 301934 -800 302046 480 0 FreeSans 3416 90 0 0 la_oenb[49]
+flabel metal2 s 142364 -800 142476 480 0 FreeSans 3416 90 0 0 la_oenb[4]
+flabel metal2 s 305480 -800 305592 480 0 FreeSans 3416 90 0 0 la_oenb[50]
+flabel metal2 s 309026 -800 309138 480 0 FreeSans 3416 90 0 0 la_oenb[51]
+flabel metal2 s 312572 -800 312684 480 0 FreeSans 3416 90 0 0 la_oenb[52]
+flabel metal2 s 316118 -800 316230 480 0 FreeSans 3416 90 0 0 la_oenb[53]
+flabel metal2 s 319664 -800 319776 480 0 FreeSans 3416 90 0 0 la_oenb[54]
+flabel metal2 s 323210 -800 323322 480 0 FreeSans 3416 90 0 0 la_oenb[55]
+flabel metal2 s 326756 -800 326868 480 0 FreeSans 3416 90 0 0 la_oenb[56]
+flabel metal2 s 330302 -800 330414 480 0 FreeSans 3416 90 0 0 la_oenb[57]
+flabel metal2 s 333848 -800 333960 480 0 FreeSans 3416 90 0 0 la_oenb[58]
+flabel metal2 s 337394 -800 337506 480 0 FreeSans 3416 90 0 0 la_oenb[59]
+flabel metal2 s 145910 -800 146022 480 0 FreeSans 3416 90 0 0 la_oenb[5]
+flabel metal2 s 340940 -800 341052 480 0 FreeSans 3416 90 0 0 la_oenb[60]
+flabel metal2 s 344486 -800 344598 480 0 FreeSans 3416 90 0 0 la_oenb[61]
+flabel metal2 s 348032 -800 348144 480 0 FreeSans 3416 90 0 0 la_oenb[62]
+flabel metal2 s 351578 -800 351690 480 0 FreeSans 3416 90 0 0 la_oenb[63]
+flabel metal2 s 355124 -800 355236 480 0 FreeSans 3416 90 0 0 la_oenb[64]
+flabel metal2 s 358670 -800 358782 480 0 FreeSans 3416 90 0 0 la_oenb[65]
+flabel metal2 s 362216 -800 362328 480 0 FreeSans 3416 90 0 0 la_oenb[66]
+flabel metal2 s 365762 -800 365874 480 0 FreeSans 3416 90 0 0 la_oenb[67]
+flabel metal2 s 369308 -800 369420 480 0 FreeSans 3416 90 0 0 la_oenb[68]
+flabel metal2 s 372854 -800 372966 480 0 FreeSans 3416 90 0 0 la_oenb[69]
+flabel metal2 s 149456 -800 149568 480 0 FreeSans 3416 90 0 0 la_oenb[6]
+flabel metal2 s 376400 -800 376512 480 0 FreeSans 3416 90 0 0 la_oenb[70]
+flabel metal2 s 379946 -800 380058 480 0 FreeSans 3416 90 0 0 la_oenb[71]
+flabel metal2 s 383492 -800 383604 480 0 FreeSans 3416 90 0 0 la_oenb[72]
+flabel metal2 s 387038 -800 387150 480 0 FreeSans 3416 90 0 0 la_oenb[73]
+flabel metal2 s 390584 -800 390696 480 0 FreeSans 3416 90 0 0 la_oenb[74]
+flabel metal2 s 394130 -800 394242 480 0 FreeSans 3416 90 0 0 la_oenb[75]
+flabel metal2 s 397676 -800 397788 480 0 FreeSans 3416 90 0 0 la_oenb[76]
+flabel metal2 s 401222 -800 401334 480 0 FreeSans 3416 90 0 0 la_oenb[77]
+flabel metal2 s 404768 -800 404880 480 0 FreeSans 3416 90 0 0 la_oenb[78]
+flabel metal2 s 408314 -800 408426 480 0 FreeSans 3416 90 0 0 la_oenb[79]
+flabel metal2 s 153002 -800 153114 480 0 FreeSans 3416 90 0 0 la_oenb[7]
+flabel metal2 s 411860 -800 411972 480 0 FreeSans 3416 90 0 0 la_oenb[80]
+flabel metal2 s 415406 -800 415518 480 0 FreeSans 3416 90 0 0 la_oenb[81]
+flabel metal2 s 418952 -800 419064 480 0 FreeSans 3416 90 0 0 la_oenb[82]
+flabel metal2 s 422498 -800 422610 480 0 FreeSans 3416 90 0 0 la_oenb[83]
+flabel metal2 s 426044 -800 426156 480 0 FreeSans 3416 90 0 0 la_oenb[84]
+flabel metal2 s 429590 -800 429702 480 0 FreeSans 3416 90 0 0 la_oenb[85]
+flabel metal2 s 433136 -800 433248 480 0 FreeSans 3416 90 0 0 la_oenb[86]
+flabel metal2 s 436682 -800 436794 480 0 FreeSans 3416 90 0 0 la_oenb[87]
+flabel metal2 s 440228 -800 440340 480 0 FreeSans 3416 90 0 0 la_oenb[88]
+flabel metal2 s 443774 -800 443886 480 0 FreeSans 3416 90 0 0 la_oenb[89]
+flabel metal2 s 156548 -800 156660 480 0 FreeSans 3416 90 0 0 la_oenb[8]
+flabel metal2 s 447320 -800 447432 480 0 FreeSans 3416 90 0 0 la_oenb[90]
+flabel metal2 s 450866 -800 450978 480 0 FreeSans 3416 90 0 0 la_oenb[91]
+flabel metal2 s 454412 -800 454524 480 0 FreeSans 3416 90 0 0 la_oenb[92]
+flabel metal2 s 457958 -800 458070 480 0 FreeSans 3416 90 0 0 la_oenb[93]
+flabel metal2 s 461504 -800 461616 480 0 FreeSans 3416 90 0 0 la_oenb[94]
+flabel metal2 s 465050 -800 465162 480 0 FreeSans 3416 90 0 0 la_oenb[95]
+flabel metal2 s 468596 -800 468708 480 0 FreeSans 3416 90 0 0 la_oenb[96]
+flabel metal2 s 472142 -800 472254 480 0 FreeSans 3416 90 0 0 la_oenb[97]
+flabel metal2 s 475688 -800 475800 480 0 FreeSans 3416 90 0 0 la_oenb[98]
+flabel metal2 s 479234 -800 479346 480 0 FreeSans 3416 90 0 0 la_oenb[99]
+flabel metal2 s 160094 -800 160206 480 0 FreeSans 3416 90 0 0 la_oenb[9]
+flabel metal2 s 579704 -800 579816 480 0 FreeSans 3416 90 0 0 user_clock2
+flabel metal2 s 580886 -800 580998 480 0 FreeSans 3416 90 0 0 user_irq[0]
+flabel metal2 s 582068 -800 582180 480 0 FreeSans 3416 90 0 0 user_irq[1]
+flabel metal2 s 583250 -800 583362 480 0 FreeSans 3416 90 0 0 user_irq[2]
+flabel metal3 s 582340 639784 584800 644584 0 FreeSans 3416 0 0 0 vccd1
+flabel metal3 s 582340 629784 584800 634584 0 FreeSans 3416 0 0 0 vccd1
+flabel metal3 s 0 643842 1660 648642 0 FreeSans 3416 0 0 0 vccd2
+flabel metal3 s 0 633842 1660 638642 0 FreeSans 3416 0 0 0 vccd2
+flabel metal3 s 582340 540562 584800 545362 0 FreeSans 3416 0 0 0 vdda1
+flabel metal3 s 582340 550562 584800 555362 0 FreeSans 3416 0 0 0 vdda1
+flabel metal3 s 582340 235230 584800 240030 0 FreeSans 3416 0 0 0 vdda1
+flabel metal3 s 582340 225230 584800 230030 0 FreeSans 3416 0 0 0 vdda1
+flabel metal3 s 0 204888 1660 209688 0 FreeSans 3416 0 0 0 vdda2
+flabel metal3 s 0 214888 1660 219688 0 FreeSans 3416 0 0 0 vdda2
+flabel metal3 s 520594 702340 525394 704800 0 FreeSans 5858 180 0 0 vssa1
+flabel metal3 s 510594 702340 515394 704800 0 FreeSans 5858 180 0 0 vssa1
+flabel metal3 s 582340 146830 584800 151630 0 FreeSans 3416 0 0 0 vssa1
+flabel metal3 s 582340 136830 584800 141630 0 FreeSans 3416 0 0 0 vssa1
+flabel metal3 s 0 559442 1660 564242 0 FreeSans 3416 0 0 0 vssa2
+flabel metal3 s 0 549442 1660 554242 0 FreeSans 3416 0 0 0 vssa2
+flabel metal3 s 582340 191430 584800 196230 0 FreeSans 3416 0 0 0 vssd1
+flabel metal3 s 582340 181430 584800 186230 0 FreeSans 3416 0 0 0 vssd1
+flabel metal3 s 0 172888 1660 177688 0 FreeSans 3416 0 0 0 vssd2
+flabel metal3 s 0 162888 1660 167688 0 FreeSans 3416 0 0 0 vssd2
+flabel metal2 s 524 -800 636 480 0 FreeSans 3416 90 0 0 wb_clk_i
+flabel metal2 s 1706 -800 1818 480 0 FreeSans 3416 90 0 0 wb_rst_i
+flabel metal2 s 2888 -800 3000 480 0 FreeSans 3416 90 0 0 wbs_ack_o
+flabel metal2 s 7616 -800 7728 480 0 FreeSans 3416 90 0 0 wbs_adr_i[0]
+flabel metal2 s 47804 -800 47916 480 0 FreeSans 3416 90 0 0 wbs_adr_i[10]
+flabel metal2 s 51350 -800 51462 480 0 FreeSans 3416 90 0 0 wbs_adr_i[11]
+flabel metal2 s 54896 -800 55008 480 0 FreeSans 3416 90 0 0 wbs_adr_i[12]
+flabel metal2 s 58442 -800 58554 480 0 FreeSans 3416 90 0 0 wbs_adr_i[13]
+flabel metal2 s 61988 -800 62100 480 0 FreeSans 3416 90 0 0 wbs_adr_i[14]
+flabel metal2 s 65534 -800 65646 480 0 FreeSans 3416 90 0 0 wbs_adr_i[15]
+flabel metal2 s 69080 -800 69192 480 0 FreeSans 3416 90 0 0 wbs_adr_i[16]
+flabel metal2 s 72626 -800 72738 480 0 FreeSans 3416 90 0 0 wbs_adr_i[17]
+flabel metal2 s 76172 -800 76284 480 0 FreeSans 3416 90 0 0 wbs_adr_i[18]
+flabel metal2 s 79718 -800 79830 480 0 FreeSans 3416 90 0 0 wbs_adr_i[19]
+flabel metal2 s 12344 -800 12456 480 0 FreeSans 3416 90 0 0 wbs_adr_i[1]
+flabel metal2 s 83264 -800 83376 480 0 FreeSans 3416 90 0 0 wbs_adr_i[20]
+flabel metal2 s 86810 -800 86922 480 0 FreeSans 3416 90 0 0 wbs_adr_i[21]
+flabel metal2 s 90356 -800 90468 480 0 FreeSans 3416 90 0 0 wbs_adr_i[22]
+flabel metal2 s 93902 -800 94014 480 0 FreeSans 3416 90 0 0 wbs_adr_i[23]
+flabel metal2 s 97448 -800 97560 480 0 FreeSans 3416 90 0 0 wbs_adr_i[24]
+flabel metal2 s 100994 -800 101106 480 0 FreeSans 3416 90 0 0 wbs_adr_i[25]
+flabel metal2 s 104540 -800 104652 480 0 FreeSans 3416 90 0 0 wbs_adr_i[26]
+flabel metal2 s 108086 -800 108198 480 0 FreeSans 3416 90 0 0 wbs_adr_i[27]
+flabel metal2 s 111632 -800 111744 480 0 FreeSans 3416 90 0 0 wbs_adr_i[28]
+flabel metal2 s 115178 -800 115290 480 0 FreeSans 3416 90 0 0 wbs_adr_i[29]
+flabel metal2 s 17072 -800 17184 480 0 FreeSans 3416 90 0 0 wbs_adr_i[2]
+flabel metal2 s 118724 -800 118836 480 0 FreeSans 3416 90 0 0 wbs_adr_i[30]
+flabel metal2 s 122270 -800 122382 480 0 FreeSans 3416 90 0 0 wbs_adr_i[31]
+flabel metal2 s 21800 -800 21912 480 0 FreeSans 3416 90 0 0 wbs_adr_i[3]
+flabel metal2 s 26528 -800 26640 480 0 FreeSans 3416 90 0 0 wbs_adr_i[4]
+flabel metal2 s 30074 -800 30186 480 0 FreeSans 3416 90 0 0 wbs_adr_i[5]
+flabel metal2 s 33620 -800 33732 480 0 FreeSans 3416 90 0 0 wbs_adr_i[6]
+flabel metal2 s 37166 -800 37278 480 0 FreeSans 3416 90 0 0 wbs_adr_i[7]
+flabel metal2 s 40712 -800 40824 480 0 FreeSans 3416 90 0 0 wbs_adr_i[8]
+flabel metal2 s 44258 -800 44370 480 0 FreeSans 3416 90 0 0 wbs_adr_i[9]
+flabel metal2 s 4070 -800 4182 480 0 FreeSans 3416 90 0 0 wbs_cyc_i
+flabel metal2 s 8798 -800 8910 480 0 FreeSans 3416 90 0 0 wbs_dat_i[0]
+flabel metal2 s 48986 -800 49098 480 0 FreeSans 3416 90 0 0 wbs_dat_i[10]
+flabel metal2 s 52532 -800 52644 480 0 FreeSans 3416 90 0 0 wbs_dat_i[11]
+flabel metal2 s 56078 -800 56190 480 0 FreeSans 3416 90 0 0 wbs_dat_i[12]
+flabel metal2 s 59624 -800 59736 480 0 FreeSans 3416 90 0 0 wbs_dat_i[13]
+flabel metal2 s 63170 -800 63282 480 0 FreeSans 3416 90 0 0 wbs_dat_i[14]
+flabel metal2 s 66716 -800 66828 480 0 FreeSans 3416 90 0 0 wbs_dat_i[15]
+flabel metal2 s 70262 -800 70374 480 0 FreeSans 3416 90 0 0 wbs_dat_i[16]
+flabel metal2 s 73808 -800 73920 480 0 FreeSans 3416 90 0 0 wbs_dat_i[17]
+flabel metal2 s 77354 -800 77466 480 0 FreeSans 3416 90 0 0 wbs_dat_i[18]
+flabel metal2 s 80900 -800 81012 480 0 FreeSans 3416 90 0 0 wbs_dat_i[19]
+flabel metal2 s 13526 -800 13638 480 0 FreeSans 3416 90 0 0 wbs_dat_i[1]
+flabel metal2 s 84446 -800 84558 480 0 FreeSans 3416 90 0 0 wbs_dat_i[20]
+flabel metal2 s 87992 -800 88104 480 0 FreeSans 3416 90 0 0 wbs_dat_i[21]
+flabel metal2 s 91538 -800 91650 480 0 FreeSans 3416 90 0 0 wbs_dat_i[22]
+flabel metal2 s 95084 -800 95196 480 0 FreeSans 3416 90 0 0 wbs_dat_i[23]
+flabel metal2 s 98630 -800 98742 480 0 FreeSans 3416 90 0 0 wbs_dat_i[24]
+flabel metal2 s 102176 -800 102288 480 0 FreeSans 3416 90 0 0 wbs_dat_i[25]
+flabel metal2 s 105722 -800 105834 480 0 FreeSans 3416 90 0 0 wbs_dat_i[26]
+flabel metal2 s 109268 -800 109380 480 0 FreeSans 3416 90 0 0 wbs_dat_i[27]
+flabel metal2 s 112814 -800 112926 480 0 FreeSans 3416 90 0 0 wbs_dat_i[28]
+flabel metal2 s 116360 -800 116472 480 0 FreeSans 3416 90 0 0 wbs_dat_i[29]
+flabel metal2 s 18254 -800 18366 480 0 FreeSans 3416 90 0 0 wbs_dat_i[2]
+flabel metal2 s 119906 -800 120018 480 0 FreeSans 3416 90 0 0 wbs_dat_i[30]
+flabel metal2 s 123452 -800 123564 480 0 FreeSans 3416 90 0 0 wbs_dat_i[31]
+flabel metal2 s 22982 -800 23094 480 0 FreeSans 3416 90 0 0 wbs_dat_i[3]
+flabel metal2 s 27710 -800 27822 480 0 FreeSans 3416 90 0 0 wbs_dat_i[4]
+flabel metal2 s 31256 -800 31368 480 0 FreeSans 3416 90 0 0 wbs_dat_i[5]
+flabel metal2 s 34802 -800 34914 480 0 FreeSans 3416 90 0 0 wbs_dat_i[6]
+flabel metal2 s 38348 -800 38460 480 0 FreeSans 3416 90 0 0 wbs_dat_i[7]
+flabel metal2 s 41894 -800 42006 480 0 FreeSans 3416 90 0 0 wbs_dat_i[8]
+flabel metal2 s 45440 -800 45552 480 0 FreeSans 3416 90 0 0 wbs_dat_i[9]
+flabel metal2 s 9980 -800 10092 480 0 FreeSans 3416 90 0 0 wbs_dat_o[0]
+flabel metal2 s 50168 -800 50280 480 0 FreeSans 3416 90 0 0 wbs_dat_o[10]
+flabel metal2 s 53714 -800 53826 480 0 FreeSans 3416 90 0 0 wbs_dat_o[11]
+flabel metal2 s 57260 -800 57372 480 0 FreeSans 3416 90 0 0 wbs_dat_o[12]
+flabel metal2 s 60806 -800 60918 480 0 FreeSans 3416 90 0 0 wbs_dat_o[13]
+flabel metal2 s 64352 -800 64464 480 0 FreeSans 3416 90 0 0 wbs_dat_o[14]
+flabel metal2 s 67898 -800 68010 480 0 FreeSans 3416 90 0 0 wbs_dat_o[15]
+flabel metal2 s 71444 -800 71556 480 0 FreeSans 3416 90 0 0 wbs_dat_o[16]
+flabel metal2 s 74990 -800 75102 480 0 FreeSans 3416 90 0 0 wbs_dat_o[17]
+flabel metal2 s 78536 -800 78648 480 0 FreeSans 3416 90 0 0 wbs_dat_o[18]
+flabel metal2 s 82082 -800 82194 480 0 FreeSans 3416 90 0 0 wbs_dat_o[19]
+flabel metal2 s 14708 -800 14820 480 0 FreeSans 3416 90 0 0 wbs_dat_o[1]
+flabel metal2 s 85628 -800 85740 480 0 FreeSans 3416 90 0 0 wbs_dat_o[20]
+flabel metal2 s 89174 -800 89286 480 0 FreeSans 3416 90 0 0 wbs_dat_o[21]
+flabel metal2 s 92720 -800 92832 480 0 FreeSans 3416 90 0 0 wbs_dat_o[22]
+flabel metal2 s 96266 -800 96378 480 0 FreeSans 3416 90 0 0 wbs_dat_o[23]
+flabel metal2 s 99812 -800 99924 480 0 FreeSans 3416 90 0 0 wbs_dat_o[24]
+flabel metal2 s 103358 -800 103470 480 0 FreeSans 3416 90 0 0 wbs_dat_o[25]
+flabel metal2 s 106904 -800 107016 480 0 FreeSans 3416 90 0 0 wbs_dat_o[26]
+flabel metal2 s 110450 -800 110562 480 0 FreeSans 3416 90 0 0 wbs_dat_o[27]
+flabel metal2 s 113996 -800 114108 480 0 FreeSans 3416 90 0 0 wbs_dat_o[28]
+flabel metal2 s 117542 -800 117654 480 0 FreeSans 3416 90 0 0 wbs_dat_o[29]
+flabel metal2 s 19436 -800 19548 480 0 FreeSans 3416 90 0 0 wbs_dat_o[2]
+flabel metal2 s 121088 -800 121200 480 0 FreeSans 3416 90 0 0 wbs_dat_o[30]
+flabel metal2 s 124634 -800 124746 480 0 FreeSans 3416 90 0 0 wbs_dat_o[31]
+flabel metal2 s 24164 -800 24276 480 0 FreeSans 3416 90 0 0 wbs_dat_o[3]
+flabel metal2 s 28892 -800 29004 480 0 FreeSans 3416 90 0 0 wbs_dat_o[4]
+flabel metal2 s 32438 -800 32550 480 0 FreeSans 3416 90 0 0 wbs_dat_o[5]
+flabel metal2 s 35984 -800 36096 480 0 FreeSans 3416 90 0 0 wbs_dat_o[6]
+flabel metal2 s 39530 -800 39642 480 0 FreeSans 3416 90 0 0 wbs_dat_o[7]
+flabel metal2 s 43076 -800 43188 480 0 FreeSans 3416 90 0 0 wbs_dat_o[8]
+flabel metal2 s 46622 -800 46734 480 0 FreeSans 3416 90 0 0 wbs_dat_o[9]
+flabel metal2 s 11162 -800 11274 480 0 FreeSans 3416 90 0 0 wbs_sel_i[0]
+flabel metal2 s 15890 -800 16002 480 0 FreeSans 3416 90 0 0 wbs_sel_i[1]
+flabel metal2 s 20618 -800 20730 480 0 FreeSans 3416 90 0 0 wbs_sel_i[2]
+flabel metal2 s 25346 -800 25458 480 0 FreeSans 3416 90 0 0 wbs_sel_i[3]
+flabel metal2 s 5252 -800 5364 480 0 FreeSans 3416 90 0 0 wbs_stb_i
+flabel metal2 s 6434 -800 6546 480 0 FreeSans 3416 90 0 0 wbs_we_i
+<< properties >>
+string FIXED_BBOX 0 0 584000 704000
+<< end >>
