| commit | 77acc9dfb7f456f9fb82b8529568a3f670fe6697 | [log] [tgz] |
|---|---|---|
| author | S Skandha Deepsita <skandha.deepsita5@gmail.com> | Mon Jun 28 12:37:32 2021 +0530 |
| committer | GitHub <noreply@github.com> | Mon Jun 28 12:37:32 2021 +0530 |
| tree | baafc24681f7fa39c191802736b45b5fa526c612 | |
| parent | 7a12a8f8bdaf6972d30736960e9e694f5b48b96a [diff] |
Update info.yaml
diff --git a/info.yaml b/info.yaml index 613ed24..e207f5e 100644 --- a/info.yaml +++ b/info.yaml
@@ -13,7 +13,7 @@ - "Open MPW" - "Test Harness" category: "Test Harness" - top_level_netlist: "verilog/gl/caravel.v" + top_level_netlist: "verilog/gl/caravan.v" user_level_netlist: "verilog/rtl/user_analog_project_wrapper.v" version: "1.00" cover_image: "Postlayout/Pictures/10bitdac layout desing.PNG "