| commit | 6c2df73837523ede05ed3b102df79308f4f50213 | [log] [tgz] |
|---|---|---|
| author | S Skandha Deepsita <skandha.deepsita5@gmail.com> | Mon Jun 28 11:46:41 2021 +0530 |
| committer | GitHub <noreply@github.com> | Mon Jun 28 11:46:41 2021 +0530 |
| tree | 35a0b4013903bf5f852bb77e4a8f4118b5d4d49f | |
| parent | aa728d57a3ff38a95d14a4ebcd0e41adadeebf89 [diff] |
Update info.yaml
diff --git a/info.yaml b/info.yaml index bec3e0e..e01c97d 100644 --- a/info.yaml +++ b/info.yaml
@@ -13,7 +13,7 @@ - "Open MPW" - "Test Harness" category: "Test Harness" - top_level_netlist: "verilog/rtl/caravel.v" + top_level_netlist: "verilog/rtl/user_analog_project_wrapper.v" user_level_netlist: "verilog/rtl/user_analog_project_wrapper.v" version: "1.00" cover_image: "Postlayout/Pictures/10bitdac layout desing.PNG "