| commit | 3dc2c754b6db5682e49e60f032447c6d83252ab9 | [log] [tgz] |
|---|---|---|
| author | S Skandha Deepsita <skandha.deepsita5@gmail.com> | Mon Jun 28 12:31:13 2021 +0530 |
| committer | GitHub <noreply@github.com> | Mon Jun 28 12:31:13 2021 +0530 |
| tree | 0daa5f3d17f35b17d1383b726aaec84e5e9c4f38 | |
| parent | d0891f2bc948155cded399e5e4fa836f5cf9653b [diff] |
Update info.yaml
diff --git a/info.yaml b/info.yaml index bec3e0e..613ed24 100644 --- a/info.yaml +++ b/info.yaml
@@ -13,7 +13,7 @@ - "Open MPW" - "Test Harness" category: "Test Harness" - top_level_netlist: "verilog/rtl/caravel.v" + top_level_netlist: "verilog/gl/caravel.v" user_level_netlist: "verilog/rtl/user_analog_project_wrapper.v" version: "1.00" cover_image: "Postlayout/Pictures/10bitdac layout desing.PNG "