commit e98885619012cd016322416e415e4ca7fa24ec60
author mrg <mrg@ucsc.edu> Fri Jun 18 08:01:45 2021 -0700
committer mrg <mrg@ucsc.edu> Fri Jun 18 08:01:45 2021 -0700
tree f1dbd0d2fd628a211c70aa94b549406720e2d245
parent 1946164ce18aa97f7c9803702be09dcd4933c11b

Update SP SRAMs to have spare_wen0

openlane/user_project_wrapper/config.tcl

diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 4e2a110..1498604 100755
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -53,6 +53,7 @@
 	$script_dir/../../verilog/rtl/sram_1rw0r0w_32_1024_sky130.v \
 	$script_dir/../../verilog/rtl/sram_1rw0r0w_32_256_sky130.v \
 	$script_dir/../../verilog/rtl/sram_1rw0r0w_32_512_sky130.v \
+	$script_dir/../../verilog/rtl/sram_1rw0r0w_32_512_sky130.v \
 	$script_dir/../../verilog/rtl/sram_1rw0r0w_64_512_sky130.v"
 #$script_dir/../../verilog/rtl/openram_testchip.v
 
@@ -101,7 +102,6 @@
 set ::env(RUN_KLAYOUT_XOR) 0
 
 # Spray diodes
-
 set ::env(DIODE_INSERTION_STRATEGY) 1
 # The following is because there are no std cells in the example wrapper project.
 #set ::env(SYNTH_TOP_LEVEL) 1