Sign in
foss-eda-tools
/
third_party
/
shuttle
/
sky130
/
mpw-002
/
slot-009
/
df3c0153165a1a83ee36fbe789b960a41c4d1572
commit
df3c0153165a1a83ee36fbe789b960a41c4d1572
[
log
]
[
tgz
]
author
AmoghLonkar <alonkar@ucsc.edu>
Tue Jun 15 19:52:26 2021 -0700
committer
AmoghLonkar <alonkar@ucsc.edu>
Tue Jun 15 19:52:26 2021 -0700
tree
801d1a45b2830ef71ad0c77c7ee5fc4263ddaa78
parent
1ccad06612ae94254dc3a170ac15ba68dbb27dd9
[
diff
]
Replaced index with shift
verilog/rtl/openram_testchip.v
[
diff
]
1 file changed
tree: 801d1a45b2830ef71ad0c77c7ee5fc4263ddaa78
.github/
def/
docs/
gds/
lef/
mag/
maglef/
openlane/
signoff/
single_port/
spi/
verilog/
caravel
.gitignore
.gitmodules
info.yaml
LICENSE
Makefile
README.md
README.md
Caravel User Project
:exclamation: Important Note
Please fill in your project documentation in this README.md file
Refer to
README
for this sample project documentation.