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foss-eda-tools/third_party/shuttle/sky130/mpw-002/slot-009/dc757e49cf503fbee2186663408a9e1f294f506b
commit
dc757e49cf503fbee2186663408a9e1f294f506b
[log]
author
AmoghLonkar <alonkar@ucsc.edu>
Thu Jun 10 22:40:49 2021 -0700
committer
AmoghLonkar <alonkar@ucsc.edu>
Thu Jun 10 22:40:49 2021 -0700
tree
ba40da513f17bc1a9f887a07e99f173a91f4cf75
parent
245e98f0ecd2a5a65c668bbc1b9eefa41face456 [diff]
Use new verilog control module
1 file changed
tree: ba40da513f17bc1a9f887a07e99f173a91f4cf75
  1. .github/
  2. chisel/
  3. def/
  4. docs/
  5. gds/
  6. lef/
  7. mag/
  8. maglef/
  9. openlane/
  10. signoff/
  11. single_port/
  12. spi/
  13. verilog/
  14. caravel
  15. .gitignore
  16. .gitmodules
  17. info.yaml
  18. LICENSE
  19. Makefile
  20. README.md
README.md

Caravel User Project

License UPRJ_CI Caravel Build

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for this sample project documentation.