commit d617e93156c0e08af3f4da9ee3b3925994ceb63d
author AmoghLonkar <alonkar@ucsc.edu> Thu Jun 17 11:30:58 2021 -0700
committer AmoghLonkar <alonkar@ucsc.edu> Thu Jun 17 11:30:58 2021 -0700
tree 6d4dda9e9ac70b491e3023c13175467ce60dc4e2
parent 2603fb948e7c06fa91e16ef6d93c7435fbf65546

Fixed index on GPIO output pin range

verilog/rtl/user_project_wrapper.v

diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 9885f23..2d92416 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -105,7 +105,7 @@
    // Only io_out[21] is output
    assign io_oeb = ~(1'b1 << 21);
    // Assign other outputs to 0
-   assign io_out[`MPRJ_IO_PADS:22] = 0;
+   assign io_out[`MPRJ_IO_PADS-1:22] = 0;
    wire     gpio_out;
    assign io_out[21] = gpio_out;
    assign io_out[20:0] = 0;