commit: 7e4a9fd504b492e531174a454b03cf841d69b9fe
[log]
author: AmoghLonkar <alonkar@ucsc.edu>
Sun May 30 23:12:28 2021 -0700
committer: AmoghLonkar <alonkar@ucsc.edu>
Sun May 30 23:12:28 2021 -0700
tree: 96c989c9e325efe2a2b6281e0647314c370b6f14
parent: 5d91038d46b355c4e137e9f6caf23f94a8711071 [diff]

Updated wrapper to include new memory instances

verilog/rtl/user_project_wrapper.v[diff]

1 file changed

tree: 96c989c9e325efe2a2b6281e0647314c370b6f14

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for this sample project documentation.