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foss-eda-tools
/
third_party
/
shuttle
/
sky130
/
mpw-002
/
slot-009
/
ceae645ad4d186e115a0a8a554ebb30d508240eb
commit
ceae645ad4d186e115a0a8a554ebb30d508240eb
[
log
]
[
tgz
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author
AmoghLonkar <alonkar@ucsc.edu>
Thu Jun 10 17:28:36 2021 -0700
committer
AmoghLonkar <alonkar@ucsc.edu>
Thu Jun 10 17:28:36 2021 -0700
tree
26db6e9b5d23e643d34f55a79c1a64bb182f8717
parent
b823400f5a170349131aaf5d3b51dac2d4bedfc1
[
diff
]
GPIO serial loading works, do data transfer
verilog/rtl/openram_testchip.v
[
diff
]
1 file changed
tree: 26db6e9b5d23e643d34f55a79c1a64bb182f8717
.github/
chisel/
def/
docs/
gds/
lef/
mag/
maglef/
openlane/
signoff/
single_port/
spi/
verilog/
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