Merge pull request #2 from AmoghLonkar/feature/floorplan
Feature/floorplan
diff --git a/gds/openram_testchip.gds b/gds/openram_testchip.gds
new file mode 100644
index 0000000..0491c66
--- /dev/null
+++ b/gds/openram_testchip.gds
Binary files differ
diff --git a/gds/sky130_sram_1kbyte_1rw1r_32x256_8.gds b/gds/sky130_sram_1kbyte_1rw1r_32x256_8.gds
new file mode 100644
index 0000000..b093a46
--- /dev/null
+++ b/gds/sky130_sram_1kbyte_1rw1r_32x256_8.gds
Binary files differ
diff --git a/lef/openram_testchip.lef b/lef/openram_testchip.lef
new file mode 100644
index 0000000..f1f6319
--- /dev/null
+++ b/lef/openram_testchip.lef
@@ -0,0 +1,3794 @@
+VERSION 5.7 ;
+ NOWIREEXTENSIONATPIN ON ;
+ DIVIDERCHAR "/" ;
+ BUSBITCHARS "[]" ;
+MACRO openram_testchip
+ CLASS BLOCK ;
+ FOREIGN openram_testchip ;
+ ORIGIN 0.000 0.000 ;
+ SIZE 1200.000 BY 1200.000 ;
+ PIN clock
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 910.890 1196.000 911.170 1200.000 ;
+ END
+ END clock
+ PIN io_gpio_packet[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 193.290 1196.000 193.570 1200.000 ;
+ END
+ END io_gpio_packet[0]
+ PIN io_gpio_packet[10]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 496.440 1200.000 497.040 ;
+ END
+ END io_gpio_packet[10]
+ PIN io_gpio_packet[11]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 1125.440 4.000 1126.040 ;
+ END
+ END io_gpio_packet[11]
+ PIN io_gpio_packet[12]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 172.590 1196.000 172.870 1200.000 ;
+ END
+ END io_gpio_packet[12]
+ PIN io_gpio_packet[13]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 833.040 1200.000 833.640 ;
+ END
+ END io_gpio_packet[13]
+ PIN io_gpio_packet[14]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1129.390 1196.000 1129.670 1200.000 ;
+ END
+ END io_gpio_packet[14]
+ PIN io_gpio_packet[15]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 94.390 0.000 94.670 4.000 ;
+ END
+ END io_gpio_packet[15]
+ PIN io_gpio_packet[16]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 217.640 1200.000 218.240 ;
+ END
+ END io_gpio_packet[16]
+ PIN io_gpio_packet[17]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1062.690 0.000 1062.970 4.000 ;
+ END
+ END io_gpio_packet[17]
+ PIN io_gpio_packet[18]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 775.190 1196.000 775.470 1200.000 ;
+ END
+ END io_gpio_packet[18]
+ PIN io_gpio_packet[19]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 972.440 1200.000 973.040 ;
+ END
+ END io_gpio_packet[19]
+ PIN io_gpio_packet[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1182.290 1196.000 1182.570 1200.000 ;
+ END
+ END io_gpio_packet[1]
+ PIN io_gpio_packet[20]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1166.190 0.000 1166.470 4.000 ;
+ END
+ END io_gpio_packet[20]
+ PIN io_gpio_packet[21]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 683.190 1196.000 683.470 1200.000 ;
+ END
+ END io_gpio_packet[21]
+ PIN io_gpio_packet[22]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 34.040 4.000 34.640 ;
+ END
+ END io_gpio_packet[22]
+ PIN io_gpio_packet[23]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 17.040 1200.000 17.640 ;
+ END
+ END io_gpio_packet[23]
+ PIN io_gpio_packet[24]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 292.440 4.000 293.040 ;
+ END
+ END io_gpio_packet[24]
+ PIN io_gpio_packet[25]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 115.090 0.000 115.370 4.000 ;
+ END
+ END io_gpio_packet[25]
+ PIN io_gpio_packet[26]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 418.240 4.000 418.840 ;
+ END
+ END io_gpio_packet[26]
+ PIN io_gpio_packet[27]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 358.890 1196.000 359.170 1200.000 ;
+ END
+ END io_gpio_packet[27]
+ PIN io_gpio_packet[28]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 802.440 4.000 803.040 ;
+ END
+ END io_gpio_packet[28]
+ PIN io_gpio_packet[29]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 1169.640 4.000 1170.240 ;
+ END
+ END io_gpio_packet[29]
+ PIN io_gpio_packet[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 78.240 1200.000 78.840 ;
+ END
+ END io_gpio_packet[2]
+ PIN io_gpio_packet[30]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 292.190 0.000 292.470 4.000 ;
+ END
+ END io_gpio_packet[30]
+ PIN io_gpio_packet[31]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 563.590 0.000 563.870 4.000 ;
+ END
+ END io_gpio_packet[31]
+ PIN io_gpio_packet[32]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 938.490 0.000 938.770 4.000 ;
+ END
+ END io_gpio_packet[32]
+ PIN io_gpio_packet[33]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 479.440 4.000 480.040 ;
+ END
+ END io_gpio_packet[33]
+ PIN io_gpio_packet[34]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 535.990 1196.000 536.270 1200.000 ;
+ END
+ END io_gpio_packet[34]
+ PIN io_gpio_packet[35]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 863.640 1200.000 864.240 ;
+ END
+ END io_gpio_packet[35]
+ PIN io_gpio_packet[36]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 312.890 0.000 313.170 4.000 ;
+ END
+ END io_gpio_packet[36]
+ PIN io_gpio_packet[37]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 833.040 4.000 833.640 ;
+ END
+ END io_gpio_packet[37]
+ PIN io_gpio_packet[38]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 161.090 1196.000 161.370 1200.000 ;
+ END
+ END io_gpio_packet[38]
+ PIN io_gpio_packet[39]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 788.840 1200.000 789.440 ;
+ END
+ END io_gpio_packet[39]
+ PIN io_gpio_packet[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 952.290 1196.000 952.570 1200.000 ;
+ END
+ END io_gpio_packet[3]
+ PIN io_gpio_packet[40]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 557.640 1200.000 558.240 ;
+ END
+ END io_gpio_packet[40]
+ PIN io_gpio_packet[41]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 1047.240 4.000 1047.840 ;
+ END
+ END io_gpio_packet[41]
+ PIN io_gpio_packet[42]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 441.690 1196.000 441.970 1200.000 ;
+ END
+ END io_gpio_packet[42]
+ PIN io_gpio_packet[43]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 724.240 4.000 724.840 ;
+ END
+ END io_gpio_packet[43]
+ PIN io_gpio_packet[44]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 1173.040 1200.000 1173.640 ;
+ END
+ END io_gpio_packet[44]
+ PIN io_gpio_packet[45]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 708.490 0.000 708.770 4.000 ;
+ END
+ END io_gpio_packet[45]
+ PIN io_gpio_packet[46]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1115.590 0.000 1115.870 4.000 ;
+ END
+ END io_gpio_packet[46]
+ PIN io_gpio_packet[47]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 243.890 1196.000 244.170 1200.000 ;
+ END
+ END io_gpio_packet[47]
+ PIN io_gpio_packet[48]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 370.640 4.000 371.240 ;
+ END
+ END io_gpio_packet[48]
+ PIN io_gpio_packet[49]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 379.590 1196.000 379.870 1200.000 ;
+ END
+ END io_gpio_packet[49]
+ PIN io_gpio_packet[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 816.590 1196.000 816.870 1200.000 ;
+ END
+ END io_gpio_packet[4]
+ PIN io_gpio_packet[50]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 598.090 1196.000 598.370 1200.000 ;
+ END
+ END io_gpio_packet[50]
+ PIN io_gpio_packet[51]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 188.690 0.000 188.970 4.000 ;
+ END
+ END io_gpio_packet[51]
+ PIN io_gpio_packet[52]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 531.390 0.000 531.670 4.000 ;
+ END
+ END io_gpio_packet[52]
+ PIN io_gpio_packet[53]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 57.590 1196.000 57.870 1200.000 ;
+ END
+ END io_gpio_packet[53]
+ PIN io_gpio_packet[54]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 876.390 0.000 876.670 4.000 ;
+ END
+ END io_gpio_packet[54]
+ PIN io_gpio_packet[55]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 540.640 4.000 541.240 ;
+ END
+ END io_gpio_packet[55]
+ PIN io_gpio_packet[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1120.190 1196.000 1120.470 1200.000 ;
+ END
+ END io_gpio_packet[5]
+ PIN io_gpio_packet[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1161.590 1196.000 1161.870 1200.000 ;
+ END
+ END io_gpio_packet[6]
+ PIN io_gpio_packet[7]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 510.040 1200.000 510.640 ;
+ END
+ END io_gpio_packet[7]
+ PIN io_gpio_packet[8]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 435.240 1200.000 435.840 ;
+ END
+ END io_gpio_packet[8]
+ PIN io_gpio_packet[9]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 234.690 1196.000 234.970 1200.000 ;
+ END
+ END io_gpio_packet[9]
+ PIN io_in_select
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 1081.240 1200.000 1081.840 ;
+ END
+ END io_in_select
+ PIN io_logical_analyzer_packet[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 131.190 1196.000 131.470 1200.000 ;
+ END
+ END io_logical_analyzer_packet[0]
+ PIN io_logical_analyzer_packet[10]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 234.640 1200.000 235.240 ;
+ END
+ END io_logical_analyzer_packet[10]
+ PIN io_logical_analyzer_packet[11]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 604.990 0.000 605.270 4.000 ;
+ END
+ END io_logical_analyzer_packet[11]
+ PIN io_logical_analyzer_packet[12]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 173.440 1200.000 174.040 ;
+ END
+ END io_logical_analyzer_packet[12]
+ PIN io_logical_analyzer_packet[13]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1014.390 1196.000 1014.670 1200.000 ;
+ END
+ END io_logical_analyzer_packet[13]
+ PIN io_logical_analyzer_packet[14]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 386.490 0.000 386.770 4.000 ;
+ END
+ END io_logical_analyzer_packet[14]
+ PIN io_logical_analyzer_packet[15]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1074.190 0.000 1074.470 4.000 ;
+ END
+ END io_logical_analyzer_packet[15]
+ PIN io_logical_analyzer_packet[16]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 846.640 4.000 847.240 ;
+ END
+ END io_logical_analyzer_packet[16]
+ PIN io_logical_analyzer_packet[17]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 36.890 1196.000 37.170 1200.000 ;
+ END
+ END io_logical_analyzer_packet[17]
+ PIN io_logical_analyzer_packet[18]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1177.690 0.000 1177.970 4.000 ;
+ END
+ END io_logical_analyzer_packet[18]
+ PIN io_logical_analyzer_packet[19]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 924.840 1200.000 925.440 ;
+ END
+ END io_logical_analyzer_packet[19]
+ PIN io_logical_analyzer_packet[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 649.440 1200.000 650.040 ;
+ END
+ END io_logical_analyzer_packet[1]
+ PIN io_logical_analyzer_packet[20]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 64.490 0.000 64.770 4.000 ;
+ END
+ END io_logical_analyzer_packet[20]
+ PIN io_logical_analyzer_packet[21]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 572.790 0.000 573.070 4.000 ;
+ END
+ END io_logical_analyzer_packet[21]
+ PIN io_logical_analyzer_packet[22]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 464.690 1196.000 464.970 1200.000 ;
+ END
+ END io_logical_analyzer_packet[22]
+ PIN io_logical_analyzer_packet[23]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 663.040 4.000 663.640 ;
+ END
+ END io_logical_analyzer_packet[23]
+ PIN io_logical_analyzer_packet[24]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 931.590 1196.000 931.870 1200.000 ;
+ END
+ END io_logical_analyzer_packet[24]
+ PIN io_logical_analyzer_packet[25]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 416.390 0.000 416.670 4.000 ;
+ END
+ END io_logical_analyzer_packet[25]
+ PIN io_logical_analyzer_packet[26]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 785.440 4.000 786.040 ;
+ END
+ END io_logical_analyzer_packet[26]
+ PIN io_logical_analyzer_packet[27]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 733.790 1196.000 734.070 1200.000 ;
+ END
+ END io_logical_analyzer_packet[27]
+ PIN io_logical_analyzer_packet[28]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 370.640 1200.000 371.240 ;
+ END
+ END io_logical_analyzer_packet[28]
+ PIN io_logical_analyzer_packet[29]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 420.990 1196.000 421.270 1200.000 ;
+ END
+ END io_logical_analyzer_packet[29]
+ PIN io_logical_analyzer_packet[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1051.190 0.000 1051.470 4.000 ;
+ END
+ END io_logical_analyzer_packet[2]
+ PIN io_logical_analyzer_packet[30]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 32.290 0.000 32.570 4.000 ;
+ END
+ END io_logical_analyzer_packet[30]
+ PIN io_logical_analyzer_packet[31]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 771.840 1200.000 772.440 ;
+ END
+ END io_logical_analyzer_packet[31]
+ PIN io_logical_analyzer_packet[32]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1005.190 1196.000 1005.470 1200.000 ;
+ END
+ END io_logical_analyzer_packet[32]
+ PIN io_logical_analyzer_packet[33]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 213.990 1196.000 214.270 1200.000 ;
+ END
+ END io_logical_analyzer_packet[33]
+ PIN io_logical_analyzer_packet[34]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 204.040 1200.000 204.640 ;
+ END
+ END io_logical_analyzer_packet[34]
+ PIN io_logical_analyzer_packet[35]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 663.040 1200.000 663.640 ;
+ END
+ END io_logical_analyzer_packet[35]
+ PIN io_logical_analyzer_packet[36]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 328.990 1196.000 329.270 1200.000 ;
+ END
+ END io_logical_analyzer_packet[36]
+ PIN io_logical_analyzer_packet[37]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 156.440 4.000 157.040 ;
+ END
+ END io_logical_analyzer_packet[37]
+ PIN io_logical_analyzer_packet[38]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 947.690 0.000 947.970 4.000 ;
+ END
+ END io_logical_analyzer_packet[38]
+ PIN io_logical_analyzer_packet[39]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 568.190 1196.000 568.470 1200.000 ;
+ END
+ END io_logical_analyzer_packet[39]
+ PIN io_logical_analyzer_packet[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 407.190 0.000 407.470 4.000 ;
+ END
+ END io_logical_analyzer_packet[3]
+ PIN io_logical_analyzer_packet[40]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 303.690 0.000 303.970 4.000 ;
+ END
+ END io_logical_analyzer_packet[40]
+ PIN io_logical_analyzer_packet[41]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1046.590 1196.000 1046.870 1200.000 ;
+ END
+ END io_logical_analyzer_packet[41]
+ PIN io_logical_analyzer_packet[42]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 692.390 1196.000 692.670 1200.000 ;
+ END
+ END io_logical_analyzer_packet[42]
+ PIN io_logical_analyzer_packet[43]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 802.790 0.000 803.070 4.000 ;
+ END
+ END io_logical_analyzer_packet[43]
+ PIN io_logical_analyzer_packet[44]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 523.640 4.000 524.240 ;
+ END
+ END io_logical_analyzer_packet[44]
+ PIN io_logical_analyzer_packet[45]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 95.240 4.000 95.840 ;
+ END
+ END io_logical_analyzer_packet[45]
+ PIN io_logical_analyzer_packet[46]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 1142.440 1200.000 1143.040 ;
+ END
+ END io_logical_analyzer_packet[46]
+ PIN io_logical_analyzer_packet[47]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 308.290 1196.000 308.570 1200.000 ;
+ END
+ END io_logical_analyzer_packet[47]
+ PIN io_logical_analyzer_packet[48]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 741.240 1200.000 741.840 ;
+ END
+ END io_logical_analyzer_packet[48]
+ PIN io_logical_analyzer_packet[49]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 699.290 0.000 699.570 4.000 ;
+ END
+ END io_logical_analyzer_packet[49]
+ PIN io_logical_analyzer_packet[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 724.590 1196.000 724.870 1200.000 ;
+ END
+ END io_logical_analyzer_packet[4]
+ PIN io_logical_analyzer_packet[50]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 64.640 1200.000 65.240 ;
+ END
+ END io_logical_analyzer_packet[50]
+ PIN io_logical_analyzer_packet[51]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 625.690 0.000 625.970 4.000 ;
+ END
+ END io_logical_analyzer_packet[51]
+ PIN io_logical_analyzer_packet[52]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 741.240 4.000 741.840 ;
+ END
+ END io_logical_analyzer_packet[52]
+ PIN io_logical_analyzer_packet[53]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 357.040 4.000 357.640 ;
+ END
+ END io_logical_analyzer_packet[53]
+ PIN io_logical_analyzer_packet[54]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 979.890 0.000 980.170 4.000 ;
+ END
+ END io_logical_analyzer_packet[54]
+ PIN io_logical_analyzer_packet[55]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 411.790 1196.000 412.070 1200.000 ;
+ END
+ END io_logical_analyzer_packet[55]
+ PIN io_logical_analyzer_packet[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 863.640 4.000 864.240 ;
+ END
+ END io_logical_analyzer_packet[5]
+ PIN io_logical_analyzer_packet[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1156.990 0.000 1157.270 4.000 ;
+ END
+ END io_logical_analyzer_packet[6]
+ PIN io_logical_analyzer_packet[7]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 680.040 4.000 680.640 ;
+ END
+ END io_logical_analyzer_packet[7]
+ PIN io_logical_analyzer_packet[8]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 1108.440 4.000 1109.040 ;
+ END
+ END io_logical_analyzer_packet[8]
+ PIN io_logical_analyzer_packet[9]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 418.240 1200.000 418.840 ;
+ END
+ END io_logical_analyzer_packet[9]
+ PIN io_sram0_connections[0]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1035.090 1196.000 1035.370 1200.000 ;
+ END
+ END io_sram0_connections[0]
+ PIN io_sram0_connections[10]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 959.190 0.000 959.470 4.000 ;
+ END
+ END io_sram0_connections[10]
+ PIN io_sram0_connections[11]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 156.490 0.000 156.770 4.000 ;
+ END
+ END io_sram0_connections[11]
+ PIN io_sram0_connections[12]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 78.240 4.000 78.840 ;
+ END
+ END io_sram0_connections[12]
+ PIN io_sram0_connections[13]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 296.790 1196.000 297.070 1200.000 ;
+ END
+ END io_sram0_connections[13]
+ PIN io_sram0_connections[14]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1140.890 1196.000 1141.170 1200.000 ;
+ END
+ END io_sram0_connections[14]
+ PIN io_sram0_connections[15]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 795.890 1196.000 796.170 1200.000 ;
+ END
+ END io_sram0_connections[15]
+ PIN io_sram0_connections[16]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 78.290 1196.000 78.570 1200.000 ;
+ END
+ END io_sram0_connections[16]
+ PIN io_sram0_connections[17]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 855.690 0.000 855.970 4.000 ;
+ END
+ END io_sram0_connections[17]
+ PIN io_sram0_connections[18]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 844.190 0.000 844.470 4.000 ;
+ END
+ END io_sram0_connections[18]
+ PIN io_sram0_connections[19]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 771.840 4.000 772.440 ;
+ END
+ END io_sram0_connections[19]
+ PIN io_sram0_connections[1]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 724.240 1200.000 724.840 ;
+ END
+ END io_sram0_connections[1]
+ PIN io_sram0_connections[20]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1186.890 0.000 1187.170 4.000 ;
+ END
+ END io_sram0_connections[20]
+ PIN io_sram0_connections[21]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 278.840 1200.000 279.440 ;
+ END
+ END io_sram0_connections[21]
+ PIN io_sram0_connections[22]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 309.440 1200.000 310.040 ;
+ END
+ END io_sram0_connections[22]
+ PIN io_sram0_connections[23]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 432.490 1196.000 432.770 1200.000 ;
+ END
+ END io_sram0_connections[23]
+ PIN io_sram0_connections[24]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 837.290 1196.000 837.570 1200.000 ;
+ END
+ END io_sram0_connections[24]
+ PIN io_sram0_connections[25]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 782.090 0.000 782.370 4.000 ;
+ END
+ END io_sram0_connections[25]
+ PIN io_sram0_connections[26]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 917.790 0.000 918.070 4.000 ;
+ END
+ END io_sram0_connections[26]
+ PIN io_sram0_connections[27]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 630.290 1196.000 630.570 1200.000 ;
+ END
+ END io_sram0_connections[27]
+ PIN io_sram0_connections[28]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 678.590 0.000 678.870 4.000 ;
+ END
+ END io_sram0_connections[28]
+ PIN io_sram0_connections[29]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 637.190 0.000 637.470 4.000 ;
+ END
+ END io_sram0_connections[29]
+ PIN io_sram0_connections[2]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 941.840 4.000 942.440 ;
+ END
+ END io_sram0_connections[2]
+ PIN io_sram0_connections[30]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 401.240 4.000 401.840 ;
+ END
+ END io_sram0_connections[30]
+ PIN io_sram0_connections[31]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 877.240 4.000 877.840 ;
+ END
+ END io_sram0_connections[31]
+ PIN io_sram0_connections[32]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 802.440 1200.000 803.040 ;
+ END
+ END io_sram0_connections[32]
+ PIN io_sram0_connections[33]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 693.640 4.000 694.240 ;
+ END
+ END io_sram0_connections[33]
+ PIN io_sram0_connections[34]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 880.640 1200.000 881.240 ;
+ END
+ END io_sram0_connections[34]
+ PIN io_sram0_connections[35]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 485.390 1196.000 485.670 1200.000 ;
+ END
+ END io_sram0_connections[35]
+ PIN io_sram0_connections[36]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 427.890 0.000 428.170 4.000 ;
+ END
+ END io_sram0_connections[36]
+ PIN io_sram0_connections[37]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 850.040 1200.000 850.640 ;
+ END
+ END io_sram0_connections[37]
+ PIN io_sram0_connections[38]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 1003.040 1200.000 1003.640 ;
+ END
+ END io_sram0_connections[38]
+ PIN io_sram0_connections[39]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 890.190 1196.000 890.470 1200.000 ;
+ END
+ END io_sram0_connections[39]
+ PIN io_sram0_connections[3]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 261.840 4.000 262.440 ;
+ END
+ END io_sram0_connections[3]
+ PIN io_sram0_connections[40]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 3.440 1200.000 4.040 ;
+ END
+ END io_sram0_connections[40]
+ PIN io_sram0_connections[41]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 112.240 1200.000 112.840 ;
+ END
+ END io_sram0_connections[41]
+ PIN io_sram0_connections[42]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 262.290 0.000 262.570 4.000 ;
+ END
+ END io_sram0_connections[42]
+ PIN io_sram0_connections[43]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 202.490 1196.000 202.770 1200.000 ;
+ END
+ END io_sram0_connections[43]
+ PIN io_sram0_connections[44]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 527.040 1200.000 527.640 ;
+ END
+ END io_sram0_connections[44]
+ PIN io_sram0_connections[45]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 460.090 0.000 460.370 4.000 ;
+ END
+ END io_sram0_connections[45]
+ PIN io_sram0_connections[46]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 187.040 1200.000 187.640 ;
+ END
+ END io_sram0_connections[46]
+ PIN io_sram0_connections[47]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 287.590 1196.000 287.870 1200.000 ;
+ END
+ END io_sram0_connections[47]
+ PIN io_sram0_connections[48]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 601.840 4.000 602.440 ;
+ END
+ END io_sram0_connections[48]
+ PIN io_sram0_connections[49]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 506.090 1196.000 506.370 1200.000 ;
+ END
+ END io_sram0_connections[49]
+ PIN io_sram0_connections[4]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 894.240 1200.000 894.840 ;
+ END
+ END io_sram0_connections[4]
+ PIN io_sram0_connections[50]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1067.290 1196.000 1067.570 1200.000 ;
+ END
+ END io_sram0_connections[50]
+ PIN io_sram0_connections[51]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 922.390 1196.000 922.670 1200.000 ;
+ END
+ END io_sram0_connections[51]
+ PIN io_sram0_connections[52]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 391.090 1196.000 391.370 1200.000 ;
+ END
+ END io_sram0_connections[52]
+ PIN io_sram0_connections[53]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1094.890 0.000 1095.170 4.000 ;
+ END
+ END io_sram0_connections[53]
+ PIN io_sram0_connections[54]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 11.590 0.000 11.870 4.000 ;
+ END
+ END io_sram0_connections[54]
+ PIN io_sram0_connections[5]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 108.840 4.000 109.440 ;
+ END
+ END io_sram0_connections[5]
+ PIN io_sram0_connections[6]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 703.890 1196.000 704.170 1200.000 ;
+ END
+ END io_sram0_connections[6]
+ PIN io_sram0_connections[7]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1124.790 0.000 1125.070 4.000 ;
+ END
+ END io_sram0_connections[7]
+ PIN io_sram0_connections[8]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 448.590 0.000 448.870 4.000 ;
+ END
+ END io_sram0_connections[8]
+ PIN io_sram0_connections[9]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 52.990 0.000 53.270 4.000 ;
+ END
+ END io_sram0_connections[9]
+ PIN io_sram0_r0_in[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 431.840 4.000 432.440 ;
+ END
+ END io_sram0_r0_in[0]
+ PIN io_sram0_r0_in[10]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 770.590 0.000 770.870 4.000 ;
+ END
+ END io_sram0_r0_in[10]
+ PIN io_sram0_r0_in[11]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1087.990 1196.000 1088.270 1200.000 ;
+ END
+ END io_sram0_r0_in[11]
+ PIN io_sram0_r0_in[12]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 552.090 0.000 552.370 4.000 ;
+ END
+ END io_sram0_r0_in[12]
+ PIN io_sram0_r0_in[13]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 897.090 0.000 897.370 4.000 ;
+ END
+ END io_sram0_r0_in[13]
+ PIN io_sram0_r0_in[14]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1099.490 1196.000 1099.770 1200.000 ;
+ END
+ END io_sram0_r0_in[14]
+ PIN io_sram0_r0_in[15]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 181.790 1196.000 182.070 1200.000 ;
+ END
+ END io_sram0_r0_in[15]
+ PIN io_sram0_r0_in[16]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 1094.840 4.000 1095.440 ;
+ END
+ END io_sram0_r0_in[16]
+ PIN io_sram0_r0_in[17]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 230.090 0.000 230.370 4.000 ;
+ END
+ END io_sram0_r0_in[17]
+ PIN io_sram0_r0_in[18]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 1186.640 1200.000 1187.240 ;
+ END
+ END io_sram0_r0_in[18]
+ PIN io_sram0_r0_in[19]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1083.390 0.000 1083.670 4.000 ;
+ END
+ END io_sram0_r0_in[19]
+ PIN io_sram0_r0_in[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 142.840 1200.000 143.440 ;
+ END
+ END io_sram0_r0_in[1]
+ PIN io_sram0_r0_in[20]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 200.640 4.000 201.240 ;
+ END
+ END io_sram0_r0_in[20]
+ PIN io_sram0_r0_in[21]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 671.690 1196.000 671.970 1200.000 ;
+ END
+ END io_sram0_r0_in[21]
+ PIN io_sram0_r0_in[22]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 231.240 4.000 231.840 ;
+ END
+ END io_sram0_r0_in[22]
+ PIN io_sram0_r0_in[23]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 23.090 0.000 23.370 4.000 ;
+ END
+ END io_sram0_r0_in[23]
+ PIN io_sram0_r0_in[24]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 639.490 1196.000 639.770 1200.000 ;
+ END
+ END io_sram0_r0_in[24]
+ PIN io_sram0_r0_in[25]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 4.690 1196.000 4.970 1200.000 ;
+ END
+ END io_sram0_r0_in[25]
+ PIN io_sram0_r0_in[26]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 832.690 0.000 832.970 4.000 ;
+ END
+ END io_sram0_r0_in[26]
+ PIN io_sram0_r0_in[27]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 64.640 4.000 65.240 ;
+ END
+ END io_sram0_r0_in[27]
+ PIN io_sram0_r0_in[28]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 540.640 1200.000 541.240 ;
+ END
+ END io_sram0_r0_in[28]
+ PIN io_sram0_r0_in[29]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 749.890 0.000 750.170 4.000 ;
+ END
+ END io_sram0_r0_in[29]
+ PIN io_sram0_r0_in[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 984.490 1196.000 984.770 1200.000 ;
+ END
+ END io_sram0_r0_in[2]
+ PIN io_sram0_r0_in[30]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 885.590 0.000 885.870 4.000 ;
+ END
+ END io_sram0_r0_in[30]
+ PIN io_sram0_r0_in[31]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 98.990 1196.000 99.270 1200.000 ;
+ END
+ END io_sram0_r0_in[31]
+ PIN io_sram0_r0_in[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 786.690 1196.000 786.970 1200.000 ;
+ END
+ END io_sram0_r0_in[3]
+ PIN io_sram0_r0_in[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1108.690 1196.000 1108.970 1200.000 ;
+ END
+ END io_sram0_r0_in[4]
+ PIN io_sram0_r0_in[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2.390 0.000 2.670 4.000 ;
+ END
+ END io_sram0_r0_in[5]
+ PIN io_sram0_r0_in[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 1186.640 4.000 1187.240 ;
+ END
+ END io_sram0_r0_in[6]
+ PIN io_sram0_r0_in[7]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 745.290 1196.000 745.570 1200.000 ;
+ END
+ END io_sram0_r0_in[7]
+ PIN io_sram0_r0_in[8]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 462.440 4.000 463.040 ;
+ END
+ END io_sram0_r0_in[8]
+ PIN io_sram0_r0_in[9]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 963.790 1196.000 964.070 1200.000 ;
+ END
+ END io_sram0_r0_in[9]
+ PIN io_sram0_rw_in[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 754.840 4.000 755.440 ;
+ END
+ END io_sram0_rw_in[0]
+ PIN io_sram0_rw_in[10]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 17.040 4.000 17.640 ;
+ END
+ END io_sram0_rw_in[10]
+ PIN io_sram0_rw_in[11]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 924.840 4.000 925.440 ;
+ END
+ END io_sram0_rw_in[11]
+ PIN io_sram0_rw_in[12]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 901.690 1196.000 901.970 1200.000 ;
+ END
+ END io_sram0_rw_in[12]
+ PIN io_sram0_rw_in[13]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 584.840 4.000 585.440 ;
+ END
+ END io_sram0_rw_in[13]
+ PIN io_sram0_rw_in[14]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 439.390 0.000 439.670 4.000 ;
+ END
+ END io_sram0_rw_in[14]
+ PIN io_sram0_rw_in[15]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 609.590 1196.000 609.870 1200.000 ;
+ END
+ END io_sram0_rw_in[15]
+ PIN io_sram0_rw_in[16]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 401.240 1200.000 401.840 ;
+ END
+ END io_sram0_rw_in[16]
+ PIN io_sram0_rw_in[17]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 187.040 4.000 187.640 ;
+ END
+ END io_sram0_rw_in[17]
+ PIN io_sram0_rw_in[18]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 110.490 1196.000 110.770 1200.000 ;
+ END
+ END io_sram0_rw_in[18]
+ PIN io_sram0_rw_in[19]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 667.090 0.000 667.370 4.000 ;
+ END
+ END io_sram0_rw_in[19]
+ PIN io_sram0_rw_in[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1041.990 0.000 1042.270 4.000 ;
+ END
+ END io_sram0_rw_in[1]
+ PIN io_sram0_rw_in[20]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 89.790 1196.000 90.070 1200.000 ;
+ END
+ END io_sram0_rw_in[20]
+ PIN io_sram0_rw_in[21]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1191.490 1196.000 1191.770 1200.000 ;
+ END
+ END io_sram0_rw_in[21]
+ PIN io_sram0_rw_in[22]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 729.190 0.000 729.470 4.000 ;
+ END
+ END io_sram0_rw_in[22]
+ PIN io_sram0_rw_in[23]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 400.290 1196.000 400.570 1200.000 ;
+ END
+ END io_sram0_rw_in[23]
+ PIN io_sram0_rw_in[24]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 276.090 1196.000 276.370 1200.000 ;
+ END
+ END io_sram0_rw_in[24]
+ PIN io_sram0_rw_in[25]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 577.390 1196.000 577.670 1200.000 ;
+ END
+ END io_sram0_rw_in[25]
+ PIN io_sram0_rw_in[26]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 266.890 1196.000 267.170 1200.000 ;
+ END
+ END io_sram0_rw_in[26]
+ PIN io_sram0_rw_in[27]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 69.090 1196.000 69.370 1200.000 ;
+ END
+ END io_sram0_rw_in[27]
+ PIN io_sram0_rw_in[28]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 34.040 1200.000 34.640 ;
+ END
+ END io_sram0_rw_in[28]
+ PIN io_sram0_rw_in[29]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 941.840 1200.000 942.440 ;
+ END
+ END io_sram0_rw_in[29]
+ PIN io_sram0_rw_in[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 554.240 4.000 554.840 ;
+ END
+ END io_sram0_rw_in[2]
+ PIN io_sram0_rw_in[30]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 986.040 1200.000 986.640 ;
+ END
+ END io_sram0_rw_in[30]
+ PIN io_sram0_rw_in[31]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 816.040 4.000 816.640 ;
+ END
+ END io_sram0_rw_in[31]
+ PIN io_sram0_rw_in[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 754.490 1196.000 754.770 1200.000 ;
+ END
+ END io_sram0_rw_in[3]
+ PIN io_sram0_rw_in[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 710.640 4.000 711.240 ;
+ END
+ END io_sram0_rw_in[4]
+ PIN io_sram0_rw_in[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 571.240 1200.000 571.840 ;
+ END
+ END io_sram0_rw_in[5]
+ PIN io_sram0_rw_in[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 649.440 4.000 650.040 ;
+ END
+ END io_sram0_rw_in[6]
+ PIN io_sram0_rw_in[7]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1104.090 0.000 1104.370 4.000 ;
+ END
+ END io_sram0_rw_in[7]
+ PIN io_sram0_rw_in[8]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 1016.640 1200.000 1017.240 ;
+ END
+ END io_sram0_rw_in[8]
+ PIN io_sram0_rw_in[9]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 282.990 0.000 283.270 4.000 ;
+ END
+ END io_sram0_rw_in[9]
+ PIN io_sram1_connections[0]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 593.490 0.000 593.770 4.000 ;
+ END
+ END io_sram1_connections[0]
+ PIN io_sram1_connections[10]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 47.640 1200.000 48.240 ;
+ END
+ END io_sram1_connections[10]
+ PIN io_sram1_connections[11]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 848.790 1196.000 849.070 1200.000 ;
+ END
+ END io_sram1_connections[11]
+ PIN io_sram1_connections[12]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 1064.240 4.000 1064.840 ;
+ END
+ END io_sram1_connections[12]
+ PIN io_sram1_connections[13]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 333.590 0.000 333.870 4.000 ;
+ END
+ END io_sram1_connections[13]
+ PIN io_sram1_connections[14]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1030.490 0.000 1030.770 4.000 ;
+ END
+ END io_sram1_connections[14]
+ PIN io_sram1_connections[15]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 151.890 1196.000 152.170 1200.000 ;
+ END
+ END io_sram1_connections[15]
+ PIN io_sram1_connections[16]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 48.390 1196.000 48.670 1200.000 ;
+ END
+ END io_sram1_connections[16]
+ PIN io_sram1_connections[17]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 47.640 4.000 48.240 ;
+ END
+ END io_sram1_connections[17]
+ PIN io_sram1_connections[18]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 828.090 1196.000 828.370 1200.000 ;
+ END
+ END io_sram1_connections[18]
+ PIN io_sram1_connections[19]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 1094.840 1200.000 1095.440 ;
+ END
+ END io_sram1_connections[19]
+ PIN io_sram1_connections[1]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 125.840 1200.000 126.440 ;
+ END
+ END io_sram1_connections[1]
+ PIN io_sram1_connections[20]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 374.990 0.000 375.270 4.000 ;
+ END
+ END io_sram1_connections[20]
+ PIN io_sram1_connections[21]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 601.840 1200.000 602.440 ;
+ END
+ END io_sram1_connections[21]
+ PIN io_sram1_connections[22]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 547.490 1196.000 547.770 1200.000 ;
+ END
+ END io_sram1_connections[22]
+ PIN io_sram1_connections[23]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 510.040 4.000 510.640 ;
+ END
+ END io_sram1_connections[23]
+ PIN io_sram1_connections[24]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 489.990 0.000 490.270 4.000 ;
+ END
+ END io_sram1_connections[24]
+ PIN io_sram1_connections[25]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 955.440 1200.000 956.040 ;
+ END
+ END io_sram1_connections[25]
+ PIN io_sram1_connections[26]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 584.290 0.000 584.570 4.000 ;
+ END
+ END io_sram1_connections[26]
+ PIN io_sram1_connections[27]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 615.440 4.000 616.040 ;
+ END
+ END io_sram1_connections[27]
+ PIN io_sram1_connections[28]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 1003.040 4.000 1003.640 ;
+ END
+ END io_sram1_connections[28]
+ PIN io_sram1_connections[29]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 119.690 1196.000 119.970 1200.000 ;
+ END
+ END io_sram1_connections[29]
+ PIN io_sram1_connections[2]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 340.040 1200.000 340.640 ;
+ END
+ END io_sram1_connections[2]
+ PIN io_sram1_connections[30]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 326.440 4.000 327.040 ;
+ END
+ END io_sram1_connections[30]
+ PIN io_sram1_connections[31]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 448.840 1200.000 449.440 ;
+ END
+ END io_sram1_connections[31]
+ PIN io_sram1_connections[32]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1009.790 0.000 1010.070 4.000 ;
+ END
+ END io_sram1_connections[32]
+ PIN io_sram1_connections[33]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 479.440 1200.000 480.040 ;
+ END
+ END io_sram1_connections[33]
+ PIN io_sram1_connections[34]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 370.390 1196.000 370.670 1200.000 ;
+ END
+ END io_sram1_connections[34]
+ PIN io_sram1_connections[35]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 309.440 4.000 310.040 ;
+ END
+ END io_sram1_connections[35]
+ PIN io_sram1_connections[36]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 43.790 0.000 44.070 4.000 ;
+ END
+ END io_sram1_connections[36]
+ PIN io_sram1_connections[37]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 526.790 1196.000 527.070 1200.000 ;
+ END
+ END io_sram1_connections[37]
+ PIN io_sram1_connections[38]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 105.890 0.000 106.170 4.000 ;
+ END
+ END io_sram1_connections[38]
+ PIN io_sram1_connections[39]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 618.840 1200.000 619.440 ;
+ END
+ END io_sram1_connections[39]
+ PIN io_sram1_connections[3]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 197.890 0.000 198.170 4.000 ;
+ END
+ END io_sram1_connections[3]
+ PIN io_sram1_connections[40]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 1111.840 1200.000 1112.440 ;
+ END
+ END io_sram1_connections[40]
+ PIN io_sram1_connections[41]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 217.640 4.000 218.240 ;
+ END
+ END io_sram1_connections[41]
+ PIN io_sram1_connections[42]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 494.590 1196.000 494.870 1200.000 ;
+ END
+ END io_sram1_connections[42]
+ PIN io_sram1_connections[43]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 571.240 4.000 571.840 ;
+ END
+ END io_sram1_connections[43]
+ PIN io_sram1_connections[44]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 465.840 1200.000 466.440 ;
+ END
+ END io_sram1_connections[44]
+ PIN io_sram1_connections[45]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 968.390 0.000 968.670 4.000 ;
+ END
+ END io_sram1_connections[45]
+ PIN io_sram1_connections[46]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 295.840 1200.000 296.440 ;
+ END
+ END io_sram1_connections[46]
+ PIN io_sram1_connections[47]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 317.490 1196.000 317.770 1200.000 ;
+ END
+ END io_sram1_connections[47]
+ PIN io_sram1_connections[48]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 139.440 4.000 140.040 ;
+ END
+ END io_sram1_connections[48]
+ PIN io_sram1_connections[49]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 126.590 0.000 126.870 4.000 ;
+ END
+ END io_sram1_connections[49]
+ PIN io_sram1_connections[4]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 986.040 4.000 986.640 ;
+ END
+ END io_sram1_connections[4]
+ PIN io_sram1_connections[50]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 265.240 1200.000 265.840 ;
+ END
+ END io_sram1_connections[50]
+ PIN io_sram1_connections[51]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 791.290 0.000 791.570 4.000 ;
+ END
+ END io_sram1_connections[51]
+ PIN io_sram1_connections[52]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 1156.040 1200.000 1156.640 ;
+ END
+ END io_sram1_connections[52]
+ PIN io_sram1_connections[53]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 248.240 4.000 248.840 ;
+ END
+ END io_sram1_connections[53]
+ PIN io_sram1_connections[54]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 167.990 0.000 168.270 4.000 ;
+ END
+ END io_sram1_connections[54]
+ PIN io_sram1_connections[5]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 271.490 0.000 271.770 4.000 ;
+ END
+ END io_sram1_connections[5]
+ PIN io_sram1_connections[6]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 542.890 0.000 543.170 4.000 ;
+ END
+ END io_sram1_connections[6]
+ PIN io_sram1_connections[7]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1136.290 0.000 1136.570 4.000 ;
+ END
+ END io_sram1_connections[7]
+ PIN io_sram1_connections[8]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 448.840 4.000 449.440 ;
+ END
+ END io_sram1_connections[8]
+ PIN io_sram1_connections[9]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 660.190 1196.000 660.470 1200.000 ;
+ END
+ END io_sram1_connections[9]
+ PIN io_sram1_ro_in[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 357.040 1200.000 357.640 ;
+ END
+ END io_sram1_ro_in[0]
+ PIN io_sram1_ro_in[10]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 1139.040 4.000 1139.640 ;
+ END
+ END io_sram1_ro_in[10]
+ PIN io_sram1_ro_in[11]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 1125.440 1200.000 1126.040 ;
+ END
+ END io_sram1_ro_in[11]
+ PIN io_sram1_ro_in[12]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 125.840 4.000 126.440 ;
+ END
+ END io_sram1_ro_in[12]
+ PIN io_sram1_ro_in[13]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 1016.640 4.000 1017.240 ;
+ END
+ END io_sram1_ro_in[13]
+ PIN io_sram1_ro_in[14]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 223.190 1196.000 223.470 1200.000 ;
+ END
+ END io_sram1_ro_in[14]
+ PIN io_sram1_ro_in[15]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 740.690 0.000 740.970 4.000 ;
+ END
+ END io_sram1_ro_in[15]
+ PIN io_sram1_ro_in[16]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 501.490 0.000 501.770 4.000 ;
+ END
+ END io_sram1_ro_in[16]
+ PIN io_sram1_ro_in[17]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 1156.040 4.000 1156.640 ;
+ END
+ END io_sram1_ro_in[17]
+ PIN io_sram1_ro_in[18]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 972.440 4.000 973.040 ;
+ END
+ END io_sram1_ro_in[18]
+ PIN io_sram1_ro_in[19]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 1033.640 1200.000 1034.240 ;
+ END
+ END io_sram1_ro_in[19]
+ PIN io_sram1_ro_in[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 657.890 0.000 658.170 4.000 ;
+ END
+ END io_sram1_ro_in[1]
+ PIN io_sram1_ro_in[20]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 387.640 1200.000 388.240 ;
+ END
+ END io_sram1_ro_in[20]
+ PIN io_sram1_ro_in[21]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 140.390 1196.000 140.670 1200.000 ;
+ END
+ END io_sram1_ro_in[21]
+ PIN io_sram1_ro_in[22]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 473.890 1196.000 474.170 1200.000 ;
+ END
+ END io_sram1_ro_in[22]
+ PIN io_sram1_ro_in[23]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 819.440 1200.000 820.040 ;
+ END
+ END io_sram1_ro_in[23]
+ PIN io_sram1_ro_in[24]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 650.990 1196.000 651.270 1200.000 ;
+ END
+ END io_sram1_ro_in[24]
+ PIN io_sram1_ro_in[25]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 135.790 0.000 136.070 4.000 ;
+ END
+ END io_sram1_ro_in[25]
+ PIN io_sram1_ro_in[26]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 220.890 0.000 221.170 4.000 ;
+ END
+ END io_sram1_ro_in[26]
+ PIN io_sram1_ro_in[27]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 1064.240 1200.000 1064.840 ;
+ END
+ END io_sram1_ro_in[27]
+ PIN io_sram1_ro_in[28]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 387.640 4.000 388.240 ;
+ END
+ END io_sram1_ro_in[28]
+ PIN io_sram1_ro_in[29]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 989.090 0.000 989.370 4.000 ;
+ END
+ END io_sram1_ro_in[29]
+ PIN io_sram1_ro_in[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 823.490 0.000 823.770 4.000 ;
+ END
+ END io_sram1_ro_in[2]
+ PIN io_sram1_ro_in[30]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 248.240 1200.000 248.840 ;
+ END
+ END io_sram1_ro_in[30]
+ PIN io_sram1_ro_in[31]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 278.840 4.000 279.440 ;
+ END
+ END io_sram1_ro_in[31]
+ PIN io_sram1_ro_in[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 255.390 1196.000 255.670 1200.000 ;
+ END
+ END io_sram1_ro_in[3]
+ PIN io_sram1_ro_in[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 493.040 4.000 493.640 ;
+ END
+ END io_sram1_ro_in[4]
+ PIN io_sram1_ro_in[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 811.990 0.000 812.270 4.000 ;
+ END
+ END io_sram1_ro_in[5]
+ PIN io_sram1_ro_in[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 25.390 1196.000 25.670 1200.000 ;
+ END
+ END io_sram1_ro_in[6]
+ PIN io_sram1_ro_in[7]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1150.090 1196.000 1150.370 1200.000 ;
+ END
+ END io_sram1_ro_in[7]
+ PIN io_sram1_ro_in[8]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 326.440 1200.000 327.040 ;
+ END
+ END io_sram1_ro_in[8]
+ PIN io_sram1_ro_in[9]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 869.490 1196.000 869.770 1200.000 ;
+ END
+ END io_sram1_ro_in[9]
+ PIN io_sram1_rw_in[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 926.990 0.000 927.270 4.000 ;
+ END
+ END io_sram1_rw_in[0]
+ PIN io_sram1_rw_in[10]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 687.790 0.000 688.070 4.000 ;
+ END
+ END io_sram1_rw_in[10]
+ PIN io_sram1_rw_in[11]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 618.790 1196.000 619.070 1200.000 ;
+ END
+ END io_sram1_rw_in[11]
+ PIN io_sram1_rw_in[12]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 906.290 0.000 906.570 4.000 ;
+ END
+ END io_sram1_rw_in[12]
+ PIN io_sram1_rw_in[13]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 209.390 0.000 209.670 4.000 ;
+ END
+ END io_sram1_rw_in[13]
+ PIN io_sram1_rw_in[14]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 73.690 0.000 73.970 4.000 ;
+ END
+ END io_sram1_rw_in[14]
+ PIN io_sram1_rw_in[15]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 345.090 0.000 345.370 4.000 ;
+ END
+ END io_sram1_rw_in[15]
+ PIN io_sram1_rw_in[16]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 588.890 1196.000 589.170 1200.000 ;
+ END
+ END io_sram1_rw_in[16]
+ PIN io_sram1_rw_in[17]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 1050.640 1200.000 1051.240 ;
+ END
+ END io_sram1_rw_in[17]
+ PIN io_sram1_rw_in[18]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 680.040 1200.000 680.640 ;
+ END
+ END io_sram1_rw_in[18]
+ PIN io_sram1_rw_in[19]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 907.840 4.000 908.440 ;
+ END
+ END io_sram1_rw_in[19]
+ PIN io_sram1_rw_in[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 761.390 0.000 761.670 4.000 ;
+ END
+ END io_sram1_rw_in[1]
+ PIN io_sram1_rw_in[20]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 710.640 1200.000 711.240 ;
+ END
+ END io_sram1_rw_in[20]
+ PIN io_sram1_rw_in[21]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 156.440 1200.000 157.040 ;
+ END
+ END io_sram1_rw_in[21]
+ PIN io_sram1_rw_in[22]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 324.390 0.000 324.670 4.000 ;
+ END
+ END io_sram1_rw_in[22]
+ PIN io_sram1_rw_in[23]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 515.290 1196.000 515.570 1200.000 ;
+ END
+ END io_sram1_rw_in[23]
+ PIN io_sram1_rw_in[24]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 177.190 0.000 177.470 4.000 ;
+ END
+ END io_sram1_rw_in[24]
+ PIN io_sram1_rw_in[25]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 588.240 1200.000 588.840 ;
+ END
+ END io_sram1_rw_in[25]
+ PIN io_sram1_rw_in[26]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 911.240 1200.000 911.840 ;
+ END
+ END io_sram1_rw_in[26]
+ PIN io_sram1_rw_in[27]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 943.090 1196.000 943.370 1200.000 ;
+ END
+ END io_sram1_rw_in[27]
+ PIN io_sram1_rw_in[28]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1055.790 1196.000 1056.070 1200.000 ;
+ END
+ END io_sram1_rw_in[28]
+ PIN io_sram1_rw_in[29]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1170.790 1196.000 1171.070 1200.000 ;
+ END
+ END io_sram1_rw_in[29]
+ PIN io_sram1_rw_in[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 878.690 1196.000 878.970 1200.000 ;
+ END
+ END io_sram1_rw_in[2]
+ PIN io_sram1_rw_in[30]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 453.190 1196.000 453.470 1200.000 ;
+ END
+ END io_sram1_rw_in[30]
+ PIN io_sram1_rw_in[31]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 85.190 0.000 85.470 4.000 ;
+ END
+ END io_sram1_rw_in[31]
+ PIN io_sram1_rw_in[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 170.040 4.000 170.640 ;
+ END
+ END io_sram1_rw_in[3]
+ PIN io_sram1_rw_in[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 556.690 1196.000 556.970 1200.000 ;
+ END
+ END io_sram1_rw_in[4]
+ PIN io_sram1_rw_in[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 1077.840 4.000 1078.440 ;
+ END
+ END io_sram1_rw_in[5]
+ PIN io_sram1_rw_in[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 1033.640 4.000 1034.240 ;
+ END
+ END io_sram1_rw_in[6]
+ PIN io_sram1_rw_in[7]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 522.190 0.000 522.470 4.000 ;
+ END
+ END io_sram1_rw_in[7]
+ PIN io_sram1_rw_in[8]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 693.640 1200.000 694.240 ;
+ END
+ END io_sram1_rw_in[8]
+ PIN io_sram1_rw_in[9]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 864.890 0.000 865.170 4.000 ;
+ END
+ END io_sram1_rw_in[9]
+ PIN io_sram_data[0]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1145.490 0.000 1145.770 4.000 ;
+ END
+ END io_sram_data[0]
+ PIN io_sram_data[10]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 340.040 4.000 340.640 ;
+ END
+ END io_sram_data[10]
+ PIN io_sram_data[11]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 632.440 4.000 633.040 ;
+ END
+ END io_sram_data[11]
+ PIN io_sram_data[12]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 758.240 1200.000 758.840 ;
+ END
+ END io_sram_data[12]
+ PIN io_sram_data[13]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 147.290 0.000 147.570 4.000 ;
+ END
+ END io_sram_data[13]
+ PIN io_sram_data[14]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1076.490 1196.000 1076.770 1200.000 ;
+ END
+ END io_sram_data[14]
+ PIN io_sram_data[15]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 857.990 1196.000 858.270 1200.000 ;
+ END
+ END io_sram_data[15]
+ PIN io_sram_data[16]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 765.990 1196.000 766.270 1200.000 ;
+ END
+ END io_sram_data[16]
+ PIN io_sram_data[17]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1025.890 1196.000 1026.170 1200.000 ;
+ END
+ END io_sram_data[17]
+ PIN io_sram_data[18]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 241.590 0.000 241.870 4.000 ;
+ END
+ END io_sram_data[18]
+ PIN io_sram_data[19]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 972.990 1196.000 973.270 1200.000 ;
+ END
+ END io_sram_data[19]
+ PIN io_sram_data[1]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 365.790 0.000 366.070 4.000 ;
+ END
+ END io_sram_data[1]
+ PIN io_sram_data[20]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 480.790 0.000 481.070 4.000 ;
+ END
+ END io_sram_data[20]
+ PIN io_sram_data[21]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 510.690 0.000 510.970 4.000 ;
+ END
+ END io_sram_data[21]
+ PIN io_sram_data[22]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 807.390 1196.000 807.670 1200.000 ;
+ END
+ END io_sram_data[22]
+ PIN io_sram_data[23]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 16.190 1196.000 16.470 1200.000 ;
+ END
+ END io_sram_data[23]
+ PIN io_sram_data[24]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 894.240 4.000 894.840 ;
+ END
+ END io_sram_data[24]
+ PIN io_sram_data[25]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 614.190 0.000 614.470 4.000 ;
+ END
+ END io_sram_data[25]
+ PIN io_sram_data[26]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 395.690 0.000 395.970 4.000 ;
+ END
+ END io_sram_data[26]
+ PIN io_sram_data[27]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1000.590 0.000 1000.870 4.000 ;
+ END
+ END io_sram_data[27]
+ PIN io_sram_data[28]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 646.390 0.000 646.670 4.000 ;
+ END
+ END io_sram_data[28]
+ PIN io_sram_data[29]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 719.990 0.000 720.270 4.000 ;
+ END
+ END io_sram_data[29]
+ PIN io_sram_data[2]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 95.240 1200.000 95.840 ;
+ END
+ END io_sram_data[2]
+ PIN io_sram_data[30]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 250.790 0.000 251.070 4.000 ;
+ END
+ END io_sram_data[30]
+ PIN io_sram_data[31]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 955.440 4.000 956.040 ;
+ END
+ END io_sram_data[31]
+ PIN io_sram_data[3]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 338.190 1196.000 338.470 1200.000 ;
+ END
+ END io_sram_data[3]
+ PIN io_sram_data[4]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 993.690 1196.000 993.970 1200.000 ;
+ END
+ END io_sram_data[4]
+ PIN io_sram_data[5]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 469.290 0.000 469.570 4.000 ;
+ END
+ END io_sram_data[5]
+ PIN io_sram_data[6]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 349.690 1196.000 349.970 1200.000 ;
+ END
+ END io_sram_data[6]
+ PIN io_sram_data[7]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1021.290 0.000 1021.570 4.000 ;
+ END
+ END io_sram_data[7]
+ PIN io_sram_data[8]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1196.000 632.440 1200.000 633.040 ;
+ END
+ END io_sram_data[8]
+ PIN io_sram_data[9]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 354.290 0.000 354.570 4.000 ;
+ END
+ END io_sram_data[9]
+ PIN reset
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 713.090 1196.000 713.370 1200.000 ;
+ END
+ END reset
+ PIN VPWR
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 1096.240 10.640 1097.840 1188.880 ;
+ END
+ END VPWR
+ PIN VPWR
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 942.640 10.640 944.240 1188.880 ;
+ END
+ END VPWR
+ PIN VPWR
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 789.040 10.640 790.640 1188.880 ;
+ END
+ END VPWR
+ PIN VPWR
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 635.440 10.640 637.040 1188.880 ;
+ END
+ END VPWR
+ PIN VPWR
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 481.840 10.640 483.440 1188.880 ;
+ END
+ END VPWR
+ PIN VPWR
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 328.240 10.640 329.840 1188.880 ;
+ END
+ END VPWR
+ PIN VPWR
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 174.640 10.640 176.240 1188.880 ;
+ END
+ END VPWR
+ PIN VPWR
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 21.040 10.640 22.640 1188.880 ;
+ END
+ END VPWR
+ PIN VPWR
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT 5.520 1098.750 1194.160 1100.350 ;
+ END
+ END VPWR
+ PIN VPWR
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT 5.520 945.570 1194.160 947.170 ;
+ END
+ END VPWR
+ PIN VPWR
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT 5.520 792.390 1194.160 793.990 ;
+ END
+ END VPWR
+ PIN VPWR
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT 5.520 639.210 1194.160 640.810 ;
+ END
+ END VPWR
+ PIN VPWR
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT 5.520 486.030 1194.160 487.630 ;
+ END
+ END VPWR
+ PIN VPWR
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT 5.520 332.850 1194.160 334.450 ;
+ END
+ END VPWR
+ PIN VPWR
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT 5.520 179.670 1194.160 181.270 ;
+ END
+ END VPWR
+ PIN VPWR
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT 5.520 26.490 1194.160 28.090 ;
+ END
+ END VPWR
+ PIN VGND
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 1173.040 10.640 1174.640 1188.880 ;
+ END
+ END VGND
+ PIN VGND
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 1019.440 10.640 1021.040 1188.880 ;
+ END
+ END VGND
+ PIN VGND
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 865.840 10.640 867.440 1188.880 ;
+ END
+ END VGND
+ PIN VGND
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 712.240 10.640 713.840 1188.880 ;
+ END
+ END VGND
+ PIN VGND
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 558.640 10.640 560.240 1188.880 ;
+ END
+ END VGND
+ PIN VGND
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 405.040 10.640 406.640 1188.880 ;
+ END
+ END VGND
+ PIN VGND
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 251.440 10.640 253.040 1188.880 ;
+ END
+ END VGND
+ PIN VGND
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 97.840 10.640 99.440 1188.880 ;
+ END
+ END VGND
+ PIN VGND
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT 5.520 1175.340 1194.160 1176.940 ;
+ END
+ END VGND
+ PIN VGND
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT 5.520 1022.160 1194.160 1023.760 ;
+ END
+ END VGND
+ PIN VGND
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT 5.520 868.980 1194.160 870.580 ;
+ END
+ END VGND
+ PIN VGND
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT 5.520 715.800 1194.160 717.400 ;
+ END
+ END VGND
+ PIN VGND
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT 5.520 562.620 1194.160 564.220 ;
+ END
+ END VGND
+ PIN VGND
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT 5.520 409.440 1194.160 411.040 ;
+ END
+ END VGND
+ PIN VGND
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT 5.520 256.260 1194.160 257.860 ;
+ END
+ END VGND
+ PIN VGND
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT 5.520 103.080 1194.160 104.680 ;
+ END
+ END VGND
+ OBS
+ LAYER li1 ;
+ RECT 7.045 6.545 1192.175 1193.995 ;
+ LAYER met1 ;
+ RECT 2.370 6.515 1194.160 1194.040 ;
+ LAYER met2 ;
+ RECT 2.400 1195.720 4.410 1196.000 ;
+ RECT 5.250 1195.720 15.910 1196.000 ;
+ RECT 16.750 1195.720 25.110 1196.000 ;
+ RECT 25.950 1195.720 36.610 1196.000 ;
+ RECT 37.450 1195.720 48.110 1196.000 ;
+ RECT 48.950 1195.720 57.310 1196.000 ;
+ RECT 58.150 1195.720 68.810 1196.000 ;
+ RECT 69.650 1195.720 78.010 1196.000 ;
+ RECT 78.850 1195.720 89.510 1196.000 ;
+ RECT 90.350 1195.720 98.710 1196.000 ;
+ RECT 99.550 1195.720 110.210 1196.000 ;
+ RECT 111.050 1195.720 119.410 1196.000 ;
+ RECT 120.250 1195.720 130.910 1196.000 ;
+ RECT 131.750 1195.720 140.110 1196.000 ;
+ RECT 140.950 1195.720 151.610 1196.000 ;
+ RECT 152.450 1195.720 160.810 1196.000 ;
+ RECT 161.650 1195.720 172.310 1196.000 ;
+ RECT 173.150 1195.720 181.510 1196.000 ;
+ RECT 182.350 1195.720 193.010 1196.000 ;
+ RECT 193.850 1195.720 202.210 1196.000 ;
+ RECT 203.050 1195.720 213.710 1196.000 ;
+ RECT 214.550 1195.720 222.910 1196.000 ;
+ RECT 223.750 1195.720 234.410 1196.000 ;
+ RECT 235.250 1195.720 243.610 1196.000 ;
+ RECT 244.450 1195.720 255.110 1196.000 ;
+ RECT 255.950 1195.720 266.610 1196.000 ;
+ RECT 267.450 1195.720 275.810 1196.000 ;
+ RECT 276.650 1195.720 287.310 1196.000 ;
+ RECT 288.150 1195.720 296.510 1196.000 ;
+ RECT 297.350 1195.720 308.010 1196.000 ;
+ RECT 308.850 1195.720 317.210 1196.000 ;
+ RECT 318.050 1195.720 328.710 1196.000 ;
+ RECT 329.550 1195.720 337.910 1196.000 ;
+ RECT 338.750 1195.720 349.410 1196.000 ;
+ RECT 350.250 1195.720 358.610 1196.000 ;
+ RECT 359.450 1195.720 370.110 1196.000 ;
+ RECT 370.950 1195.720 379.310 1196.000 ;
+ RECT 380.150 1195.720 390.810 1196.000 ;
+ RECT 391.650 1195.720 400.010 1196.000 ;
+ RECT 400.850 1195.720 411.510 1196.000 ;
+ RECT 412.350 1195.720 420.710 1196.000 ;
+ RECT 421.550 1195.720 432.210 1196.000 ;
+ RECT 433.050 1195.720 441.410 1196.000 ;
+ RECT 442.250 1195.720 452.910 1196.000 ;
+ RECT 453.750 1195.720 464.410 1196.000 ;
+ RECT 465.250 1195.720 473.610 1196.000 ;
+ RECT 474.450 1195.720 485.110 1196.000 ;
+ RECT 485.950 1195.720 494.310 1196.000 ;
+ RECT 495.150 1195.720 505.810 1196.000 ;
+ RECT 506.650 1195.720 515.010 1196.000 ;
+ RECT 515.850 1195.720 526.510 1196.000 ;
+ RECT 527.350 1195.720 535.710 1196.000 ;
+ RECT 536.550 1195.720 547.210 1196.000 ;
+ RECT 548.050 1195.720 556.410 1196.000 ;
+ RECT 557.250 1195.720 567.910 1196.000 ;
+ RECT 568.750 1195.720 577.110 1196.000 ;
+ RECT 577.950 1195.720 588.610 1196.000 ;
+ RECT 589.450 1195.720 597.810 1196.000 ;
+ RECT 598.650 1195.720 609.310 1196.000 ;
+ RECT 610.150 1195.720 618.510 1196.000 ;
+ RECT 619.350 1195.720 630.010 1196.000 ;
+ RECT 630.850 1195.720 639.210 1196.000 ;
+ RECT 640.050 1195.720 650.710 1196.000 ;
+ RECT 651.550 1195.720 659.910 1196.000 ;
+ RECT 660.750 1195.720 671.410 1196.000 ;
+ RECT 672.250 1195.720 682.910 1196.000 ;
+ RECT 683.750 1195.720 692.110 1196.000 ;
+ RECT 692.950 1195.720 703.610 1196.000 ;
+ RECT 704.450 1195.720 712.810 1196.000 ;
+ RECT 713.650 1195.720 724.310 1196.000 ;
+ RECT 725.150 1195.720 733.510 1196.000 ;
+ RECT 734.350 1195.720 745.010 1196.000 ;
+ RECT 745.850 1195.720 754.210 1196.000 ;
+ RECT 755.050 1195.720 765.710 1196.000 ;
+ RECT 766.550 1195.720 774.910 1196.000 ;
+ RECT 775.750 1195.720 786.410 1196.000 ;
+ RECT 787.250 1195.720 795.610 1196.000 ;
+ RECT 796.450 1195.720 807.110 1196.000 ;
+ RECT 807.950 1195.720 816.310 1196.000 ;
+ RECT 817.150 1195.720 827.810 1196.000 ;
+ RECT 828.650 1195.720 837.010 1196.000 ;
+ RECT 837.850 1195.720 848.510 1196.000 ;
+ RECT 849.350 1195.720 857.710 1196.000 ;
+ RECT 858.550 1195.720 869.210 1196.000 ;
+ RECT 870.050 1195.720 878.410 1196.000 ;
+ RECT 879.250 1195.720 889.910 1196.000 ;
+ RECT 890.750 1195.720 901.410 1196.000 ;
+ RECT 902.250 1195.720 910.610 1196.000 ;
+ RECT 911.450 1195.720 922.110 1196.000 ;
+ RECT 922.950 1195.720 931.310 1196.000 ;
+ RECT 932.150 1195.720 942.810 1196.000 ;
+ RECT 943.650 1195.720 952.010 1196.000 ;
+ RECT 952.850 1195.720 963.510 1196.000 ;
+ RECT 964.350 1195.720 972.710 1196.000 ;
+ RECT 973.550 1195.720 984.210 1196.000 ;
+ RECT 985.050 1195.720 993.410 1196.000 ;
+ RECT 994.250 1195.720 1004.910 1196.000 ;
+ RECT 1005.750 1195.720 1014.110 1196.000 ;
+ RECT 1014.950 1195.720 1025.610 1196.000 ;
+ RECT 1026.450 1195.720 1034.810 1196.000 ;
+ RECT 1035.650 1195.720 1046.310 1196.000 ;
+ RECT 1047.150 1195.720 1055.510 1196.000 ;
+ RECT 1056.350 1195.720 1067.010 1196.000 ;
+ RECT 1067.850 1195.720 1076.210 1196.000 ;
+ RECT 1077.050 1195.720 1087.710 1196.000 ;
+ RECT 1088.550 1195.720 1099.210 1196.000 ;
+ RECT 1100.050 1195.720 1108.410 1196.000 ;
+ RECT 1109.250 1195.720 1119.910 1196.000 ;
+ RECT 1120.750 1195.720 1129.110 1196.000 ;
+ RECT 1129.950 1195.720 1140.610 1196.000 ;
+ RECT 1141.450 1195.720 1149.810 1196.000 ;
+ RECT 1150.650 1195.720 1161.310 1196.000 ;
+ RECT 1162.150 1195.720 1170.510 1196.000 ;
+ RECT 1171.350 1195.720 1182.010 1196.000 ;
+ RECT 1182.850 1195.720 1191.210 1196.000 ;
+ RECT 1192.050 1195.720 1192.220 1196.000 ;
+ RECT 2.400 4.280 1192.220 1195.720 ;
+ RECT 2.950 3.555 11.310 4.280 ;
+ RECT 12.150 3.555 22.810 4.280 ;
+ RECT 23.650 3.555 32.010 4.280 ;
+ RECT 32.850 3.555 43.510 4.280 ;
+ RECT 44.350 3.555 52.710 4.280 ;
+ RECT 53.550 3.555 64.210 4.280 ;
+ RECT 65.050 3.555 73.410 4.280 ;
+ RECT 74.250 3.555 84.910 4.280 ;
+ RECT 85.750 3.555 94.110 4.280 ;
+ RECT 94.950 3.555 105.610 4.280 ;
+ RECT 106.450 3.555 114.810 4.280 ;
+ RECT 115.650 3.555 126.310 4.280 ;
+ RECT 127.150 3.555 135.510 4.280 ;
+ RECT 136.350 3.555 147.010 4.280 ;
+ RECT 147.850 3.555 156.210 4.280 ;
+ RECT 157.050 3.555 167.710 4.280 ;
+ RECT 168.550 3.555 176.910 4.280 ;
+ RECT 177.750 3.555 188.410 4.280 ;
+ RECT 189.250 3.555 197.610 4.280 ;
+ RECT 198.450 3.555 209.110 4.280 ;
+ RECT 209.950 3.555 220.610 4.280 ;
+ RECT 221.450 3.555 229.810 4.280 ;
+ RECT 230.650 3.555 241.310 4.280 ;
+ RECT 242.150 3.555 250.510 4.280 ;
+ RECT 251.350 3.555 262.010 4.280 ;
+ RECT 262.850 3.555 271.210 4.280 ;
+ RECT 272.050 3.555 282.710 4.280 ;
+ RECT 283.550 3.555 291.910 4.280 ;
+ RECT 292.750 3.555 303.410 4.280 ;
+ RECT 304.250 3.555 312.610 4.280 ;
+ RECT 313.450 3.555 324.110 4.280 ;
+ RECT 324.950 3.555 333.310 4.280 ;
+ RECT 334.150 3.555 344.810 4.280 ;
+ RECT 345.650 3.555 354.010 4.280 ;
+ RECT 354.850 3.555 365.510 4.280 ;
+ RECT 366.350 3.555 374.710 4.280 ;
+ RECT 375.550 3.555 386.210 4.280 ;
+ RECT 387.050 3.555 395.410 4.280 ;
+ RECT 396.250 3.555 406.910 4.280 ;
+ RECT 407.750 3.555 416.110 4.280 ;
+ RECT 416.950 3.555 427.610 4.280 ;
+ RECT 428.450 3.555 439.110 4.280 ;
+ RECT 439.950 3.555 448.310 4.280 ;
+ RECT 449.150 3.555 459.810 4.280 ;
+ RECT 460.650 3.555 469.010 4.280 ;
+ RECT 469.850 3.555 480.510 4.280 ;
+ RECT 481.350 3.555 489.710 4.280 ;
+ RECT 490.550 3.555 501.210 4.280 ;
+ RECT 502.050 3.555 510.410 4.280 ;
+ RECT 511.250 3.555 521.910 4.280 ;
+ RECT 522.750 3.555 531.110 4.280 ;
+ RECT 531.950 3.555 542.610 4.280 ;
+ RECT 543.450 3.555 551.810 4.280 ;
+ RECT 552.650 3.555 563.310 4.280 ;
+ RECT 564.150 3.555 572.510 4.280 ;
+ RECT 573.350 3.555 584.010 4.280 ;
+ RECT 584.850 3.555 593.210 4.280 ;
+ RECT 594.050 3.555 604.710 4.280 ;
+ RECT 605.550 3.555 613.910 4.280 ;
+ RECT 614.750 3.555 625.410 4.280 ;
+ RECT 626.250 3.555 636.910 4.280 ;
+ RECT 637.750 3.555 646.110 4.280 ;
+ RECT 646.950 3.555 657.610 4.280 ;
+ RECT 658.450 3.555 666.810 4.280 ;
+ RECT 667.650 3.555 678.310 4.280 ;
+ RECT 679.150 3.555 687.510 4.280 ;
+ RECT 688.350 3.555 699.010 4.280 ;
+ RECT 699.850 3.555 708.210 4.280 ;
+ RECT 709.050 3.555 719.710 4.280 ;
+ RECT 720.550 3.555 728.910 4.280 ;
+ RECT 729.750 3.555 740.410 4.280 ;
+ RECT 741.250 3.555 749.610 4.280 ;
+ RECT 750.450 3.555 761.110 4.280 ;
+ RECT 761.950 3.555 770.310 4.280 ;
+ RECT 771.150 3.555 781.810 4.280 ;
+ RECT 782.650 3.555 791.010 4.280 ;
+ RECT 791.850 3.555 802.510 4.280 ;
+ RECT 803.350 3.555 811.710 4.280 ;
+ RECT 812.550 3.555 823.210 4.280 ;
+ RECT 824.050 3.555 832.410 4.280 ;
+ RECT 833.250 3.555 843.910 4.280 ;
+ RECT 844.750 3.555 855.410 4.280 ;
+ RECT 856.250 3.555 864.610 4.280 ;
+ RECT 865.450 3.555 876.110 4.280 ;
+ RECT 876.950 3.555 885.310 4.280 ;
+ RECT 886.150 3.555 896.810 4.280 ;
+ RECT 897.650 3.555 906.010 4.280 ;
+ RECT 906.850 3.555 917.510 4.280 ;
+ RECT 918.350 3.555 926.710 4.280 ;
+ RECT 927.550 3.555 938.210 4.280 ;
+ RECT 939.050 3.555 947.410 4.280 ;
+ RECT 948.250 3.555 958.910 4.280 ;
+ RECT 959.750 3.555 968.110 4.280 ;
+ RECT 968.950 3.555 979.610 4.280 ;
+ RECT 980.450 3.555 988.810 4.280 ;
+ RECT 989.650 3.555 1000.310 4.280 ;
+ RECT 1001.150 3.555 1009.510 4.280 ;
+ RECT 1010.350 3.555 1021.010 4.280 ;
+ RECT 1021.850 3.555 1030.210 4.280 ;
+ RECT 1031.050 3.555 1041.710 4.280 ;
+ RECT 1042.550 3.555 1050.910 4.280 ;
+ RECT 1051.750 3.555 1062.410 4.280 ;
+ RECT 1063.250 3.555 1073.910 4.280 ;
+ RECT 1074.750 3.555 1083.110 4.280 ;
+ RECT 1083.950 3.555 1094.610 4.280 ;
+ RECT 1095.450 3.555 1103.810 4.280 ;
+ RECT 1104.650 3.555 1115.310 4.280 ;
+ RECT 1116.150 3.555 1124.510 4.280 ;
+ RECT 1125.350 3.555 1136.010 4.280 ;
+ RECT 1136.850 3.555 1145.210 4.280 ;
+ RECT 1146.050 3.555 1156.710 4.280 ;
+ RECT 1157.550 3.555 1165.910 4.280 ;
+ RECT 1166.750 3.555 1177.410 4.280 ;
+ RECT 1178.250 3.555 1186.610 4.280 ;
+ RECT 1187.450 3.555 1192.220 4.280 ;
+ LAYER met3 ;
+ RECT 4.000 1187.640 1196.000 1188.805 ;
+ RECT 4.400 1186.240 1195.600 1187.640 ;
+ RECT 4.000 1174.040 1196.000 1186.240 ;
+ RECT 4.000 1172.640 1195.600 1174.040 ;
+ RECT 4.000 1170.640 1196.000 1172.640 ;
+ RECT 4.400 1169.240 1196.000 1170.640 ;
+ RECT 4.000 1157.040 1196.000 1169.240 ;
+ RECT 4.400 1155.640 1195.600 1157.040 ;
+ RECT 4.000 1143.440 1196.000 1155.640 ;
+ RECT 4.000 1142.040 1195.600 1143.440 ;
+ RECT 4.000 1140.040 1196.000 1142.040 ;
+ RECT 4.400 1138.640 1196.000 1140.040 ;
+ RECT 4.000 1126.440 1196.000 1138.640 ;
+ RECT 4.400 1125.040 1195.600 1126.440 ;
+ RECT 4.000 1112.840 1196.000 1125.040 ;
+ RECT 4.000 1111.440 1195.600 1112.840 ;
+ RECT 4.000 1109.440 1196.000 1111.440 ;
+ RECT 4.400 1108.040 1196.000 1109.440 ;
+ RECT 4.000 1095.840 1196.000 1108.040 ;
+ RECT 4.400 1094.440 1195.600 1095.840 ;
+ RECT 4.000 1082.240 1196.000 1094.440 ;
+ RECT 4.000 1080.840 1195.600 1082.240 ;
+ RECT 4.000 1078.840 1196.000 1080.840 ;
+ RECT 4.400 1077.440 1196.000 1078.840 ;
+ RECT 4.000 1065.240 1196.000 1077.440 ;
+ RECT 4.400 1063.840 1195.600 1065.240 ;
+ RECT 4.000 1051.640 1196.000 1063.840 ;
+ RECT 4.000 1050.240 1195.600 1051.640 ;
+ RECT 4.000 1048.240 1196.000 1050.240 ;
+ RECT 4.400 1046.840 1196.000 1048.240 ;
+ RECT 4.000 1034.640 1196.000 1046.840 ;
+ RECT 4.400 1033.240 1195.600 1034.640 ;
+ RECT 4.000 1017.640 1196.000 1033.240 ;
+ RECT 4.400 1016.240 1195.600 1017.640 ;
+ RECT 4.000 1004.040 1196.000 1016.240 ;
+ RECT 4.400 1002.640 1195.600 1004.040 ;
+ RECT 4.000 987.040 1196.000 1002.640 ;
+ RECT 4.400 985.640 1195.600 987.040 ;
+ RECT 4.000 973.440 1196.000 985.640 ;
+ RECT 4.400 972.040 1195.600 973.440 ;
+ RECT 4.000 956.440 1196.000 972.040 ;
+ RECT 4.400 955.040 1195.600 956.440 ;
+ RECT 4.000 942.840 1196.000 955.040 ;
+ RECT 4.400 941.440 1195.600 942.840 ;
+ RECT 4.000 925.840 1196.000 941.440 ;
+ RECT 4.400 924.440 1195.600 925.840 ;
+ RECT 4.000 912.240 1196.000 924.440 ;
+ RECT 4.000 910.840 1195.600 912.240 ;
+ RECT 4.000 908.840 1196.000 910.840 ;
+ RECT 4.400 907.440 1196.000 908.840 ;
+ RECT 4.000 895.240 1196.000 907.440 ;
+ RECT 4.400 893.840 1195.600 895.240 ;
+ RECT 4.000 881.640 1196.000 893.840 ;
+ RECT 4.000 880.240 1195.600 881.640 ;
+ RECT 4.000 878.240 1196.000 880.240 ;
+ RECT 4.400 876.840 1196.000 878.240 ;
+ RECT 4.000 864.640 1196.000 876.840 ;
+ RECT 4.400 863.240 1195.600 864.640 ;
+ RECT 4.000 851.040 1196.000 863.240 ;
+ RECT 4.000 849.640 1195.600 851.040 ;
+ RECT 4.000 847.640 1196.000 849.640 ;
+ RECT 4.400 846.240 1196.000 847.640 ;
+ RECT 4.000 834.040 1196.000 846.240 ;
+ RECT 4.400 832.640 1195.600 834.040 ;
+ RECT 4.000 820.440 1196.000 832.640 ;
+ RECT 4.000 819.040 1195.600 820.440 ;
+ RECT 4.000 817.040 1196.000 819.040 ;
+ RECT 4.400 815.640 1196.000 817.040 ;
+ RECT 4.000 803.440 1196.000 815.640 ;
+ RECT 4.400 802.040 1195.600 803.440 ;
+ RECT 4.000 789.840 1196.000 802.040 ;
+ RECT 4.000 788.440 1195.600 789.840 ;
+ RECT 4.000 786.440 1196.000 788.440 ;
+ RECT 4.400 785.040 1196.000 786.440 ;
+ RECT 4.000 772.840 1196.000 785.040 ;
+ RECT 4.400 771.440 1195.600 772.840 ;
+ RECT 4.000 759.240 1196.000 771.440 ;
+ RECT 4.000 757.840 1195.600 759.240 ;
+ RECT 4.000 755.840 1196.000 757.840 ;
+ RECT 4.400 754.440 1196.000 755.840 ;
+ RECT 4.000 742.240 1196.000 754.440 ;
+ RECT 4.400 740.840 1195.600 742.240 ;
+ RECT 4.000 725.240 1196.000 740.840 ;
+ RECT 4.400 723.840 1195.600 725.240 ;
+ RECT 4.000 711.640 1196.000 723.840 ;
+ RECT 4.400 710.240 1195.600 711.640 ;
+ RECT 4.000 694.640 1196.000 710.240 ;
+ RECT 4.400 693.240 1195.600 694.640 ;
+ RECT 4.000 681.040 1196.000 693.240 ;
+ RECT 4.400 679.640 1195.600 681.040 ;
+ RECT 4.000 664.040 1196.000 679.640 ;
+ RECT 4.400 662.640 1195.600 664.040 ;
+ RECT 4.000 650.440 1196.000 662.640 ;
+ RECT 4.400 649.040 1195.600 650.440 ;
+ RECT 4.000 633.440 1196.000 649.040 ;
+ RECT 4.400 632.040 1195.600 633.440 ;
+ RECT 4.000 619.840 1196.000 632.040 ;
+ RECT 4.000 618.440 1195.600 619.840 ;
+ RECT 4.000 616.440 1196.000 618.440 ;
+ RECT 4.400 615.040 1196.000 616.440 ;
+ RECT 4.000 602.840 1196.000 615.040 ;
+ RECT 4.400 601.440 1195.600 602.840 ;
+ RECT 4.000 589.240 1196.000 601.440 ;
+ RECT 4.000 587.840 1195.600 589.240 ;
+ RECT 4.000 585.840 1196.000 587.840 ;
+ RECT 4.400 584.440 1196.000 585.840 ;
+ RECT 4.000 572.240 1196.000 584.440 ;
+ RECT 4.400 570.840 1195.600 572.240 ;
+ RECT 4.000 558.640 1196.000 570.840 ;
+ RECT 4.000 557.240 1195.600 558.640 ;
+ RECT 4.000 555.240 1196.000 557.240 ;
+ RECT 4.400 553.840 1196.000 555.240 ;
+ RECT 4.000 541.640 1196.000 553.840 ;
+ RECT 4.400 540.240 1195.600 541.640 ;
+ RECT 4.000 528.040 1196.000 540.240 ;
+ RECT 4.000 526.640 1195.600 528.040 ;
+ RECT 4.000 524.640 1196.000 526.640 ;
+ RECT 4.400 523.240 1196.000 524.640 ;
+ RECT 4.000 511.040 1196.000 523.240 ;
+ RECT 4.400 509.640 1195.600 511.040 ;
+ RECT 4.000 497.440 1196.000 509.640 ;
+ RECT 4.000 496.040 1195.600 497.440 ;
+ RECT 4.000 494.040 1196.000 496.040 ;
+ RECT 4.400 492.640 1196.000 494.040 ;
+ RECT 4.000 480.440 1196.000 492.640 ;
+ RECT 4.400 479.040 1195.600 480.440 ;
+ RECT 4.000 466.840 1196.000 479.040 ;
+ RECT 4.000 465.440 1195.600 466.840 ;
+ RECT 4.000 463.440 1196.000 465.440 ;
+ RECT 4.400 462.040 1196.000 463.440 ;
+ RECT 4.000 449.840 1196.000 462.040 ;
+ RECT 4.400 448.440 1195.600 449.840 ;
+ RECT 4.000 436.240 1196.000 448.440 ;
+ RECT 4.000 434.840 1195.600 436.240 ;
+ RECT 4.000 432.840 1196.000 434.840 ;
+ RECT 4.400 431.440 1196.000 432.840 ;
+ RECT 4.000 419.240 1196.000 431.440 ;
+ RECT 4.400 417.840 1195.600 419.240 ;
+ RECT 4.000 402.240 1196.000 417.840 ;
+ RECT 4.400 400.840 1195.600 402.240 ;
+ RECT 4.000 388.640 1196.000 400.840 ;
+ RECT 4.400 387.240 1195.600 388.640 ;
+ RECT 4.000 371.640 1196.000 387.240 ;
+ RECT 4.400 370.240 1195.600 371.640 ;
+ RECT 4.000 358.040 1196.000 370.240 ;
+ RECT 4.400 356.640 1195.600 358.040 ;
+ RECT 4.000 341.040 1196.000 356.640 ;
+ RECT 4.400 339.640 1195.600 341.040 ;
+ RECT 4.000 327.440 1196.000 339.640 ;
+ RECT 4.400 326.040 1195.600 327.440 ;
+ RECT 4.000 310.440 1196.000 326.040 ;
+ RECT 4.400 309.040 1195.600 310.440 ;
+ RECT 4.000 296.840 1196.000 309.040 ;
+ RECT 4.000 295.440 1195.600 296.840 ;
+ RECT 4.000 293.440 1196.000 295.440 ;
+ RECT 4.400 292.040 1196.000 293.440 ;
+ RECT 4.000 279.840 1196.000 292.040 ;
+ RECT 4.400 278.440 1195.600 279.840 ;
+ RECT 4.000 266.240 1196.000 278.440 ;
+ RECT 4.000 264.840 1195.600 266.240 ;
+ RECT 4.000 262.840 1196.000 264.840 ;
+ RECT 4.400 261.440 1196.000 262.840 ;
+ RECT 4.000 249.240 1196.000 261.440 ;
+ RECT 4.400 247.840 1195.600 249.240 ;
+ RECT 4.000 235.640 1196.000 247.840 ;
+ RECT 4.000 234.240 1195.600 235.640 ;
+ RECT 4.000 232.240 1196.000 234.240 ;
+ RECT 4.400 230.840 1196.000 232.240 ;
+ RECT 4.000 218.640 1196.000 230.840 ;
+ RECT 4.400 217.240 1195.600 218.640 ;
+ RECT 4.000 205.040 1196.000 217.240 ;
+ RECT 4.000 203.640 1195.600 205.040 ;
+ RECT 4.000 201.640 1196.000 203.640 ;
+ RECT 4.400 200.240 1196.000 201.640 ;
+ RECT 4.000 188.040 1196.000 200.240 ;
+ RECT 4.400 186.640 1195.600 188.040 ;
+ RECT 4.000 174.440 1196.000 186.640 ;
+ RECT 4.000 173.040 1195.600 174.440 ;
+ RECT 4.000 171.040 1196.000 173.040 ;
+ RECT 4.400 169.640 1196.000 171.040 ;
+ RECT 4.000 157.440 1196.000 169.640 ;
+ RECT 4.400 156.040 1195.600 157.440 ;
+ RECT 4.000 143.840 1196.000 156.040 ;
+ RECT 4.000 142.440 1195.600 143.840 ;
+ RECT 4.000 140.440 1196.000 142.440 ;
+ RECT 4.400 139.040 1196.000 140.440 ;
+ RECT 4.000 126.840 1196.000 139.040 ;
+ RECT 4.400 125.440 1195.600 126.840 ;
+ RECT 4.000 113.240 1196.000 125.440 ;
+ RECT 4.000 111.840 1195.600 113.240 ;
+ RECT 4.000 109.840 1196.000 111.840 ;
+ RECT 4.400 108.440 1196.000 109.840 ;
+ RECT 4.000 96.240 1196.000 108.440 ;
+ RECT 4.400 94.840 1195.600 96.240 ;
+ RECT 4.000 79.240 1196.000 94.840 ;
+ RECT 4.400 77.840 1195.600 79.240 ;
+ RECT 4.000 65.640 1196.000 77.840 ;
+ RECT 4.400 64.240 1195.600 65.640 ;
+ RECT 4.000 48.640 1196.000 64.240 ;
+ RECT 4.400 47.240 1195.600 48.640 ;
+ RECT 4.000 35.040 1196.000 47.240 ;
+ RECT 4.400 33.640 1195.600 35.040 ;
+ RECT 4.000 18.040 1196.000 33.640 ;
+ RECT 4.400 16.640 1195.600 18.040 ;
+ RECT 4.000 4.440 1196.000 16.640 ;
+ RECT 4.000 3.575 1195.600 4.440 ;
+ END
+END openram_testchip
+END LIBRARY
+
diff --git a/lef/sky130_sram_1kbyte_1rw1r_32x256_8.lef b/lef/sky130_sram_1kbyte_1rw1r_32x256_8.lef
new file mode 100644
index 0000000..11337b2
--- /dev/null
+++ b/lef/sky130_sram_1kbyte_1rw1r_32x256_8.lef
@@ -0,0 +1,1078 @@
+VERSION 5.4 ;
+NAMESCASESENSITIVE ON ;
+BUSBITCHARS "[]" ;
+DIVIDERCHAR "/" ;
+UNITS
+ DATABASE MICRONS 2000 ;
+END UNITS
+MACRO sky130_sram_1kbyte_1rw1r_32x256_8
+ CLASS BLOCK ;
+ SIZE 477.06 BY 396.14 ;
+ SYMMETRY X Y R90 ;
+ PIN din0[0]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 105.4 0.0 105.78 0.38 ;
+ END
+ END din0[0]
+ PIN din0[1]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 111.52 0.0 111.9 0.38 ;
+ END
+ END din0[1]
+ PIN din0[2]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 116.96 0.0 117.34 0.38 ;
+ END
+ END din0[2]
+ PIN din0[3]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 123.76 0.0 124.14 0.38 ;
+ END
+ END din0[3]
+ PIN din0[4]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 129.2 0.0 129.58 0.38 ;
+ END
+ END din0[4]
+ PIN din0[5]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 134.64 0.0 135.02 0.38 ;
+ END
+ END din0[5]
+ PIN din0[6]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 140.08 0.0 140.46 0.38 ;
+ END
+ END din0[6]
+ PIN din0[7]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 146.88 0.0 147.26 0.38 ;
+ END
+ END din0[7]
+ PIN din0[8]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 152.32 0.0 152.7 0.38 ;
+ END
+ END din0[8]
+ PIN din0[9]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 157.76 0.0 158.14 0.38 ;
+ END
+ END din0[9]
+ PIN din0[10]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 163.88 0.0 164.26 0.38 ;
+ END
+ END din0[10]
+ PIN din0[11]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 169.32 0.0 169.7 0.38 ;
+ END
+ END din0[11]
+ PIN din0[12]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 176.12 0.0 176.5 0.38 ;
+ END
+ END din0[12]
+ PIN din0[13]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 181.56 0.0 181.94 0.38 ;
+ END
+ END din0[13]
+ PIN din0[14]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 187.0 0.0 187.38 0.38 ;
+ END
+ END din0[14]
+ PIN din0[15]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 193.12 0.0 193.5 0.38 ;
+ END
+ END din0[15]
+ PIN din0[16]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 199.92 0.0 200.3 0.38 ;
+ END
+ END din0[16]
+ PIN din0[17]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 205.36 0.0 205.74 0.38 ;
+ END
+ END din0[17]
+ PIN din0[18]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 210.8 0.0 211.18 0.38 ;
+ END
+ END din0[18]
+ PIN din0[19]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 216.24 0.0 216.62 0.38 ;
+ END
+ END din0[19]
+ PIN din0[20]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 223.04 0.0 223.42 0.38 ;
+ END
+ END din0[20]
+ PIN din0[21]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 228.48 0.0 228.86 0.38 ;
+ END
+ END din0[21]
+ PIN din0[22]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 233.92 0.0 234.3 0.38 ;
+ END
+ END din0[22]
+ PIN din0[23]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 240.04 0.0 240.42 0.38 ;
+ END
+ END din0[23]
+ PIN din0[24]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 245.48 0.0 245.86 0.38 ;
+ END
+ END din0[24]
+ PIN din0[25]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 252.28 0.0 252.66 0.38 ;
+ END
+ END din0[25]
+ PIN din0[26]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 257.72 0.0 258.1 0.38 ;
+ END
+ END din0[26]
+ PIN din0[27]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 263.16 0.0 263.54 0.38 ;
+ END
+ END din0[27]
+ PIN din0[28]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 268.6 0.0 268.98 0.38 ;
+ END
+ END din0[28]
+ PIN din0[29]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 274.72 0.0 275.1 0.38 ;
+ END
+ END din0[29]
+ PIN din0[30]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 281.52 0.0 281.9 0.38 ;
+ END
+ END din0[30]
+ PIN din0[31]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 286.96 0.0 287.34 0.38 ;
+ END
+ END din0[31]
+ PIN addr0[0]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 76.16 0.0 76.54 0.38 ;
+ END
+ END addr0[0]
+ PIN addr0[1]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 127.84 0.38 128.22 ;
+ END
+ END addr0[1]
+ PIN addr0[2]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 136.0 0.38 136.38 ;
+ END
+ END addr0[2]
+ PIN addr0[3]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 141.44 0.38 141.82 ;
+ END
+ END addr0[3]
+ PIN addr0[4]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 149.6 0.38 149.98 ;
+ END
+ END addr0[4]
+ PIN addr0[5]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 155.04 0.38 155.42 ;
+ END
+ END addr0[5]
+ PIN addr0[6]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 163.88 0.38 164.26 ;
+ END
+ END addr0[6]
+ PIN addr0[7]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 169.32 0.38 169.7 ;
+ END
+ END addr0[7]
+ PIN addr1[0]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 395.76 395.76 396.14 396.14 ;
+ END
+ END addr1[0]
+ PIN addr1[1]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 476.68 82.28 477.06 82.66 ;
+ END
+ END addr1[1]
+ PIN addr1[2]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 476.68 74.12 477.06 74.5 ;
+ END
+ END addr1[2]
+ PIN addr1[3]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 476.68 68.0 477.06 68.38 ;
+ END
+ END addr1[3]
+ PIN addr1[4]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 414.12 0.0 414.5 0.38 ;
+ END
+ END addr1[4]
+ PIN addr1[5]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 412.08 0.0 412.46 0.38 ;
+ END
+ END addr1[5]
+ PIN addr1[6]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 412.76 0.0 413.14 0.38 ;
+ END
+ END addr1[6]
+ PIN addr1[7]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 413.44 0.0 413.82 0.38 ;
+ END
+ END addr1[7]
+ PIN csb0
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 25.84 0.38 26.22 ;
+ END
+ END csb0
+ PIN csb1
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 476.68 382.16 477.06 382.54 ;
+ END
+ END csb1
+ PIN web0
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 34.68 0.38 35.06 ;
+ END
+ END web0
+ PIN clk0
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 27.88 0.0 28.26 0.38 ;
+ END
+ END clk0
+ PIN clk1
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 448.8 395.76 449.18 396.14 ;
+ END
+ END clk1
+ PIN wmask0[0]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 82.28 0.0 82.66 0.38 ;
+ END
+ END wmask0[0]
+ PIN wmask0[1]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 87.72 0.0 88.1 0.38 ;
+ END
+ END wmask0[1]
+ PIN wmask0[2]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 94.52 0.0 94.9 0.38 ;
+ END
+ END wmask0[2]
+ PIN wmask0[3]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 99.28 0.0 99.66 0.38 ;
+ END
+ END wmask0[3]
+ PIN dout0[0]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 138.04 0.0 138.42 0.38 ;
+ END
+ END dout0[0]
+ PIN dout0[1]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 144.84 0.0 145.22 0.38 ;
+ END
+ END dout0[1]
+ PIN dout0[2]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 150.28 0.0 150.66 0.38 ;
+ END
+ END dout0[2]
+ PIN dout0[3]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 158.44 0.0 158.82 0.38 ;
+ END
+ END dout0[3]
+ PIN dout0[4]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 164.56 0.0 164.94 0.38 ;
+ END
+ END dout0[4]
+ PIN dout0[5]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 170.68 0.0 171.06 0.38 ;
+ END
+ END dout0[5]
+ PIN dout0[6]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 176.8 0.0 177.18 0.38 ;
+ END
+ END dout0[6]
+ PIN dout0[7]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 182.92 0.0 183.3 0.38 ;
+ END
+ END dout0[7]
+ PIN dout0[8]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 187.68 0.0 188.06 0.38 ;
+ END
+ END dout0[8]
+ PIN dout0[9]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 195.16 0.0 195.54 0.38 ;
+ END
+ END dout0[9]
+ PIN dout0[10]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 201.96 0.0 202.34 0.38 ;
+ END
+ END dout0[10]
+ PIN dout0[11]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 208.08 0.0 208.46 0.38 ;
+ END
+ END dout0[11]
+ PIN dout0[12]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 214.2 0.0 214.58 0.38 ;
+ END
+ END dout0[12]
+ PIN dout0[13]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 220.32 0.0 220.7 0.38 ;
+ END
+ END dout0[13]
+ PIN dout0[14]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 226.44 0.0 226.82 0.38 ;
+ END
+ END dout0[14]
+ PIN dout0[15]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 231.88 0.0 232.26 0.38 ;
+ END
+ END dout0[15]
+ PIN dout0[16]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 238.0 0.0 238.38 0.38 ;
+ END
+ END dout0[16]
+ PIN dout0[17]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 244.12 0.0 244.5 0.38 ;
+ END
+ END dout0[17]
+ PIN dout0[18]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 251.6 0.0 251.98 0.38 ;
+ END
+ END dout0[18]
+ PIN dout0[19]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 255.68 0.0 256.06 0.38 ;
+ END
+ END dout0[19]
+ PIN dout0[20]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 264.52 0.0 264.9 0.38 ;
+ END
+ END dout0[20]
+ PIN dout0[21]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 270.64 0.0 271.02 0.38 ;
+ END
+ END dout0[21]
+ PIN dout0[22]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 276.76 0.0 277.14 0.38 ;
+ END
+ END dout0[22]
+ PIN dout0[23]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 282.88 0.0 283.26 0.38 ;
+ END
+ END dout0[23]
+ PIN dout0[24]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 287.64 0.0 288.02 0.38 ;
+ END
+ END dout0[24]
+ PIN dout0[25]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 295.12 0.0 295.5 0.38 ;
+ END
+ END dout0[25]
+ PIN dout0[26]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 301.24 0.0 301.62 0.38 ;
+ END
+ END dout0[26]
+ PIN dout0[27]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 308.04 0.0 308.42 0.38 ;
+ END
+ END dout0[27]
+ PIN dout0[28]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 314.16 0.0 314.54 0.38 ;
+ END
+ END dout0[28]
+ PIN dout0[29]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 320.28 0.0 320.66 0.38 ;
+ END
+ END dout0[29]
+ PIN dout0[30]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 326.4 0.0 326.78 0.38 ;
+ END
+ END dout0[30]
+ PIN dout0[31]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 332.52 0.0 332.9 0.38 ;
+ END
+ END dout0[31]
+ PIN dout1[0]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 139.4 395.76 139.78 396.14 ;
+ END
+ END dout1[0]
+ PIN dout1[1]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 146.2 395.76 146.58 396.14 ;
+ END
+ END dout1[1]
+ PIN dout1[2]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 151.64 395.76 152.02 396.14 ;
+ END
+ END dout1[2]
+ PIN dout1[3]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 158.44 395.76 158.82 396.14 ;
+ END
+ END dout1[3]
+ PIN dout1[4]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 164.56 395.76 164.94 396.14 ;
+ END
+ END dout1[4]
+ PIN dout1[5]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 171.36 395.76 171.74 396.14 ;
+ END
+ END dout1[5]
+ PIN dout1[6]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 177.48 395.76 177.86 396.14 ;
+ END
+ END dout1[6]
+ PIN dout1[7]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 182.92 395.76 183.3 396.14 ;
+ END
+ END dout1[7]
+ PIN dout1[8]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 189.72 395.76 190.1 396.14 ;
+ END
+ END dout1[8]
+ PIN dout1[9]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 195.16 395.76 195.54 396.14 ;
+ END
+ END dout1[9]
+ PIN dout1[10]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 201.96 395.76 202.34 396.14 ;
+ END
+ END dout1[10]
+ PIN dout1[11]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 208.08 395.76 208.46 396.14 ;
+ END
+ END dout1[11]
+ PIN dout1[12]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 214.88 395.76 215.26 396.14 ;
+ END
+ END dout1[12]
+ PIN dout1[13]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 220.32 395.76 220.7 396.14 ;
+ END
+ END dout1[13]
+ PIN dout1[14]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 226.44 395.76 226.82 396.14 ;
+ END
+ END dout1[14]
+ PIN dout1[15]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 233.24 395.76 233.62 396.14 ;
+ END
+ END dout1[15]
+ PIN dout1[16]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 239.36 395.76 239.74 396.14 ;
+ END
+ END dout1[16]
+ PIN dout1[17]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 246.16 395.76 246.54 396.14 ;
+ END
+ END dout1[17]
+ PIN dout1[18]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 251.6 395.76 251.98 396.14 ;
+ END
+ END dout1[18]
+ PIN dout1[19]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 258.4 395.76 258.78 396.14 ;
+ END
+ END dout1[19]
+ PIN dout1[20]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 263.84 395.76 264.22 396.14 ;
+ END
+ END dout1[20]
+ PIN dout1[21]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 269.96 395.76 270.34 396.14 ;
+ END
+ END dout1[21]
+ PIN dout1[22]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 276.76 395.76 277.14 396.14 ;
+ END
+ END dout1[22]
+ PIN dout1[23]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 282.88 395.76 283.26 396.14 ;
+ END
+ END dout1[23]
+ PIN dout1[24]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 289.68 395.76 290.06 396.14 ;
+ END
+ END dout1[24]
+ PIN dout1[25]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 295.12 395.76 295.5 396.14 ;
+ END
+ END dout1[25]
+ PIN dout1[26]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 301.92 395.76 302.3 396.14 ;
+ END
+ END dout1[26]
+ PIN dout1[27]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 308.04 395.76 308.42 396.14 ;
+ END
+ END dout1[27]
+ PIN dout1[28]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 314.84 395.76 315.22 396.14 ;
+ END
+ END dout1[28]
+ PIN dout1[29]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 320.28 395.76 320.66 396.14 ;
+ END
+ END dout1[29]
+ PIN dout1[30]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 326.4 395.76 326.78 396.14 ;
+ END
+ END dout1[30]
+ PIN dout1[31]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 333.2 395.76 333.58 396.14 ;
+ END
+ END dout1[31]
+ PIN vccd1
+ DIRECTION INOUT ;
+ USE POWER ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met4 ;
+ RECT 473.28 2.04 475.02 394.1 ;
+ LAYER met4 ;
+ RECT 2.04 2.04 3.78 394.1 ;
+ LAYER met3 ;
+ RECT 2.04 2.04 475.02 3.78 ;
+ LAYER met3 ;
+ RECT 2.04 392.36 475.02 394.1 ;
+ END
+ END vccd1
+ PIN vssd1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met4 ;
+ RECT 469.88 5.44 471.62 390.7 ;
+ LAYER met4 ;
+ RECT 5.44 5.44 7.18 390.7 ;
+ LAYER met3 ;
+ RECT 5.44 388.96 471.62 390.7 ;
+ LAYER met3 ;
+ RECT 5.44 5.44 471.62 7.18 ;
+ END
+ END vssd1
+ OBS
+ LAYER met1 ;
+ RECT 0.62 0.62 476.44 395.52 ;
+ LAYER met2 ;
+ RECT 0.62 0.62 476.44 395.52 ;
+ LAYER met3 ;
+ RECT 0.98 127.24 476.44 128.82 ;
+ RECT 0.62 128.82 0.98 135.4 ;
+ RECT 0.62 136.98 0.98 140.84 ;
+ RECT 0.62 142.42 0.98 149.0 ;
+ RECT 0.62 150.58 0.98 154.44 ;
+ RECT 0.62 156.02 0.98 163.28 ;
+ RECT 0.62 164.86 0.98 168.72 ;
+ RECT 0.62 170.3 0.98 395.52 ;
+ RECT 0.98 81.68 476.08 83.26 ;
+ RECT 0.98 83.26 476.08 127.24 ;
+ RECT 476.08 83.26 476.44 127.24 ;
+ RECT 476.08 75.1 476.44 81.68 ;
+ RECT 476.08 0.62 476.44 67.4 ;
+ RECT 476.08 68.98 476.44 73.52 ;
+ RECT 0.62 0.62 0.98 25.24 ;
+ RECT 0.98 128.82 476.08 381.56 ;
+ RECT 0.98 381.56 476.08 383.14 ;
+ RECT 476.08 128.82 476.44 381.56 ;
+ RECT 476.08 383.14 476.44 395.52 ;
+ RECT 0.62 26.82 0.98 34.08 ;
+ RECT 0.62 35.66 0.98 127.24 ;
+ RECT 0.98 0.62 1.44 1.44 ;
+ RECT 0.98 1.44 1.44 4.38 ;
+ RECT 0.98 4.38 1.44 81.68 ;
+ RECT 1.44 0.62 475.62 1.44 ;
+ RECT 475.62 0.62 476.08 1.44 ;
+ RECT 475.62 1.44 476.08 4.38 ;
+ RECT 475.62 4.38 476.08 81.68 ;
+ RECT 0.98 383.14 1.44 391.76 ;
+ RECT 0.98 391.76 1.44 394.7 ;
+ RECT 0.98 394.7 1.44 395.52 ;
+ RECT 1.44 394.7 475.62 395.52 ;
+ RECT 475.62 383.14 476.08 391.76 ;
+ RECT 475.62 391.76 476.08 394.7 ;
+ RECT 475.62 394.7 476.08 395.52 ;
+ RECT 1.44 383.14 4.84 388.36 ;
+ RECT 1.44 388.36 4.84 391.3 ;
+ RECT 1.44 391.3 4.84 391.76 ;
+ RECT 4.84 383.14 472.22 388.36 ;
+ RECT 4.84 391.3 472.22 391.76 ;
+ RECT 472.22 383.14 475.62 388.36 ;
+ RECT 472.22 388.36 475.62 391.3 ;
+ RECT 472.22 391.3 475.62 391.76 ;
+ RECT 1.44 4.38 4.84 4.84 ;
+ RECT 1.44 4.84 4.84 7.78 ;
+ RECT 1.44 7.78 4.84 81.68 ;
+ RECT 4.84 4.38 472.22 4.84 ;
+ RECT 4.84 7.78 472.22 81.68 ;
+ RECT 472.22 4.38 475.62 4.84 ;
+ RECT 472.22 4.84 475.62 7.78 ;
+ RECT 472.22 7.78 475.62 81.68 ;
+ LAYER met4 ;
+ RECT 104.8 0.98 106.38 395.52 ;
+ RECT 106.38 0.62 110.92 0.98 ;
+ RECT 112.5 0.62 116.36 0.98 ;
+ RECT 117.94 0.62 123.16 0.98 ;
+ RECT 124.74 0.62 128.6 0.98 ;
+ RECT 130.18 0.62 134.04 0.98 ;
+ RECT 153.3 0.62 157.16 0.98 ;
+ RECT 258.7 0.62 262.56 0.98 ;
+ RECT 106.38 0.98 395.16 395.16 ;
+ RECT 395.16 0.98 396.74 395.16 ;
+ RECT 415.1 0.62 476.44 0.98 ;
+ RECT 0.62 0.62 27.28 0.98 ;
+ RECT 28.86 0.62 75.56 0.98 ;
+ RECT 396.74 395.16 448.2 395.52 ;
+ RECT 449.78 395.16 476.44 395.52 ;
+ RECT 77.14 0.62 81.68 0.98 ;
+ RECT 83.26 0.62 87.12 0.98 ;
+ RECT 88.7 0.62 93.92 0.98 ;
+ RECT 95.5 0.62 98.68 0.98 ;
+ RECT 100.26 0.62 104.8 0.98 ;
+ RECT 135.62 0.62 137.44 0.98 ;
+ RECT 139.02 0.62 139.48 0.98 ;
+ RECT 141.06 0.62 144.24 0.98 ;
+ RECT 145.82 0.62 146.28 0.98 ;
+ RECT 147.86 0.62 149.68 0.98 ;
+ RECT 151.26 0.62 151.72 0.98 ;
+ RECT 159.42 0.62 163.28 0.98 ;
+ RECT 165.54 0.62 168.72 0.98 ;
+ RECT 171.66 0.62 175.52 0.98 ;
+ RECT 177.78 0.62 180.96 0.98 ;
+ RECT 183.9 0.62 186.4 0.98 ;
+ RECT 188.66 0.62 192.52 0.98 ;
+ RECT 194.1 0.62 194.56 0.98 ;
+ RECT 196.14 0.62 199.32 0.98 ;
+ RECT 200.9 0.62 201.36 0.98 ;
+ RECT 202.94 0.62 204.76 0.98 ;
+ RECT 206.34 0.62 207.48 0.98 ;
+ RECT 209.06 0.62 210.2 0.98 ;
+ RECT 211.78 0.62 213.6 0.98 ;
+ RECT 215.18 0.62 215.64 0.98 ;
+ RECT 217.22 0.62 219.72 0.98 ;
+ RECT 221.3 0.62 222.44 0.98 ;
+ RECT 224.02 0.62 225.84 0.98 ;
+ RECT 227.42 0.62 227.88 0.98 ;
+ RECT 229.46 0.62 231.28 0.98 ;
+ RECT 232.86 0.62 233.32 0.98 ;
+ RECT 234.9 0.62 237.4 0.98 ;
+ RECT 238.98 0.62 239.44 0.98 ;
+ RECT 241.02 0.62 243.52 0.98 ;
+ RECT 246.46 0.62 251.0 0.98 ;
+ RECT 253.26 0.62 255.08 0.98 ;
+ RECT 256.66 0.62 257.12 0.98 ;
+ RECT 265.5 0.62 268.0 0.98 ;
+ RECT 269.58 0.62 270.04 0.98 ;
+ RECT 271.62 0.62 274.12 0.98 ;
+ RECT 275.7 0.62 276.16 0.98 ;
+ RECT 277.74 0.62 280.92 0.98 ;
+ RECT 283.86 0.62 286.36 0.98 ;
+ RECT 288.62 0.62 294.52 0.98 ;
+ RECT 296.1 0.62 300.64 0.98 ;
+ RECT 302.22 0.62 307.44 0.98 ;
+ RECT 309.02 0.62 313.56 0.98 ;
+ RECT 315.14 0.62 319.68 0.98 ;
+ RECT 321.26 0.62 325.8 0.98 ;
+ RECT 327.38 0.62 331.92 0.98 ;
+ RECT 333.5 0.62 411.48 0.98 ;
+ RECT 106.38 395.16 138.8 395.52 ;
+ RECT 140.38 395.16 145.6 395.52 ;
+ RECT 147.18 395.16 151.04 395.52 ;
+ RECT 152.62 395.16 157.84 395.52 ;
+ RECT 159.42 395.16 163.96 395.52 ;
+ RECT 165.54 395.16 170.76 395.52 ;
+ RECT 172.34 395.16 176.88 395.52 ;
+ RECT 178.46 395.16 182.32 395.52 ;
+ RECT 183.9 395.16 189.12 395.52 ;
+ RECT 190.7 395.16 194.56 395.52 ;
+ RECT 196.14 395.16 201.36 395.52 ;
+ RECT 202.94 395.16 207.48 395.52 ;
+ RECT 209.06 395.16 214.28 395.52 ;
+ RECT 215.86 395.16 219.72 395.52 ;
+ RECT 221.3 395.16 225.84 395.52 ;
+ RECT 227.42 395.16 232.64 395.52 ;
+ RECT 234.22 395.16 238.76 395.52 ;
+ RECT 240.34 395.16 245.56 395.52 ;
+ RECT 247.14 395.16 251.0 395.52 ;
+ RECT 252.58 395.16 257.8 395.52 ;
+ RECT 259.38 395.16 263.24 395.52 ;
+ RECT 264.82 395.16 269.36 395.52 ;
+ RECT 270.94 395.16 276.16 395.52 ;
+ RECT 277.74 395.16 282.28 395.52 ;
+ RECT 283.86 395.16 289.08 395.52 ;
+ RECT 290.66 395.16 294.52 395.52 ;
+ RECT 296.1 395.16 301.32 395.52 ;
+ RECT 302.9 395.16 307.44 395.52 ;
+ RECT 309.02 395.16 314.24 395.52 ;
+ RECT 315.82 395.16 319.68 395.52 ;
+ RECT 321.26 395.16 325.8 395.52 ;
+ RECT 327.38 395.16 332.6 395.52 ;
+ RECT 334.18 395.16 395.16 395.52 ;
+ RECT 396.74 0.98 472.68 1.44 ;
+ RECT 396.74 394.7 472.68 395.16 ;
+ RECT 472.68 0.98 475.62 1.44 ;
+ RECT 472.68 394.7 475.62 395.16 ;
+ RECT 475.62 0.98 476.44 1.44 ;
+ RECT 475.62 1.44 476.44 394.7 ;
+ RECT 475.62 394.7 476.44 395.16 ;
+ RECT 0.62 0.98 1.44 1.44 ;
+ RECT 0.62 1.44 1.44 394.7 ;
+ RECT 0.62 394.7 1.44 395.52 ;
+ RECT 1.44 0.98 4.38 1.44 ;
+ RECT 1.44 394.7 4.38 395.52 ;
+ RECT 4.38 0.98 104.8 1.44 ;
+ RECT 4.38 394.7 104.8 395.52 ;
+ RECT 396.74 1.44 469.28 4.84 ;
+ RECT 396.74 4.84 469.28 391.3 ;
+ RECT 396.74 391.3 469.28 394.7 ;
+ RECT 469.28 1.44 472.22 4.84 ;
+ RECT 469.28 391.3 472.22 394.7 ;
+ RECT 472.22 1.44 472.68 4.84 ;
+ RECT 472.22 4.84 472.68 391.3 ;
+ RECT 472.22 391.3 472.68 394.7 ;
+ RECT 4.38 1.44 4.84 4.84 ;
+ RECT 4.38 4.84 4.84 391.3 ;
+ RECT 4.38 391.3 4.84 394.7 ;
+ RECT 4.84 1.44 7.78 4.84 ;
+ RECT 4.84 391.3 7.78 394.7 ;
+ RECT 7.78 1.44 104.8 4.84 ;
+ RECT 7.78 4.84 104.8 391.3 ;
+ RECT 7.78 391.3 104.8 394.7 ;
+ END
+END sky130_sram_1kbyte_1rw1r_32x256_8
+END LIBRARY
diff --git a/openlane/openram_testchip/config.tcl b/openlane/openram_testchip/config.tcl
new file mode 100644
index 0000000..04304b9
--- /dev/null
+++ b/openlane/openram_testchip/config.tcl
@@ -0,0 +1,35 @@
+set script_dir [file dirname [file normalize [info script]]]
+
+set ::env(DESIGN_NAME) openram_testchip
+
+set ::env(DESIGN_IS_CORE) 0
+set ::env(FP_PDN_CORE_RING) 0
+set ::env(GLB_RT_MAXLAYER) 5
+
+set ::env(VERILOG_FILES) "$script_dir/../../verilog/rtl/testchip/openram_testchip.v"
+
+set ::env(CLOCK_PORT) "clock"
+set ::env(CLOCK_PERIOD) "10"
+
+# Fill this
+set ::env(DESIGN_IS_CORE) 0
+set ::env(FP_PDN_CORE_RING) 0
+set ::env(GLB_RT_MAXLAYER) 5
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 1200 1200"
+
+set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 0
+set ::env(PL_RANDOM_GLB_PLACEMENT) 1
+set ::env(PL_BASIC_PLACEMENT) 1
+set ::env(PL_TARGET_DENSITY) 0.99
+
+# Power config
+set ::env(PDN_CFG) $script_dir/pdn.tcl
+
+set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
+if { [file exists $filename] == 1} {
+ source $filename
+}
+
+
diff --git a/openlane/openram_testchip/pdn.tcl b/openlane/openram_testchip/pdn.tcl
new file mode 100644
index 0000000..4ce71c4
--- /dev/null
+++ b/openlane/openram_testchip/pdn.tcl
@@ -0,0 +1,34 @@
+# Power nets
+set ::power_nets $::env(VDD_PIN)
+set ::ground_nets $::env(GND_PIN)
+
+set ::macro_blockage_layer_list "li1 met1 met2 met3 met4 met5"
+
+pdngen::specify_grid stdcell {
+ name grid
+ rails {
+ met1 {width 0.48 pitch $::env(PLACE_SITE_HEIGHT) offset 0}
+ }
+ straps {
+ met4 {width 1.6 pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)}
+ met5 {width 1.6 pitch $::env(FP_PDN_HPITCH) offset $::env(FP_PDN_HOFFSET)}
+ }
+ connect {{met1 met4} {met4 met5}}
+}
+
+pdngen::specify_grid macro {
+ power_pins "VPWR VDD vdd"
+ ground_pins "VGND VSS gnd"
+ blockages "li1 met1 met2 met3 met4"
+ straps {
+ }
+ connect {{met4_PIN_ver met5} {met3_PIN_hor met5}}
+}
+
+set ::halo $::env(FP_HORIZONTAL_HALO)
+
+# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
+set ::rails_start_with "POWER" ;
+
+# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area
+set ::stripes_start_with "POWER" ;
\ No newline at end of file
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 330cf57..0bc78f8 100755
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -27,11 +27,12 @@
## Source Verilog Files
set ::env(VERILOG_FILES) "\
$script_dir/../../caravel/verilog/rtl/defines.v \
- $script_dir/../../verilog/rtl/user_project_wrapper.v"
+ $script_dir/../../verilog/rtl/user_project_wrapper.v \
+ $script_dir/../../verilog/rtl/testchip/openram_testchip.v"
## Clock configurations
-set ::env(CLOCK_PORT) "user_clock2"
-set ::env(CLOCK_NET) "mprj.clk"
+set ::env(CLOCK_PORT) "wb_clk_i"
+set ::env(CLOCK_NET) "wb_clk_i"
set ::env(CLOCK_PERIOD) "10"
@@ -42,28 +43,30 @@
### Black-box verilog and views
set ::env(VERILOG_FILES_BLACKBOX) "\
$script_dir/../../caravel/verilog/rtl/defines.v \
- $script_dir/../../verilog/rtl/user_proj_example.v"
+ $script_dir/../../verilog/rtl/sky130_sram_1kbyte_1rw1r_32x256_8.v"
set ::env(EXTRA_LEFS) "\
- $script_dir/../../lef/user_proj_example.lef"
+ $script_dir/../../lef/user_project_wrapper.lef \
+ $script_dir/../../lef/sky130_sram_1kbyte_1rw1r_32x256_8.lef"
set ::env(EXTRA_GDS_FILES) "\
- $script_dir/../../gds/user_proj_example.gds"
+ $script_dir/../../gds/user_project_wrapper.gds \
+ $script_dir/../../lef/sky130_sram_1kbyte_1rw1r_32x256_8.gds"
set ::env(GLB_RT_MAXLAYER) 5
set ::env(FP_PDN_CHECK_NODES) 0
+# Power config
+#set ::env(PDN_CFG) $script_dir/pdn.tcl
-# The following is because there are no std cells in the example wrapper project.
-set ::env(SYNTH_TOP_LEVEL) 1
+#set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
+
+# Placement config
+set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 0
set ::env(PL_RANDOM_GLB_PLACEMENT) 1
+set ::env(PL_BASIC_PLACEMENT) 1
+set ::env(PL_TARGET_DENSITY) 0.99
-set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
-set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
-set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) 0
-set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0
+set ::env(MAGIC_DRC_USE_GDS) 0
-set ::env(DIODE_INSERTION_STRATEGY) 0
-set ::env(FILL_INSERTION) 0
-set ::env(TAP_DECAP_INSERTION) 0
-set ::env(CLOCK_TREE_SYNTH) 0
+set ::env(RUN_CVC) 0
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index a7365ab..3ff2863 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -1 +1,2 @@
-mprj 1175 1690 N
+SRAM0 75 51.805 N
+SRAM1 75 522.040 N
diff --git a/verilog/rtl/sky130_sram_1kbyte_1rw1r_32x256_8.v b/verilog/rtl/sky130_sram_1kbyte_1rw1r_32x256_8.v
new file mode 100644
index 0000000..fe885ed
--- /dev/null
+++ b/verilog/rtl/sky130_sram_1kbyte_1rw1r_32x256_8.v
@@ -0,0 +1,114 @@
+// OpenRAM SRAM model
+// Words: 256
+// Word size: 32
+// Write size: 8
+
+module sky130_sram_1kbyte_1rw1r_32x256_8(
+`ifdef USE_POWER_PINS
+ vccd1,
+ vssd1,
+`endif
+// Port 0: RW
+ clk0,csb0,web0,wmask0,addr0,din0,dout0,
+// Port 1: R
+ clk1,csb1,addr1,dout1
+ );
+
+ parameter NUM_WMASKS = 4 ;
+ parameter DATA_WIDTH = 32 ;
+ parameter ADDR_WIDTH = 8 ;
+ parameter RAM_DEPTH = 1 << ADDR_WIDTH;
+ // FIXME: This delay is arbitrary.
+ parameter DELAY = 3 ;
+ parameter VERBOSE = 1 ; //Set to 0 to only display warnings
+ parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary
+
+`ifdef USE_POWER_PINS
+ inout vccd1;
+ inout vssd1;
+`endif
+ input clk0; // clock
+ input csb0; // active low chip select
+ input web0; // active low write control
+ input [NUM_WMASKS-1:0] wmask0; // write mask
+ input [ADDR_WIDTH-1:0] addr0;
+ input [DATA_WIDTH-1:0] din0;
+ output [DATA_WIDTH-1:0] dout0;
+ input clk1; // clock
+ input csb1; // active low chip select
+ input [ADDR_WIDTH-1:0] addr1;
+ output [DATA_WIDTH-1:0] dout1;
+
+ reg csb0_reg;
+ reg web0_reg;
+ reg [NUM_WMASKS-1:0] wmask0_reg;
+ reg [ADDR_WIDTH-1:0] addr0_reg;
+ reg [DATA_WIDTH-1:0] din0_reg;
+ reg [DATA_WIDTH-1:0] dout0;
+
+ // All inputs are registers
+ always @(posedge clk0)
+ begin
+ csb0_reg = csb0;
+ web0_reg = web0;
+ wmask0_reg = wmask0;
+ addr0_reg = addr0;
+ din0_reg = din0;
+ #(T_HOLD) dout0 = 32'bx;
+ if ( !csb0_reg && web0_reg && VERBOSE )
+ $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]);
+ if ( !csb0_reg && !web0_reg && VERBOSE )
+ $display($time," Writing %m addr0=%b din0=%b wmask0=%b",addr0_reg,din0_reg,wmask0_reg);
+ end
+
+ reg csb1_reg;
+ reg [ADDR_WIDTH-1:0] addr1_reg;
+ reg [DATA_WIDTH-1:0] dout1;
+
+ // All inputs are registers
+ always @(posedge clk1)
+ begin
+ csb1_reg = csb1;
+ addr1_reg = addr1;
+ if (!csb0 && !web0 && !csb1 && (addr0 == addr1))
+ $display($time," WARNING: Writing and reading addr0=%b and addr1=%b simultaneously!",addr0,addr1);
+ #(T_HOLD) dout1 = 32'bx;
+ if ( !csb1_reg && VERBOSE )
+ $display($time," Reading %m addr1=%b dout1=%b",addr1_reg,mem[addr1_reg]);
+ end
+
+reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
+
+ // Memory Write Block Port 0
+ // Write Operation : When web0 = 0, csb0 = 0
+ always @ (negedge clk0)
+ begin : MEM_WRITE0
+ if ( !csb0_reg && !web0_reg ) begin
+ if (wmask0_reg[0])
+ mem[addr0_reg][7:0] = din0_reg[7:0];
+ if (wmask0_reg[1])
+ mem[addr0_reg][15:8] = din0_reg[15:8];
+ if (wmask0_reg[2])
+ mem[addr0_reg][23:16] = din0_reg[23:16];
+ if (wmask0_reg[3])
+ mem[addr0_reg][31:24] = din0_reg[31:24];
+ end
+ end
+
+ // Memory Read Block Port 0
+ // Read Operation : When web0 = 1, csb0 = 0
+ always @ (negedge clk0)
+ begin : MEM_READ0
+ if (!csb0_reg && web0_reg)
+ dout0 <= #(DELAY) mem[addr0_reg];
+ end
+
+ // Memory Read Block Port 1
+ // Read Operation : When web1 = 1, csb1 = 0
+ always @ (negedge clk1)
+ begin : MEM_READ1
+ if (!csb1_reg)
+ dout1 <= #(DELAY) mem[addr1_reg];
+ end
+
+endmodule
diff --git a/verilog/rtl/testchip/control_logic.v b/verilog/rtl/testchip/control_logic.v
index 1e5f8d7..c7719e3 100644
--- a/verilog/rtl/testchip/control_logic.v
+++ b/verilog/rtl/testchip/control_logic.v
@@ -2,6 +2,7 @@
module SRAM_IN(
input clk_in,
+ input rst,
input chip_select,
input [54:0] packet,
@@ -32,16 +33,40 @@
reg [54:0] in_packet;
reg cs;
-always @(packet) begin
- in_packet <= packet[54:0];
- cs <= chip_select;
+always @(posedge clk_in or rst) begin
+ if(rst) begin
+ in_packet <= 55'b0;
+ cs <= 0;
+ end
+ else begin
+ in_packet <= packet[54:0];
+ cs <= chip_select;
+ end
end
//Forward input bits to proper SRAM and
//0's to other SRAM pins
-always @(in_packet, cs) begin
- case(cs)
- 1'b0 : begin
+always @(posedge clk_in, rst) begin
+ if(rst) begin
+ mgmt_ena0 <= 1'b1;
+ mgmt_wen0 <= 1'b1;
+ mgmt_wen_mask0 <= 4'b0000;
+ mgmt_addr0 <= 8'd0;
+ mgmt_wdata0 = 32'd0;
+ mgmt_ena_ro0 = 1'b1;
+ mgmt_addr_ro0 = 8'd0;
+
+ mgmt_ena1 <= 1'b1;
+ mgmt_wen1 <= 1'b1;
+ mgmt_wen_mask1 <= 4'b0000;
+ mgmt_addr1 <= 8'd0;
+ mgmt_wdata1 = 32'd0;
+ mgmt_ena_ro1 = 1'b1;
+ mgmt_addr_ro1 = 8'd0;
+ end
+ else begin
+ case(cs)
+ 1'b0 : begin
mgmt_ena0 <= in_packet[54];
mgmt_wen0 <= in_packet[53];
mgmt_wen_mask0 <= in_packet[52:49];
@@ -55,7 +80,7 @@
mgmt_wen_mask1 <= 4'b0000;
mgmt_addr1 <= 8'd0;
mgmt_wdata1 = 32'd0;
- mgmt_ena_ro1 = 1'b0;
+ mgmt_ena_ro1 = 1'b1;
mgmt_addr_ro1 = 8'd0;
end
@@ -76,13 +101,14 @@
mgmt_ena_ro0 = 1'b0;
mgmt_addr_ro0 = 8'd0;
end
-
endcase
-
+ end
end
endmodule
module SRAM_DATA(
+ input clk_in,
+ input rst,
input csb0,
input csb1,
input [31:0] dout0,
@@ -91,15 +117,27 @@
);
//Mux out values from SRAM Ports
-always @(dout0, dout1) begin
+//always @(posedge clk_in or rst) begin
+always @(dout0 or dout1) begin
if(csb0 == 0)
sram_data <= dout0;
else if(csb1 == 0)
sram_data <= dout1;
end
+
+always @(posedge clk_in or rst) begin
+ if(rst) begin
+ sram_data <= 32'd0;
+ end
+ else begin
+ sram_data <= sram_data;
+ end
+end
endmodule
module SRAM_OUT(
+ input clk_in,
+ input rst,
input chip_select,
input [31:0] sram0_data,
input [31:0] sram1_data,
@@ -108,11 +146,22 @@
//Mux read values from different SRAMS
//and send to picorv
-always @(sram0_data, sram1_data) begin
+always @(sram0_data or sram1_data) begin
if(chip_select == 0)
sram_contents <= sram0_data;
else if(chip_select == 1)
sram_contents <= sram1_data;
end
+
+always @(posedge clk_in or rst) begin
+ if(rst) begin
+ sram_contents <= 32'd0;
+ end
+ else begin
+ sram_contents <= sram_contents;
+ end
+end
+
+
endmodule
`default_nettype wire
\ No newline at end of file
diff --git a/verilog/rtl/testchip/control_logic_tb.v b/verilog/rtl/testchip/control_logic_tb.v
index 5ddb35c..8272688 100644
--- a/verilog/rtl/testchip/control_logic_tb.v
+++ b/verilog/rtl/testchip/control_logic_tb.v
@@ -12,6 +12,7 @@
module control_logic_tb;
reg clk_in;
+reg rst;
reg chip_select;
reg [54:0] packet;
@@ -48,6 +49,7 @@
//Instantitate port connections
SRAM_IN in_control(.clk_in(clk_in),
+ .rst(rst),
.chip_select(chip_select),
.packet(packet),
.mgmt_ena0(mgmt_ena0),
@@ -84,7 +86,7 @@
sky130_sram_1kbyte_1rw1r_32x256_8 SRAM_1 (
// MGMT R/W port
- .clk0(clk_in),
+ .clk0(clk_in),
.csb0(mgmt_ena1),
.web0(mgmt_wen1),
.wmask0(mgmt_wen_mask1),
@@ -98,24 +100,33 @@
.dout1(mgmt_rdata_ro1)
);
-SRAM_DATA sram0_out(.csb0(packet[54]),
+SRAM_DATA sram0_out(
+ .clk_in(clk_in),
+ .rst(rst),
+ .csb0(packet[54]),
.csb1(packet[8]),
.dout0(mgmt_rdata0),
.dout1(mgmt_rdata_ro0),
.sram_data(sram0_data)
);
-SRAM_DATA sram1_out(.csb0(packet[54]),
+SRAM_DATA sram1_out(
+ .clk_in(clk_in),
+ .rst(rst),
+ .csb0(packet[54]),
.csb1(packet[8]),
.dout0(mgmt_rdata1),
.dout1(mgmt_rdata_ro1),
.sram_data(sram1_data)
);
-SRAM_OUT out_control(.chip_select(chip_select),
- .sram0_data(sram0_data),
- .sram1_data(sram1_data),
- .sram_contents(read_data)
+SRAM_OUT out_control(
+ .clk_in(clk_in),
+ .rst(rst),
+ .chip_select(chip_select),
+ .sram0_data(sram0_data),
+ .sram1_data(sram1_data),
+ .sram_contents(read_data)
);
@@ -123,13 +134,14 @@
$dumpfile("control_logic_tb.vcd");
$dumpvars(0, control_logic_tb);
clk_in = 1;
+ rst = 0;
chip_select = 0;
packet = 55'd0;
//Write 1 to address 1 in SRAM 0
packet = {1'b0, 1'b0, 4'd15, 8'd1, 32'd1, 1'b0, 8'd0};
//Check each output is being sent properly to SRAM
- #10;
+ #15;
`assert(mgmt_ena0, 1'b0);
`assert(mgmt_wen0, 1'b0);
`assert(mgmt_wen_mask0, 4'd15);
@@ -140,11 +152,13 @@
`assert(mgmt_ena_ro0, 1'b0);
`assert(mgmt_addr_ro0, 8'd0);
- #10
+ //Disable write enable after write
+ packet = {1'b0, 1'b1, 4'd15, 8'd1, 32'd1, 1'b0, 8'd0};
+ #20
//Read from address 1 in SRAM 0
packet = {1'b0, 1'b1, 4'd0, 8'd1, 32'd0, 1'b1, 8'd0};
- #10;
+ #20;
`assert(mgmt_ena0, 1'b0);
`assert(mgmt_wen0, 1'b1);
@@ -156,15 +170,16 @@
`assert(mgmt_ena_ro0, 1'b1);
`assert(mgmt_addr_ro0, 8'd0);
- #10
+ #15
`assert(read_data, 32'd1);
+
chip_select = 1;
//Write to address 2 in SRAM 1
packet = {1'b0, 1'b0, 4'd15, 8'd2, 32'd2, 1'b0, 8'd0};
//Check each output is being sent properly to SRAM
- #10;
+ #15;
`assert(mgmt_ena1, 1'b0);
`assert(mgmt_wen1, 1'b0);
`assert(mgmt_wen_mask1, 4'd15);
@@ -174,10 +189,14 @@
//RO Port
`assert(mgmt_ena_ro1, 1'b0);
`assert(mgmt_addr_ro1, 8'd0);
-
+
+ //Disable write enable after write
+ packet = {1'b0, 1'b1, 4'd15, 8'd2, 32'd2, 1'b0, 8'd0};
+ #20
+
//Read from address 2 in SRAM 1
packet = {1'b0, 1'b1, 4'd0, 8'd2, 32'd0, 1'b1, 8'd0};
- #10;
+ #20;
`assert(mgmt_ena1, 1'b0);
`assert(mgmt_wen1, 1'b1);
@@ -189,8 +208,9 @@
`assert(mgmt_ena_ro1, 1'b1);
`assert(mgmt_addr_ro1, 8'd0);
- #10
+ #15
`assert(read_data, 32'd2);
+
#100;$finish;
end
diff --git a/verilog/rtl/testchip/openram_testchip.v b/verilog/rtl/testchip/openram_testchip.v
index 1443944..9857a74 100644
--- a/verilog/rtl/testchip/openram_testchip.v
+++ b/verilog/rtl/testchip/openram_testchip.v
@@ -1,134 +1,94 @@
-`default_nettype none
-`include "control_logic.v"
-`include "sky130_sram_1kbyte_1rw1r_32x256_8.v"
-
-module TEST_CHIP(
- input clk_in,
- input [55:0] analyzer_packet,
- input [55:0] gpio_packet,
- input in_select,
- output reg [31:0] sram_data
-);
-
-reg [54:0] packet;
-reg chip_select;
-
-//SRAM0
-//RW Port
-wire mgmt_ena0;
-wire mgmt_wen0;
-wire [3:0] mgmt_wen_mask0;
-wire [7:0] mgmt_addr0;
-wire [31:0] mgmt_wdata0;
-wire [31:0] mgmt_rdata0;
-//RO Port
-wire mgmt_ena_ro0;
-wire [7:0] mgmt_addr_ro0;
-wire [31:0] mgmt_rdata_ro0;
-
-//SRAM1
-wire mgmt_ena1;
-wire mgmt_wen1;
-wire [3:0] mgmt_wen_mask1;
-wire [7:0] mgmt_addr1;
-wire [31:0] mgmt_wdata1;
-wire [31:0] mgmt_rdata1;
-//RO Port
-wire mgmt_ena_ro1;
-wire [7:0] mgmt_addr_ro1;
-wire [31:0] mgmt_rdata_ro1;
-
-//Data from SRAMs
-wire [31:0] sram0_data;
-wire [31:0] sram1_data;
-wire [31:0] read_data;
-
-//Read in input packet from analyzer or GPIO pins
-always @(analyzer_packet, gpio_packet) begin
- if(in_select == 0) begin
- chip_select <= analyzer_packet[55];
- packet <= analyzer_packet[54:0];
- end
- else if(in_select == 1) begin
- chip_select <= gpio_packet[55];
- packet <= gpio_packet[54:0];
- end
-end
-
-//Instantitate port connections
-SRAM_IN in_control(.clk_in(clk_in),
- .chip_select(chip_select),
- .packet(packet),
- .mgmt_ena0(mgmt_ena0),
- .mgmt_wen0(mgmt_wen0),
- .mgmt_wen_mask0(mgmt_wen_mask0),
- .mgmt_addr0(mgmt_addr0),
- .mgmt_wdata0(mgmt_wdata0),
- .mgmt_ena_ro0(mgmt_ena_ro0),
- .mgmt_addr_ro0(mgmt_addr_ro0),
- .mgmt_ena1(mgmt_ena1),
- .mgmt_wen1(mgmt_wen1),
- .mgmt_wen_mask1(mgmt_wen_mask1),
- .mgmt_addr1(mgmt_addr1),
- .mgmt_wdata1(mgmt_wdata1),
- .mgmt_ena_ro1(mgmt_ena_ro1),
- .mgmt_addr_ro1(mgmt_addr_ro1)
-);
-
-sky130_sram_1kbyte_1rw1r_32x256_8 SRAM_0 (
-// MGMT R/W port
- .clk0(clk_in),
- .csb0(mgmt_ena0),
- .web0(mgmt_wen0),
- .wmask0(mgmt_wen_mask0),
- .addr0(mgmt_addr0),
- .din0(mgmt_wdata0),
- .dout0(mgmt_rdata0),
- // MGMT RO port
- .clk1(clk_in),
- .csb1(mgmt_ena_ro0),
- .addr1(mgmt_addr_ro0),
- .dout1(mgmt_rdata_ro0)
-);
-
-sky130_sram_1kbyte_1rw1r_32x256_8 SRAM_1 (
- // MGMT R/W port
- .clk0(clk_in),
- .csb0(mgmt_ena1),
- .web0(mgmt_wen1),
- .wmask0(mgmt_wen_mask1),
- .addr0(mgmt_addr1),
- .din0(mgmt_wdata1),
- .dout0(mgmt_rdata1),
- // MGMT RO port
- .clk1(clk_in),
- .csb1(mgmt_ena_ro1),
- .addr1(mgmt_addr_ro1),
- .dout1(mgmt_rdata_ro1)
-);
-
-SRAM_DATA sram0_out(.csb0(packet[54]),
- .csb1(packet[8]),
- .dout0(mgmt_rdata0),
- .dout1(mgmt_rdata_ro0),
- .sram_data(sram0_data)
-);
-
-SRAM_DATA sram1_out(.csb0(packet[54]),
- .csb1(packet[8]),
- .dout0(mgmt_rdata1),
- .dout1(mgmt_rdata_ro1),
- .sram_data(sram1_data)
-);
-
-SRAM_OUT out_control(.chip_select(chip_select),
- .sram0_data(sram0_data),
- .sram1_data(sram1_data),
- .sram_contents(read_data)
-);
-
-always @(read_data) begin
- sram_data <= read_data;
-end
-endmodule
-`default_nettype wire
+module openram_testchip(
+
+ `ifdef USE_POWER_PINS
+ inout vdda1, // User area 1 3.3V supply
+ inout vdda2, // User area 2 3.3V supply
+ inout vssa1, // User area 1 analog ground
+ inout vssa2, // User area 2 analog ground
+ inout vccd1, // User area 1 1.8V supply
+ inout vccd2, // User area 2 1.8v supply
+ inout vssd1, // User area 1 digital ground
+ inout vssd2, // User area 2 digital ground
+ `endif
+
+ input clock,
+ input reset,
+ input [55:0] io_logical_analyzer_packet,
+ input [55:0] io_gpio_packet,
+ input io_in_select,
+ input [31:0] io_sram0_rw_in,
+ input [31:0] io_sram0_r0_in,
+ input [31:0] io_sram1_rw_in,
+ input [31:0] io_sram1_ro_in,
+ output [54:0] io_sram0_connections,
+ output [54:0] io_sram1_connections,
+ output [31:0] io_sram_data
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [63:0] _RAND_0;
+`endif // RANDOMIZE_REG_INIT
+ reg [55:0] input_; // @[openram_testchip.scala 22:20]
+ wire chip_select = input_[55]; // @[openram_testchip.scala 29:28]
+ wire csb0 = input_[54]; // @[openram_testchip.scala 30:21]
+ wire web = input_[53]; // @[openram_testchip.scala 31:20]
+ wire _T = ~chip_select; // @[Conditional.scala 37:30]
+ wire [54:0] _GEN_0 = chip_select ? input_[54:0] : 55'h7fffffffffffff; // @[Conditional.scala 39:67 openram_testchip.scala 42:34 openram_testchip.scala 34:26]
+ wire [31:0] _io_sram_data_T = csb0 ? io_sram1_ro_in : io_sram1_rw_in; // @[openram_testchip.scala 49:45]
+ wire [31:0] _io_sram_data_T_1 = csb0 ? io_sram0_r0_in : io_sram0_rw_in; // @[openram_testchip.scala 49:88]
+ wire [31:0] _io_sram_data_T_2 = chip_select ? _io_sram_data_T : _io_sram_data_T_1; // @[openram_testchip.scala 49:28]
+ assign io_sram0_connections = _T ? input_[54:0] : 55'h7fffffffffffff; // @[Conditional.scala 40:58 openram_testchip.scala 38:34 openram_testchip.scala 33:26]
+ assign io_sram1_connections = _T ? 55'h7fffffffffffff : _GEN_0; // @[Conditional.scala 40:58 openram_testchip.scala 34:26]
+ assign io_sram_data = web ? _io_sram_data_T_2 : 32'h0; // @[openram_testchip.scala 48:14 openram_testchip.scala 49:22 openram_testchip.scala 46:18]
+ always @(posedge clock) begin
+ if (io_in_select) begin // @[openram_testchip.scala 27:17]
+ input_ <= io_gpio_packet;
+ end else begin
+ input_ <= io_logical_analyzer_packet;
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {2{`RANDOM}};
+ input_ = _RAND_0[55:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
diff --git a/verilog/rtl/testchip/sky130_sram_1kbyte_1rw1r_32x256_8.v b/verilog/rtl/testchip/sky130_sram_1kbyte_1rw1r_32x256_8.v
index c62b4f3..f08ab44 100644
--- a/verilog/rtl/testchip/sky130_sram_1kbyte_1rw1r_32x256_8.v
+++ b/verilog/rtl/testchip/sky130_sram_1kbyte_1rw1r_32x256_8.v
@@ -3,7 +3,18 @@
// Word size: 32
// Write size: 8
+
module sky130_sram_1kbyte_1rw1r_32x256_8(
+`ifdef USE_POWER_PINS
+ vdda1,
+ vdda2,
+ vssa1,
+ vssa2,
+ vccd1,
+ vccd2,
+ vssd1,
+ vssd2,
+`endif
// Port 0: RW
clk0,csb0,web0,wmask0,addr0,din0,dout0,
// Port 1: R
@@ -19,6 +30,16 @@
parameter VERBOSE = 1 ; //Set to 0 to only display warnings
parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary
+ `ifdef USE_POWER_PINS
+ inout vdda1; // User area 1 3.3V supply
+ inout vdda2; // User area 2 3.3V supply
+ inout vssa1; // User area 1 analog ground
+ inout vssa2; // User area 2 analog ground
+ inout vccd1; // User area 1 1.8V supply
+ inout vccd2; // User area 2 1.8v supply
+ inout vssd1; // User area 1 digital ground
+ inout vssd2; // User area 2 digital ground
+ `endif
input clk0; // clock
input csb0; // active low chip select
input web0; // active low write control
diff --git a/verilog/rtl/testchip/test_chip_tb.v b/verilog/rtl/testchip/test_chip_tb.v
index 966c2b9..5b4b3c9 100644
--- a/verilog/rtl/testchip/test_chip_tb.v
+++ b/verilog/rtl/testchip/test_chip_tb.v
@@ -8,18 +8,20 @@
//`include "control_logic.v"
//`include "sky130_sram_1kbyte_1rw1r_32x256_8.v"
-`include "test_chip.v"
+`include "openram_testchip.v"
module test_chip_tb;
reg clk_in;
+reg rst;
reg [55:0] from_analyzer;
reg [55:0] from_gpio;
reg in_select;
wire [31:0] read_data;
-TEST_CHIP test_logic(.clk_in(clk_in),
+openram_testchip test_logic(.clk_in(clk_in),
+ .rst(rst),
.analyzer_packet(from_analyzer),
.gpio_packet(from_gpio),
.in_select(in_select),
@@ -30,39 +32,51 @@
$dumpfile("test_chip_tb.vcd");
$dumpvars(0, test_chip_tb);
clk_in = 1;
-
+ rst = 0;
//Send packet using logic analyzer
in_select = 0;
from_analyzer = 55'd0;
from_gpio = 55'd0;
//Write 1 to address 1 in SRAM 0
from_analyzer = {1'b0, 1'b0, 1'b0, 4'd15, 8'd1, 32'd1, 1'b0, 8'd0};
-
#10;
+
+ //Disable write enable after write
+ from_analyzer = {1'b0, 1'b0, 1'b1, 4'd15, 8'd1, 32'd1, 1'b0, 8'd0};
+ #20;
+
//Read from address 1 in SRAM 0
from_analyzer = {1'b0, 1'b0, 1'b1, 4'd0, 8'd1, 32'd0, 1'b1, 8'd0};
- #19;
+ #25;
`assert(read_data, 32'd1);
-
+
//Send packet using GPIO pins
in_select = 1;
//Write 1 to address 1 in SRAM 0
from_gpio = {1'b0, 1'b0, 1'b0, 4'd15, 8'd2, 32'd2, 1'b0, 8'd0};
#10;
+ //Disable write enable after write
+ from_gpio = {1'b0, 1'b0, 1'b1, 4'd15, 8'd2, 32'd2, 1'b0, 8'd0};
+ #20;
+
//Read from address 1 in SRAM 0 using RO Port
from_gpio = {1'b0, 1'b1, 1'b1, 4'd0, 8'd0, 32'd0, 1'b0, 8'd2};
- #10;
+ #40;
`assert(read_data, 32'd2);
in_select = 0;
//Write 1 to address 1 in SRAM 1
from_analyzer = {1'b1, 1'b0, 1'b0, 4'd15, 8'd1, 32'd1, 1'b0, 8'd0};
-
- #10;
+ #10
+
+ //Disable write enable after write
+ from_analyzer = {1'b1, 1'b0, 1'b1, 4'd15, 8'd1, 32'd1, 1'b0, 8'd0};
+ #20;
+
//Read from address 1 in SRAM 1
from_analyzer = {1'b1, 1'b0, 1'b1, 4'd0, 8'd1, 32'd0, 1'b1, 8'd0};
- #10;
+ #40;
`assert(read_data, 32'd1);
//Send packet using GPIO pins
@@ -70,15 +84,20 @@
//Write 1 to address 1 in SRAM 1
from_gpio = {1'b1, 1'b0, 1'b0, 4'd15, 8'd2, 32'd2, 1'b0, 8'd0};
#10;
+
+ //Disable write enable after write
+ from_gpio = {1'b1, 1'b0, 1'b1, 4'd15, 8'd2, 32'd2, 1'b0, 8'd0};
+ #20;
//Read from address 1 in SRAM 1 using RO Port
from_gpio = {1'b1, 1'b1, 1'b1, 4'd0, 8'd0, 32'd0, 1'b0, 8'd2};
- #10;
+ #40;
`assert(read_data, 32'd2);
+
#30;$finish;
end
always
#5 clk_in = !clk_in;
-endmodule
\ No newline at end of file
+endmodule
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 2a3462b..1a32bc5 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -78,52 +78,66 @@
output [2:0] user_irq
);
-/*--------------------------------------*/
-/* User project is instantiated here */
-/*--------------------------------------*/
+wire [54:0] sram0_connections;
+wire [54:0] sram1_connections;
-user_proj_example mprj (
- `ifdef USE_POWER_PINS
- .vdda1(vdda1), // User area 1 3.3V power
- .vdda2(vdda2), // User area 2 3.3V power
- .vssa1(vssa1), // User area 1 analog ground
- .vssa2(vssa2), // User area 2 analog ground
- .vccd1(vccd1), // User area 1 1.8V power
- .vccd2(vccd2), // User area 2 1.8V power
- .vssd1(vssd1), // User area 1 digital ground
- .vssd2(vssd2), // User area 2 digital ground
- `endif
+wire [31:0] sram0_rw_out;
+wire [31:0] sram0_ro_out;
+wire [31:0] sram1_rw_out;
+wire [31:0] sram1_ro_out;
- .wb_clk_i(wb_clk_i),
- .wb_rst_i(wb_rst_i),
-
- // MGMT SoC Wishbone Slave
-
- .wbs_cyc_i(wbs_cyc_i),
- .wbs_stb_i(wbs_stb_i),
- .wbs_we_i(wbs_we_i),
- .wbs_sel_i(wbs_sel_i),
- .wbs_adr_i(wbs_adr_i),
- .wbs_dat_i(wbs_dat_i),
- .wbs_ack_o(wbs_ack_o),
- .wbs_dat_o(wbs_dat_o),
-
- // Logic Analyzer
-
- .la_data_in(la_data_in),
- .la_data_out(la_data_out),
- .la_oenb (la_oenb),
-
- // IO Pads
-
- .io_in (io_in),
- .io_out(io_out),
- .io_oeb(io_oeb),
-
- // IRQ
- .irq(user_irq)
+openram_testchip CONTROL_LOGIC(
+ .clock(wb_clk_i),
+ .reset(wb_rst_i),
+ .io_logical_analyzer_packet(la_data_in[55:0]),
+ .io_gpio_packet(la_data_in[55:0]),
+ .io_in_select(la_data_in[56]),
+ .io_sram0_rw_in(sram0_rw_out),
+ .io_sram0_r0_in(sram0_ro_out),
+ .io_sram1_rw_in(sram1_rw_out),
+ .io_sram1_ro_in(sram1_ro_out),
+ .io_sram0_connections(sram0_connections),
+ .io_sram1_connections(sram1_connections),
+ .io_sram_data(la_data_out[31:0])
);
+sky130_sram_1kbyte_1rw1r_32x256_8 SRAM0
+ (
+
+ `ifdef USE_POWER_PINS
+ .vccd1(vccd1),
+ .vssd1(vssd1),
+ `endif
+ .clk0 (wb_clk_i),
+ .csb0 (sram0_connections[54]),
+ .web0 (sram0_connections[53]),
+ .wmask0 (sram0_connections[52:49]),
+ .addr0 (sram0_connections[48:41]),
+ .din0 (sram0_connections[40:9]),
+ .dout0 (sram0_rw_out),
+ .clk1 (wb_clk_i),
+ .csb1 (sram0_connections[8]),
+ .addr1 (sram0_connections[7:0]),
+ .dout1 (sram0_ro_out));
+
+sky130_sram_1kbyte_1rw1r_32x256_8 SRAM1
+ (
+ `ifdef USE_POWER_PINS
+ .vccd1(vccd1),
+ .vssd1(vssd1),
+ `endif
+ .clk0 (wb_clk_i),
+ .csb0 (sram1_connections[54]),
+ .web0 (sram1_connections[53]),
+ .wmask0 (sram1_connections[52:49]),
+ .addr0 (sram1_connections[48:41]),
+ .din0 (sram1_connections[40:9]),
+ .dout0 (sram1_rw_out),
+ .clk1 (wb_clk_i),
+ .csb1 (sram1_connections[8]),
+ .addr1 (sram1_connections[7:0]),
+ .dout1 (sram1_ro_out));
+
endmodule // user_project_wrapper
`default_nettype wire
