commit c52702bcf560bd63a9bdcd1298915491ce4cb924
author AmoghLonkar <alonkar@ucsc.edu> Sat Jun 12 16:58:53 2021 -0700
committer AmoghLonkar <alonkar@ucsc.edu> Sat Jun 12 16:58:53 2021 -0700
tree d658d394c0ab4b54d58d355d3509d932d0ba2ca9
parent ff1d0fc3264d3f0ee530b30c30dcb03f3fa2c4ea

Fixed read_data bit width

verilog/rtl/openram_testchip.v

diff --git a/verilog/rtl/openram_testchip.v b/verilog/rtl/openram_testchip.v
index 279ec49..2f1b930 100644
--- a/verilog/rtl/openram_testchip.v
+++ b/verilog/rtl/openram_testchip.v
@@ -61,8 +61,8 @@
 

 // Mux output to connect final output data

 // into sram_register

-reg [32:0] read_data0;

-reg [32:0] read_data1;

+reg [31:0] read_data0;

+reg [31:0] read_data1;

 

 // SRAM input connections

 reg [3:0] chip_select;

@@ -98,6 +98,7 @@
     end

     else if(gpio_sram_load || la_sram_load) begin

         sram_register <= {sram_register[111:92], read_data0, sram_register[59:38], read_data1, sram_register[5:0]};

+        //sram_register <= sram_register;

     end

     //GPIO scanning for output transfer

     else if(gpio_out_scan) begin