commit c16cb81976428dd4dae9580ce857985564ae3899
author AmoghLonkar <alonkar@ucsc.edu> Thu Jun 10 17:50:45 2021 -0700
committer AmoghLonkar <alonkar@ucsc.edu> Thu Jun 10 17:50:45 2021 -0700
tree ba79d0e32f461f3d817a34232c8beb57f5642f74
parent 92534d05cdc50634238f81a326a6ed60a39e410d

LA Testbench

verilog/rtl/openram_testchip_tb.v

diff --git a/verilog/rtl/openram_testchip_tb.v b/verilog/rtl/openram_testchip_tb.v
index af2c9fa..ca4c7f2 100644
--- a/verilog/rtl/openram_testchip_tb.v
+++ b/verilog/rtl/openram_testchip_tb.v
@@ -142,7 +142,7 @@
     in_select = 0;

     from_analyzer = 86'd0;

     from_gpio =  1'd0;

-

+    

     //Write 1 to address 1 in SRAM 0

     from_analyzer = {3'd0, 28'd0, 1'b0, 1'b0, 4'd15, 8'd1, 32'd1, 1'b0, 8'd0};

     #20;

@@ -209,11 +209,9 @@
     from_analyzer = {3'd5, 1'b0, 1'b1, 8'd0, 9'd5, 64'd0};

     #60;

     `assert(to_la, 64'd5);

-

     #10;$finish;

 end

 

 always 

     #5 clk_in = !clk_in;

-

 endmodule