Two input clocks for control module
diff --git a/verilog/rtl/openram_testchip.v b/verilog/rtl/openram_testchip.v
index e98b7bc..a3755cb 100644
--- a/verilog/rtl/openram_testchip.v
+++ b/verilog/rtl/openram_testchip.v
@@ -9,7 +9,8 @@
inout vssd1, // User area 1 digital ground
inout vssd2, // User area 2 digital ground
`endif
- input clk,
+ input la_clk,
+ input gpio_clk,
input reset,
input [85:0] la_packet,
input gpio_packet,
@@ -44,6 +45,12 @@
reg[6:0] gpio_counter = 7'd0;
reg transfer = 1'b0;
+reg clk;
+
+always @(*) begin
+ clk <= in_select ? gpio_clk : la_clk;
+end
+
always @(gpio_packet, read_data) begin
if(!transfer && in_select) begin
transfer <= 1;
diff --git a/verilog/rtl/openram_testchip_tb.v b/verilog/rtl/openram_testchip_tb.v
index 6a6e07c..5ff4a6d 100644
--- a/verilog/rtl/openram_testchip_tb.v
+++ b/verilog/rtl/openram_testchip_tb.v
@@ -41,7 +41,8 @@
wire to_gpio;
openram_testchip CONTROL_LOGIC(
- .clk(clk_in),
+ .la_clk(clk_in),
+ .gpio_clk(clk_in),
.reset(rst),
.la_packet(from_analyzer),
.gpio_packet(from_gpio),
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 8eca946..53ece04 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -95,18 +95,13 @@
wire [31:0] sram4_rw_out;
wire [63:0] sram5_rw_out;
-reg clk;
-
-always @(*) begin
- clk <= io_in[1] ? user_clock2 : wb_clk_i;
-end
-
openram_testchip CONTROL_LOGIC(
- .clk(clk),
+ .la_clk(wb_clk_i),
+ .gpio_clk(io_in[1]),
.reset(wb_rst_i),
.la_packet(la_data_in[85:0]),
.gpio_packet(io_in[2]),
- .in_select(la_data_in[86]),
+ .in_select(io_in[3]),
.sram0_rw_in(sram0_rw_out),
.sram0_ro_in(sram0_ro_out),
.sram1_rw_in(sram1_rw_out),
