commit | be1762c047b70bcf3b0963376355cc9335c7b58e | [log] [tgz] |
---|---|---|
author | mrg <mrg@ucsc.edu> | Fri Jun 18 18:49:18 2021 -0700 |
committer | mrg <mrg@ucsc.edu> | Fri Jun 18 18:49:18 2021 -0700 |
tree | e18521d10b5a7018dcda78e97a57668cf804c5fc | |
parent | 80511b3bd091af7f96e6778f2a7d13c2b0d57a8c [diff] | |
parent | 2cb8c08befc549e452258011a43859fcc556f21d [diff] |
Merge branch 'main' of github.com:AmoghLonkar/openram_testchip into main
:exclamation: Important Note |
---|
This project contains a test chip for several OpenRAM memory configurations. The configurations have varying levels of verification. In particular, it has these sizes:
There are two test modes available. Each one inputs an packet that configures the read and write operations of a particular SRAM. The GPIO pin io_in[16] determines whether to use GPIO (1) or LA mode (0).
The test packet is a 112-bit value that has the follow signals and bit size:
During a read operation, the din bits are replaced with the data output bits so that they can be verified.
Note: The 64-bit memory leaves the middle 32-bits as a value of 0 and instead reads/writes the upper and lower 16-bits to reduce the number of packet bits.
In GPIO mode, the test packet is scanned in/out with the GPIO pins in 112 cycles. The GPIO pins used are as follows:
In LA mode, the test packet is directly written from the output of the 128-bit LA. The top bits of the LA register are used for the control signals during test: