Sign in
foss-eda-tools
/
third_party
/
shuttle
/
sky130
/
mpw-002
/
slot-009
/
7c55d39a32718510a519b4d3ca7b28d9a18519ee
commit
7c55d39a32718510a519b4d3ca7b28d9a18519ee
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[
tgz
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author
Jesse Cirimelli-Low <jcirimel@ucsc.edu>
Wed Jun 02 18:04:15 2021 -0700
committer
Jesse Cirimelli-Low <jcirimel@ucsc.edu>
Wed Jun 02 18:04:15 2021 -0700
tree
2bef265d9ca42c504acd5ff16c4564bed4fb1d05
parent
20d0669af23d26cb07119b0ff5df6dd963fd83d5
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remove extra folders
openlane/openram_testchip/config.tcl
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openlane/openram_testchip/pdn.tcl
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openlane/user_proj_example/config.tcl
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openlane/user_proj_example/pin_order.cfg
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4 files changed
tree: 2bef265d9ca42c504acd5ff16c4564bed4fb1d05
.github/
def/
docs/
gds/
lef/
mag/
maglef/
openlane/
signoff/
single_port/
spi/
verilog/
caravel
.gitignore
.gitmodules
info.yaml
LICENSE
Makefile
README.md
README.md
Caravel User Project
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Please fill in your project documentation in this README.md file
Refer to
README
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