commit: da4b9cfb72fa2e044c64a6777ed8b9af138cc987
[log]
author: AmoghLonkar <alonkar@ucsc.edu>
Mon May 17 18:38:50 2021 -0700
committer: AmoghLonkar <alonkar@ucsc.edu>
Mon May 17 18:38:50 2021 -0700
tree: a3baba4233d4bcb9214a9a33b2c21f4244844cfb
parent: ad022ab9abe47e919730bf0378d498632b06cfc8 [diff]

Added rst conditions and needed to set web to low after writing. Mask/wdata when disabling is a small issue

verilog/rtl/testchip/control_logic_tb.v[diff]

1 file changed

tree: a3baba4233d4bcb9214a9a33b2c21f4244844cfb

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for this sample project documentation.