commit aef5f1acdc5a6e531e0b784b5350d33ad66b403e
author AmoghLonkar <alonkar@ucsc.edu> Tue Jun 15 14:01:48 2021 -0700
committer AmoghLonkar <alonkar@ucsc.edu> Tue Jun 15 14:01:48 2021 -0700
tree c0d82ce3803802f2937878bce29c0464298699c7
parent 741732cb13fbb5f5f57d0f56d8a217175d5eae72

Switched to for loops, check why assertion fails

verilog/rtl/openram_testchip_tb.v

diff --git a/verilog/rtl/openram_testchip_tb.v b/verilog/rtl/openram_testchip_tb.v
index 1bd2955..9561fc0 100644
--- a/verilog/rtl/openram_testchip_tb.v
+++ b/verilog/rtl/openram_testchip_tb.v
@@ -391,8 +391,8 @@
       sram_clk = 1;

       #5;

       sram_clk = 0;

-      #10;

-      

+      #20;

+

       `assert(la_data_out, {4'd0, 16'd1, 32'd1, 1'b0, 1'b1, 4'd0, 16'd2, 32'd2, 1'b0, 1'b1, 4'd0});

     end

     #10;$finish;