Change csr to csb
diff --git a/verilog/rtl/openram_testchip.v b/verilog/rtl/openram_testchip.v
index e46077e..c3622d0 100644
--- a/verilog/rtl/openram_testchip.v
+++ b/verilog/rtl/openram_testchip.v
@@ -20,7 +20,7 @@
input gpio_in,
input gpio_scan,
input gpio_sram_load,
- input global_csr,
+ input global_csb,
// SRAM data outputs to be captured
input [`DATA_SIZE-1:0] sram0_data0,
input [`DATA_SIZE-1:0] sram0_data1,
@@ -116,13 +116,13 @@
addr0 = sram_register[`TOTAL_SIZE-`SELECT_SIZE-1:`TOTAL_SIZE-`SELECT_SIZE-`ADDR_SIZE];
din0 = sram_register[`DATA_SIZE+`PORT_SIZE+`WMASK_SIZE+1:`PORT_SIZE+`WMASK_SIZE+2];
- csb0_temp = global_csr | sram_register[`PORT_SIZE+`WMASK_SIZE+1];
+ csb0_temp = global_csb | sram_register[`PORT_SIZE+`WMASK_SIZE+1];
web0 = sram_register[`PORT_SIZE+`WMASK_SIZE];
wmask0 = sram_register[`PORT_SIZE+`WMASK_SIZE-1:`PORT_SIZE];
addr1 = sram_register[`PORT_SIZE-1:`DATA_SIZE+`WMASK_SIZE+2];
din1 = sram_register[`DATA_SIZE+`WMASK_SIZE+1:`WMASK_SIZE+2];
- csb1_temp = global_csr | sram_register[`WMASK_SIZE+1];
+ csb1_temp = global_csb | sram_register[`WMASK_SIZE+1];
web1 = sram_register[`WMASK_SIZE];
wmask1 = sram_register[`WMASK_SIZE-1:0];
end
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 87b870d..9e5dd1f 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -98,7 +98,7 @@
wire gpio_sram_clk = io_in[18];
wire gpio_scan = io_in[19];
wire gpio_sram_load = io_in[20];
- wire global_csr = io_in[21];
+ wire global_csb = io_in[21];
wire la_clk = la_data_in[127];
wire la_in_load = la_data_in[125];
wire la_sram_load = la_data_in[124];
@@ -119,7 +119,7 @@
openram_testchip CONTROL_LOGIC(
.resetn(resetn & wb_rst_i),
.clk(clk),
- .global_csr(global_csr),
+ .global_csb(global_csb),
.gpio_scan(gpio_scan),
.gpio_sram_load(gpio_sram_load),
.la_in_load(la_in_load),
