commit abe028975cfcbced09f32f98ccee2331bc7f14c9
author mrg <mrg@ucsc.edu> Fri Jun 25 12:31:02 2021 -0700
committer mrg <mrg@ucsc.edu> Fri Jun 25 12:31:02 2021 -0700
tree 2f44bc4821ec29026a3be445c0c6db81aa2679c5
parent 18d2c0ed1e5a795c14443bbc6ba04a467eba2c1e

Restrict data to < 8bits for SRAM0

verilog/dv/gpio_test/gpio_test_tb.v

diff --git a/verilog/dv/gpio_test/gpio_test_tb.v b/verilog/dv/gpio_test/gpio_test_tb.v
index b231668..f3fa89c 100644
--- a/verilog/dv/gpio_test/gpio_test_tb.v
+++ b/verilog/dv/gpio_test/gpio_test_tb.v
@@ -185,12 +185,12 @@
 			      16'd0,
 			      32'd0);
 
-		   // write 2 to address 2
+		   // write i^3 to address 2
 		   write_sram(i,
 			      1'b0,
 			      1'b0,
 			      16'd2,
-			      ~i,
+			      i<<3,
 			      1'b1,
 			      1'b1,
 			      16'd0,
@@ -205,7 +205,7 @@
 			     1'b0,
 			     1'b1,
 			     16'd2,
-			     ~i);
+			     i<<3);