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1f8c571ba8e360f203a75341800d737bdd28dc8e
commit
1f8c571ba8e360f203a75341800d737bdd28dc8e
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log
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author
AmoghLonkar <alonkar@ucsc.edu>
Thu Jun 03 08:47:11 2021 -0700
committer
AmoghLonkar <alonkar@ucsc.edu>
Thu Jun 03 08:47:11 2021 -0700
tree
cba343ff158ef36adb3ef978b2cf13f1dd0d5c62
parent
8487a5801f08c2f0e518b6cd5d22dc0071edc631
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Adding chisel files
chisel/control_logic-main.zip:Zone.Identifier
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chisel/control_logic-main/control_logic-main/.github/workflows/test.yml
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chisel/control_logic-main/control_logic-main/.gitignore
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chisel/control_logic-main/control_logic-main/README.md
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chisel/control_logic-main/control_logic-main/build.sbt
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chisel/control_logic-main/control_logic-main/openram_testchip.v
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chisel/control_logic-main/control_logic-main/project/build.properties
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chisel/control_logic-main/control_logic-main/project/plugins.sbt
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chisel/control_logic-main/control_logic-main/src/main/scala/control_logic/openram_testchip.scala
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chisel/control_logic-main/control_logic-main/src/test/scala/control_logic/openramTestSuite.scala
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10 files changed
tree: cba343ff158ef36adb3ef978b2cf13f1dd0d5c62
.github/
chisel/
def/
docs/
gds/
lef/
mag/
maglef/
openlane/
signoff/
single_port/
spi/
verilog/
caravel
.gitignore
.gitmodules
info.yaml
LICENSE
Makefile
README.md
README.md
Caravel User Project
:exclamation: Important Note
Please fill in your project documentation in this README.md file
Refer to
README
for this sample project documentation.