| commit | a5189a72e22eee0a0aa9fb9b97c311dbc3452a1b | [log] [tgz] |
|---|---|---|
| author | mrg <mrg@ucsc.edu> | Mon Jul 12 09:37:14 2021 -0700 |
| committer | mrg <mrg@ucsc.edu> | Mon Jul 12 09:37:14 2021 -0700 |
| tree | cb91f1e5a4917e8b144cd9bded8762eefa4443ed | |
| parent | 2a9207761be7db22d687ad2e2f98333cd14c49af [diff] |
Add authors to README
diff --git a/README.md b/README.md index d4bf5aa..4ac5e34 100644 --- a/README.md +++ b/README.md
@@ -70,3 +70,9 @@ * Load control register: la_in_load la_data_in[125] * Load SRAM result into register: la_sram_load la_data_in[124] * CSB for all SRAM: ?? + +# Authors + +Jesse Cirimeli-Low <jcirimel@ucsc.edu> +Amogh Lonkar <alonkar@ucsc.edu> +Matthew Guthaus <mrg@ucsc.edu>