commit: f9a9f3a3e0232ab12cc0b118665d434435d11535
[log]
author: AmoghLonkar <alonkar@ucsc.edu>
Sat May 08 22:15:15 2021 -0700
committer: AmoghLonkar <alonkar@ucsc.edu>
Sat May 08 22:15:15 2021 -0700
tree: 95bf4d20fb33dc6c70c496e0fb0e74b2e24be89f
parent: b4abbeb9ec2ce2bf49ee5220da82f6c8ad22e5b1 [diff]

Instantiated two SRAM chips, need to connect wires to input via demux

verilog/rtl/testchip/control_logic.v[diff]

1 file changed

tree: 95bf4d20fb33dc6c70c496e0fb0e74b2e24be89f

README.md

Caravel User Project

NOTE

Fill this README with your caravel user project documentation.

Refer to README for this sample project documentation.