commit: 646a13626811d36d2aa22d5e7d1d7281665cd8b0
[log]
author: Amogh Lonkar <35778429+AmoghLonkar@users.noreply.github.com>
Sun May 16 21:40:53 2021 -0700
committer: GitHub <noreply@github.com>
Sun May 16 21:40:53 2021 -0700
tree: 0bc7ba49ee2a9716e707ade1928ce8fea9c4fc75
parent: 9f7f84b188ee739e23b8666f40e6f1772b89db51 [diff]

Rename test_chip.v to openram_testchip.v

Removes Yosys parsing errors

verilog/rtl/testchip/openram_testchip.v[Renamed from verilog/rtl/testchip/test_chip.v - diff]

1 file changed

tree: 0bc7ba49ee2a9716e707ade1928ce8fea9c4fc75

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for this sample project documentation.