Add pins to sides of block.
diff --git a/openlane/openram_testchip/pin_order.cfg b/openlane/openram_testchip/pin_order.cfg
new file mode 100644
index 0000000..bbd4cba
--- /dev/null
+++ b/openlane/openram_testchip/pin_order.cfg
@@ -0,0 +1,46 @@
+#BUS_SORT
+#NR
+in_select
+gpio.*
+
+#S
+reset.*
+la_.*
+
+#E
+sram0_clk
+sram0.*
+sram1_clk
+sram1.*
+sram2_clk
+sram2.*
+sram3_clk
+sram3.*
+right.*
+sram4_clk
+sram4.*
+sram5_clk
+sram5.*
+sram6_clk
+sram6.*
+sram7_clk
+sram7.*
+
+#WR
+sram8_clk
+sram8.*
+sram9_clk
+sram9.*
+sram10_clk
+sram10.*
+sram11_clk
+sram11.*
+left.*
+sram12_clk
+sram12.*
+sram13_clk
+sram13.*
+sram14_clk
+sram14.*
+sram15_clk
+sram15.*
\ No newline at end of file
diff --git a/verilog/rtl/openram_defines.v b/verilog/rtl/openram_defines.v
new file mode 100644
index 0000000..ff695e8
--- /dev/null
+++ b/verilog/rtl/openram_defines.v
@@ -0,0 +1,7 @@
+`define WMASK_SIZE 4
+`define ADDR_SIZE 16
+`define DATA_SIZE 32
+`define SELECT_SIZE 4
+`define MAX_CHIPS 16
+`define PORT_SIZE `DATA_SIZE+`DATA_SIZE+`WMASK_SIZE+2
+`define TOTAL_SIZE 2*`PORT_SIZE + `SELECT_SIZE
diff --git a/verilog/rtl/openram_testchip.v b/verilog/rtl/openram_testchip.v
index d363874..f8aa54e 100644
--- a/verilog/rtl/openram_testchip.v
+++ b/verilog/rtl/openram_testchip.v
@@ -1,10 +1,4 @@
-`define WMASK_SIZE 4
-`define ADDR_SIZE 16
-`define DATA_SIZE 32
-`define SELECT_SIZE 4
-`define MAX_CHIPS 16
-`define PORT_SIZE `DATA_SIZE+`DATA_SIZE+`WMASK_SIZE+2
-`define TOTAL_SIZE 2*`PORT_SIZE + `SELECT_SIZE
+`include "openram_defines.v"
module openram_testchip(
`ifdef USE_POWER_PINS
@@ -68,17 +62,26 @@
input [`DATA_SIZE-1:0] sram15_dout1,
// Shared control/data to the SRAMs
- output reg [`ADDR_SIZE-1:0] addr0,
- output reg [`DATA_SIZE-1:0] din0,
- output reg web0,
- output reg [`WMASK_SIZE-1:0] wmask0,
- output reg [`ADDR_SIZE-1:0] addr1,
- output reg [`DATA_SIZE-1:0] din1,
- output reg web1,
- output reg [`WMASK_SIZE-1:0] wmask1,
+ output reg [`ADDR_SIZE-1:0] left_addr0,
+ output reg [`DATA_SIZE-1:0] left_din0,
+ output reg left_web0,
+ output reg [`WMASK_SIZE-1:0] left_wmask0,
+ output reg [`ADDR_SIZE-1:0] left_addr1,
+ output reg [`DATA_SIZE-1:0] left_din1,
+ output reg left_web1,
+ output reg [`WMASK_SIZE-1:0] left_wmask1,
// One CSB for each SRAM
- output reg [`ADDR_SIZE-1:0] csb0,
- output reg [`ADDR_SIZE-1:0] csb1,
+ // One CSB for each SRAM
+ output reg [`MAX_CHIPS-1:0] left_csb0,
+ output reg [`MAX_CHIPS-1:0] left_csb1,
+
+ // Shared control/data to the SRAMs
+ output [`ADDR_SIZE-1:0] right_addr0,
+ output [`DATA_SIZE-1:0] right_din0,
+ output right_web0,
+ output [`WMASK_SIZE-1:0] right_wmask0,
+ // One CSB for each SRAM
+ output [`MAX_CHIPS-1:0] right_csb0,
// Clocks for each SRAM
output reg sram0_clk,
@@ -144,14 +147,23 @@
reg [`DATA_SIZE-1:0] sram15_data0;
reg [`DATA_SIZE-1:0] sram15_data1;
-// Mux output to connect final output data
-// into sram_register
+ // Mux output to connect final output data
+ // into sram_register
reg [`DATA_SIZE-1:0] read_data0;
reg [`DATA_SIZE-1:0] read_data1;
-// SRAM input connections
+ // SRAM input connections
reg [`SELECT_SIZE-1:0] chip_select;
+ // Duplicate pins on other side
+ wire [`ADDR_SIZE-1:0] right_addr0 = left_addr0;
+ wire [`DATA_SIZE-1:0] right_din0 = left_din0;
+ wire right_web0 = left_web0;
+ wire [`WMASK_SIZE-1:0] right_wmask0 = left_wmask0;
+ wire [`MAX_CHIPS-1:0] right_csb0 = left_csb0;
+
+
+
//Selecting clock pin
always @(*) begin
clk = in_select ? gpio_clk : la_clk;
@@ -202,17 +214,17 @@
// TODO: Use defines for these
chip_select = sram_register[`TOTAL_SIZE-1:108];
- addr0 = sram_register[107:92];
- din0 = sram_register[91:60];
+ left_addr0 = sram_register[107:92];
+ left_din0 = sram_register[91:60];
csb0_temp = sram_register[59];
- web0 = sram_register[58];
- wmask0 = sram_register[57:54];
+ left_web0 = sram_register[58];
+ left_wmask0 = sram_register[57:54];
- addr1 = sram_register[`PORT_SIZE-1:`DATA_SIZE+`WMASK_SIZE+2];
- din1 = sram_register[`DATA_SIZE+`WMASK_SIZE+1:`WMASK_SIZE+2];
- csb1_temp = sram_register[`WMASK_SIZE+1];
- web1 = sram_register[`WMASK_SIZE];
- wmask1 = sram_register[`WMASK_SIZE-1:0];
+ left_addr1 = sram_register[`PORT_SIZE-1:`DATA_SIZE+`WMASK_SIZE+2];
+ left_din1 = sram_register[`DATA_SIZE+`WMASK_SIZE+1:`WMASK_SIZE+2];
+ left_csb1_temp = sram_register[`WMASK_SIZE+1];
+ left_web1 = sram_register[`WMASK_SIZE];
+ left_wmask1 = sram_register[`WMASK_SIZE-1:0];
end
// Apply the correct CSB
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 986b543..86c92de 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -14,6 +14,7 @@
// SPDX-License-Identifier: Apache-2.0
`default_nettype none
+`include "openram_defines.v"
/*
*-------------------------------------------------------------
*
@@ -78,40 +79,69 @@
output [2:0] user_irq
);
-wire [55:0] sram0_connections;
-wire [55:0] sram1_connections;
-wire [48:0] io_sram2_connections;
-wire [46:0] io_sram3_connections;
-wire [47:0] io_sram4_connections;
-wire [83:0] io_sram5_connections;
+ // Shared control/data to the SRAMs
+ wire [`ADDR_SIZE-1:0] addr0;
+ wire [`DATA_SIZE-1:0] din0;
+ wire web0;
+ wire [`WMASK_SIZE-1:0] wmask0;
+ wire [`ADDR_SIZE-1:0] addr1;
+ wire [`DATA_SIZE-1:0] din1;
+ wire web1;
+ wire [`WMASK_SIZE-1:0] wmask1;
+ // One CSB for each SRAM
+ wire [`MAX_CHIPS-1:0] csb0;
+ wire [`MAX_CHIPS-1:0] csb1;
+
-wire [31:0] sram0_rw_out;
-wire [31:0] sram0_ro_out;
-wire [31:0] sram1_rw_out;
-wire [31:0] sram1_ro_out;
-wire [31:0] sram2_rw_out;
-wire [31:0] sram3_rw_out;
-wire [31:0] sram4_rw_out;
-wire [63:0] sram5_rw_out;
-
+wire [31:0] sram0_dout0;
+wire [31:0] sram0_dout1;
+wire [31:0] sram1_dout0;
+wire [31:0] sram1_dout1;
+wire [31:0] sram2_dout0;
+wire [31:0] sram2_dout1;
+wire [31:0] sram3_dout0;
+wire [31:0] sram3_dout1;
+wire [31:0] sram4_dout0;
+wire [31:0] sram4_dout1;
+wire [31:0] sram5_dout0;
+wire [31:0] sram5_dout1;
+wire [31:0] sram6_dout0;
+wire [31:0] sram6_dout1;
+wire [31:0] sram7_dout0;
+wire [31:0] sram7_dout1;
+wire [31:0] sram8_dout0;
+wire [31:0] sram8_dout1;
+wire [31:0] sram9_dout0;
+wire [31:0] sram9_dout1;
+wire [31:0] sram10_dout0;
+wire [31:0] sram10_dout1;
+wire [31:0] sram11_dout0;
+wire [31:0] sram11_dout1;
+wire [31:0] sram12_dout0;
+wire [31:0] sram12_dout1;
+wire [31:0] sram13_dout0;
+wire [31:0] sram13_dout1;
+wire [31:0] sram14_dout0;
+wire [31:0] sram14_dout1;
openram_testchip CONTROL_LOGIC(
- .reset(wb_rst_i),
- .in_select(io_in[0]),
- .gpio_clk(io_in[1]),
- .gpio_sram_clk(io_in[2]),
- .gpio_scan(io_in[3]),
- .gpio_sram_load(io_in[4]),
+ .reset(io_in[15]|~wb_rst_i),
+ .in_select(io_in[16]),
+ .gpio_clk(io_in[17]),
+ .gpio_sram_clk(io_in[18]),
+ .gpio_scan(io_in[19]),
+ .gpio_sram_load(io_in[20]),
+
.la_clk(la_data_in[127]),
.la_sram_clk(la_data_in[126]),
.la_in_load(la_data_in[125]),
.la_sram_load(la_data_in[124]),
.la_data_in(la_data_in[111:0]),
.la_data_out(la_data_out[111:0]),
- .gpio_out(io_out[0]),
+ .gpio_out(io_out[21]),
// Shared control/data to the SRAMs
.addr0(addr0),
@@ -224,7 +254,9 @@
wire [31:0] sram14_dout1;
wire [31:0] sram15_dout0;
wire [31:0] sram15_dout1;
-
+
+ // Only io_out[27] is output
+ assgin io_oeb = 1'b1 << 21;
// Not working yet
// sky130_sram_1kbyte_1r1w_8x1024_8 SRAM0
