commit 988bba95b3c20fd37149c341848c8f858daffe9f
author AmoghLonkar <alonkar@ucsc.edu> Mon May 17 10:36:14 2021 -0700
committer AmoghLonkar <alonkar@ucsc.edu> Mon May 17 10:36:14 2021 -0700
tree df091a35a3b7f3e995b4692ec31c7dd732748730
parent 1ad4c6971a6f377b58f412229031b72ba37f280b

Commented out include statements for yosys parsing

verilog/rtl/testchip/openram_testchip.v

diff --git a/verilog/rtl/testchip/openram_testchip.v b/verilog/rtl/testchip/openram_testchip.v
index 8afe30f..597d02d 100644
--- a/verilog/rtl/testchip/openram_testchip.v
+++ b/verilog/rtl/testchip/openram_testchip.v
@@ -1,6 +1,6 @@
 `default_nettype  none

-`include "control_logic.v"

-`include "sky130_sram_1kbyte_1rw1r_32x256_8.v"

+//`include "control_logic.v"

+//`include "sky130_sram_1kbyte_1rw1r_32x256_8.v"

 

 module openram_testchip(

     input clk_in,