commit 954cb248a178a3c2a1548b5f81522e8ca4ad319a
author AmoghLonkar <alonkar@ucsc.edu> Sat Jun 12 17:00:30 2021 -0700
committer AmoghLonkar <alonkar@ucsc.edu> Sat Jun 12 17:00:30 2021 -0700
tree f6c57524ea0533d3aeffdbf9d2f5fe05e58e832e
parent c52702bcf560bd63a9bdcd1298915491ce4cb924

Figure out why correct dout is not stored in sram_register

verilog/rtl/openram_testchip_tb.v

diff --git a/verilog/rtl/openram_testchip_tb.v b/verilog/rtl/openram_testchip_tb.v
index a3d6459..e4322c6 100644
--- a/verilog/rtl/openram_testchip_tb.v
+++ b/verilog/rtl/openram_testchip_tb.v
@@ -156,6 +156,7 @@
     $dumpvars(0, test_chip_tb);

     la_clk = 1;

     gpio_clk = 0;

+    la_sram_clk = 0;

     gpio_sram_clk = 0;

     gpio_in_scan = 0;

     gpio_bit = 0;

@@ -165,6 +166,7 @@
     //Send bits using logic analyzer

     in_select = 0;

     la_in_load = 1;

+    la_sram_load = 0;

     la_bits = {4'd0, 16'd1, 32'd1, 1'b0, 1'b0, 4'd15, 16'd0, 32'd0, 1'b1, 1'b1, 4'd0};

     

     #10;