Change reset to resetn
diff --git a/openlane/openram_testchip/config.tcl b/openlane/openram_testchip/config.tcl
index 8195c4f..6448023 100644
--- a/openlane/openram_testchip/config.tcl
+++ b/openlane/openram_testchip/config.tcl
@@ -8,10 +8,12 @@
set ::env(VERILOG_FILES) "$script_dir/../../verilog/rtl/openram_defines.v \
$script_dir/../../verilog/rtl/openram_testchip.v"
-#set ::env(BASE_SDC_FILE) "$script_dir/openram_testchip.sdc"
+set ::env(BASE_SDC_FILE) "$script_dir/openram_testchip.sdc"
set ::env(CLOCK_PORT) "la_clk"
set ::env(CLOCK_NET) "clk"
+set ::env(RESET_PORT) "resetn"
+
#set ::env(CLOCK_NET) ""
set ::env(CLOCK_PERIOD) "20"
set ::env(IO_PCT) 0.1
diff --git a/openlane/openram_testchip/openram_testchip.sdc b/openlane/openram_testchip/openram_testchip.sdc
index 5f91463..c96b83b 100644
--- a/openlane/openram_testchip/openram_testchip.sdc
+++ b/openlane/openram_testchip/openram_testchip.sdc
@@ -1,4 +1,4 @@
-create_clock [get_port $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD)
+create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD)
set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
puts "\[INFO\]: Setting output delay to: $output_delay_value"
@@ -7,17 +7,15 @@
set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]
set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
-#set rst_indx [lsearch [all_inputs] [get_port resetn]]
+set rst_indx [lsearch [all_inputs] [get_port $::env(RESET_PORT)]]
set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
-#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
-set all_inputs_wo_clk_rst $all_inputs_wo_clk
+set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
+#set all_inputs_wo_clk_rst $all_inputs_wo_clk
+
# correct resetn
set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
-#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}
-#set clk_indx [lsearch [all_outputs] [get_port sram*_clk]]
-#set all_outputs_wo_clk [lreplace [all_outputs] $clk_indx $clk_indx]
-#set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] $all_outputs_wo_clk
+set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] [get_port $::env(RESET_PORT)]
set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
# TODO set this as parameter
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 6748289..deb410e 100755
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -30,10 +30,14 @@
$script_dir/../../verilog/rtl/user_project_wrapper.v "
## Clock configurations
-set ::env(CLOCK_PORT) "la_sram_clk"
+# This is la_sram_clk
+# This should be la_data_in[126]
+#set ::env(CLOCK_PORT) "la_sram_clk"
+set ::env(CLOCK_PORT) {la_data_in\[126\]}
set ::env(CLOCK_NET) "sram_clk"
set ::env(CLOCK_PERIOD) "20"
+set ::env(BASE_SDC_FILE) "$script_dir/user_project_wrapper.sdc"
## Internal Macros
### Macro Placement
@@ -89,8 +93,8 @@
set ::env(PL_DIAMOND_SEARCH_HEIGHT) 500
set ::env(PL_RANDOM_GLB_PLACEMENT) 1
-set ::env(GLB_RT_ADJUSTMENT) 0.10
-set ::env(PL_TARGET_DENSITY) 0.7
+set ::env(GLB_RT_ADJUSTMENT) 0.25
+set ::env(PL_TARGET_DENSITY) 0.5
#set ::env(MAGIC_DRC_USE_GDS) 0
diff --git a/openlane/user_project_wrapper/user_project_wrapper.sdc b/openlane/user_project_wrapper/user_project_wrapper.sdc
new file mode 100644
index 0000000..c96b83b
--- /dev/null
+++ b/openlane/user_project_wrapper/user_project_wrapper.sdc
@@ -0,0 +1,25 @@
+create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD)
+set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
+set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
+puts "\[INFO\]: Setting output delay to: $output_delay_value"
+puts "\[INFO\]: Setting input delay to: $input_delay_value"
+
+set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]
+
+set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
+set rst_indx [lsearch [all_inputs] [get_port $::env(RESET_PORT)]]
+set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
+set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
+#set all_inputs_wo_clk_rst $all_inputs_wo_clk
+
+
+# correct resetn
+set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
+set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] [get_port $::env(RESET_PORT)]
+set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
+
+# TODO set this as parameter
+set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
+set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+puts "\[INFO\]: Setting load to: $cap_load"
+set_load $cap_load [all_outputs]
diff --git a/verilog/rtl/openram_testchip.v b/verilog/rtl/openram_testchip.v
index ef0036d..1768cca 100644
--- a/verilog/rtl/openram_testchip.v
+++ b/verilog/rtl/openram_testchip.v
@@ -11,12 +11,12 @@
inout vssd1, // User area 1 digital ground
inout vssd2, // User area 2 digital ground
`endif
- input reset,
+ input resetn,
// Select either GPIO or LA mode
input in_select,
-
+
input la_clk,
- input la_in_load,
+ input la_in_load,
input la_sram_load,
input [`TOTAL_SIZE-1:0] la_data_in,
// GPIO bit to clock control register
@@ -58,7 +58,7 @@
input [`DATA_SIZE-1:0] sram14_data1,
input [`DATA_SIZE-1:0] sram15_data0,
input [`DATA_SIZE-1:0] sram15_data1,
-
+
// Shared control/data to the SRAMs
output reg [`ADDR_SIZE-1:0] left_addr0,
output reg [`DATA_SIZE-1:0] left_din0,
@@ -80,7 +80,7 @@
output [`WMASK_SIZE-1:0] right_wmask0,
// One CSB for each SRAM
output [`MAX_CHIPS-1:0] right_csb0,
-
+
output reg [`TOTAL_SIZE-1:0] la_data_out,
output reg gpio_out
);
@@ -106,8 +106,8 @@
wire right_web0 = left_web0;
wire [`WMASK_SIZE-1:0] right_wmask0 = left_wmask0;
wire [`MAX_CHIPS-1:0] right_csb0 = left_csb0;
-
-
+
+
//Selecting clock pin
always @(*) begin
@@ -115,7 +115,7 @@
end
always @ (posedge clk) begin
- if(reset) begin
+ if(!resetn) begin
sram_register <= {`TOTAL_SIZE{1'b0}};
end
// GPIO scanning for transfer
@@ -128,11 +128,11 @@
end
// Store results for read out
else if(gpio_sram_load || la_sram_load) begin
-
- sram_register <= {sram_register[`TOTAL_SIZE-1:`TOTAL_SIZE-`SELECT_SIZE-`ADDR_SIZE],
- read_data0,
- sram_register[`ADDR_SIZE+`DATA_SIZE+2*`WMASK_SIZE+3:`DATA_SIZE+`WMASK_SIZE+2],
- read_data1,
+
+ sram_register <= {sram_register[`TOTAL_SIZE-1:`TOTAL_SIZE-`SELECT_SIZE-`ADDR_SIZE],
+ read_data0,
+ sram_register[`ADDR_SIZE+`DATA_SIZE+2*`WMASK_SIZE+3:`DATA_SIZE+`WMASK_SIZE+2],
+ read_data1,
sram_register[`WMASK_SIZE+1:0]};
end
end
@@ -146,22 +146,22 @@
csb0_temp = sram_register[`PORT_SIZE+`WMASK_SIZE+1];
left_web0 = sram_register[`PORT_SIZE+`WMASK_SIZE];
left_wmask0 = sram_register[`PORT_SIZE+`WMASK_SIZE-1:`PORT_SIZE];
-
+
left_addr1 = sram_register[`PORT_SIZE-1:`DATA_SIZE+`WMASK_SIZE+2];
left_din1 = sram_register[`DATA_SIZE+`WMASK_SIZE+1:`WMASK_SIZE+2];
csb1_temp = sram_register[`WMASK_SIZE+1];
left_web1 = sram_register[`WMASK_SIZE];
left_wmask1 = sram_register[`WMASK_SIZE-1:0];
-end
-
+end
+
// Apply the correct CSB
always @(*) begin
left_csb0 = ~( ~csb0_temp << chip_select);
left_csb1 = ~( ~csb1_temp << chip_select);
end
-
-// Mux value of correct SRAM data input to feed into
-// DFF clocked by la/gpio clk
+
+// Mux value of correct SRAM data input to feed into
+// DFF clocked by la/gpio clk
always @ (*) begin
case(chip_select)
4'd0: begin
@@ -238,5 +238,3 @@
end
endmodule
-
-
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
deleted file mode 100644
index b33e032..0000000
--- a/verilog/rtl/user_proj_example.v
+++ /dev/null
@@ -1,171 +0,0 @@
-// SPDX-FileCopyrightText: 2020 Efabless Corporation
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-
-`default_nettype none
-/*
- *-------------------------------------------------------------
- *
- * user_proj_example
- *
- * This is an example of a (trivially simple) user project,
- * showing how the user project can connect to the logic
- * analyzer, the wishbone bus, and the I/O pads.
- *
- * This project generates an integer count, which is output
- * on the user area GPIO pads (digital output only). The
- * wishbone connection allows the project to be controlled
- * (start and stop) from the management SoC program.
- *
- * See the testbenches in directory "mprj_counter" for the
- * example programs that drive this user project. The three
- * testbenches are "io_ports", "la_test1", and "la_test2".
- *
- *-------------------------------------------------------------
- */
-
-module user_proj_example #(
- parameter BITS = 32
-)(
-`ifdef USE_POWER_PINS
- inout vdda1, // User area 1 3.3V supply
- inout vdda2, // User area 2 3.3V supply
- inout vssa1, // User area 1 analog ground
- inout vssa2, // User area 2 analog ground
- inout vccd1, // User area 1 1.8V supply
- inout vccd2, // User area 2 1.8v supply
- inout vssd1, // User area 1 digital ground
- inout vssd2, // User area 2 digital ground
-`endif
-
- // Wishbone Slave ports (WB MI A)
- input wb_clk_i,
- input wb_rst_i,
- input wbs_stb_i,
- input wbs_cyc_i,
- input wbs_we_i,
- input [3:0] wbs_sel_i,
- input [31:0] wbs_dat_i,
- input [31:0] wbs_adr_i,
- output wbs_ack_o,
- output [31:0] wbs_dat_o,
-
- // Logic Analyzer Signals
- input [127:0] la_data_in,
- output [127:0] la_data_out,
- input [127:0] la_oenb,
-
- // IOs
- input [`MPRJ_IO_PADS-1:0] io_in,
- output [`MPRJ_IO_PADS-1:0] io_out,
- output [`MPRJ_IO_PADS-1:0] io_oeb,
-
- // IRQ
- output [2:0] irq
-);
- wire clk;
- wire rst;
-
- wire [`MPRJ_IO_PADS-1:0] io_in;
- wire [`MPRJ_IO_PADS-1:0] io_out;
- wire [`MPRJ_IO_PADS-1:0] io_oeb;
-
- wire [31:0] rdata;
- wire [31:0] wdata;
- wire [BITS-1:0] count;
-
- wire valid;
- wire [3:0] wstrb;
- wire [31:0] la_write;
-
- // WB MI A
- assign valid = wbs_cyc_i && wbs_stb_i;
- assign wstrb = wbs_sel_i & {4{wbs_we_i}};
- assign wbs_dat_o = rdata;
- assign wdata = wbs_dat_i;
-
- // IO
- assign io_out = count;
- assign io_oeb = {(`MPRJ_IO_PADS-1){rst}};
-
- // IRQ
- assign irq = 3'b000; // Unused
-
- // LA
- assign la_data_out = {{(127-BITS){1'b0}}, count};
- // Assuming LA probes [63:32] are for controlling the count register
- assign la_write = ~la_oenb[63:32] & ~{BITS{valid}};
- // Assuming LA probes [65:64] are for controlling the count clk & reset
- assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i;
- assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i;
-
- counter #(
- .BITS(BITS)
- ) counter(
- .clk(clk),
- .reset(rst),
- .ready(wbs_ack_o),
- .valid(valid),
- .rdata(rdata),
- .wdata(wbs_dat_i),
- .wstrb(wstrb),
- .la_write(la_write),
- .la_input(la_data_in[63:32]),
- .count(count)
- );
-
-endmodule
-
-module counter #(
- parameter BITS = 32
-)(
- input clk,
- input reset,
- input valid,
- input [3:0] wstrb,
- input [BITS-1:0] wdata,
- input [BITS-1:0] la_write,
- input [BITS-1:0] la_input,
- output ready,
- output [BITS-1:0] rdata,
- output [BITS-1:0] count
-);
- reg ready;
- reg [BITS-1:0] count;
- reg [BITS-1:0] rdata;
-
- always @(posedge clk) begin
- if (reset) begin
- count <= 0;
- ready <= 0;
- end else begin
- ready <= 1'b0;
- if (~|la_write) begin
- count <= count + 1;
- end
- if (valid && !ready) begin
- ready <= 1'b1;
- rdata <= count;
- if (wstrb[0]) count[7:0] <= wdata[7:0];
- if (wstrb[1]) count[15:8] <= wdata[15:8];
- if (wstrb[2]) count[23:16] <= wdata[23:16];
- if (wstrb[3]) count[31:24] <= wdata[31:24];
- end else if (|la_write) begin
- count <= la_write & la_input;
- end
- end
- end
-
-endmodule
-`default_nettype wire
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index aa559a2..5b1e7e3 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -91,7 +91,7 @@
// One CSB for each SRAM
wire [`MAX_CHIPS-1:0] csb0;
wire [`MAX_CHIPS-1:0] csb1;
-
+
wire [31:0] sram0_dout0;
@@ -124,10 +124,10 @@
wire [31:0] sram13_dout1;
wire [31:0] sram14_dout0;
wire [31:0] sram14_dout1;
-
+
wire in_select = io_in[16];
- wire in_reset = io_in[15];
+ wire resetn = io_in[15];
wire gpio_clk = io_in[17];
wire gpio_sram_clk = io_in[18];
wire gpio_scan = io_in[19];
@@ -140,22 +140,22 @@
wire gpio_out;
assign io_out[21] = gpio_out;
assign io_out[20:0] = 0;
-
+
wire la_sram_clk = la_data_in[126];
reg sram_clk;
-
+
always @(*) begin
sram_clk = in_select ? gpio_sram_clk : la_sram_clk;
end
-
+
openram_testchip CONTROL_LOGIC(
- .reset(in_reset|~wb_rst_i),
+ .resetn(resetn & wb_rst_i),
.in_select(in_select),
.gpio_clk(gpio_clk),
.gpio_scan(gpio_scan),
.gpio_sram_load(gpio_sram_load),
-
+
.la_clk(la_data_in[127]),
.la_in_load(la_data_in[125]),
.la_sram_load(la_data_in[124]),
@@ -174,7 +174,7 @@
// One CSB for each SRAM
.left_csb0(left_csb0),
.left_csb1(left_csb1),
-
+
// Shared control/data to the SRAMs
.right_addr0(right_addr0),
.right_din0(right_din0),
@@ -182,7 +182,7 @@
.right_wmask0(right_wmask0),
// One CSB for each SRAM
.right_csb0(right_csb0),
-
+
// SRAM data outputs to be captured
.sram0_data0(sram0_data0),
.sram0_data1(sram0_data1),
@@ -216,7 +216,7 @@
.sram14_data1(sram14_data1),
.sram15_data0(sram15_data0),
.sram15_data1(sram15_data1)
-
+
);
wire [`ADDR_SIZE-1:0] left_addr0;
@@ -235,7 +235,7 @@
wire right_web0;
wire [`WMASK_SIZE-1:0] right_wmask0;
wire [`MAX_CHIPS-1:0] right_csb0;
-
+
wire [`DATA_SIZE-1:0] sram0_dout0;
wire [`DATA_SIZE-1:0] sram0_dout1;
wire [`DATA_SIZE-1:0] sram1_dout0;
@@ -273,7 +273,7 @@
(
`ifdef USE_POWER_PINS
.vccd1(vccd1),
- .vssd1(vssd1),
+ .vssd1(vssd1),
`endif
.clk0 (sram_clk),
.csb0 (left_csb0[0]),
@@ -289,12 +289,12 @@
);
assign sram0_dout0[`DATA_SIZE-1:8] = 0;
assign sram0_dout1[`DATA_SIZE-1:8] = 0;
-
+
sky130_sram_1kbyte_1rw1r_32x256_8 SRAM1
(
`ifdef USE_POWER_PINS
.vccd1(vccd1),
- .vssd1(vssd1),
+ .vssd1(vssd1),
`endif
.clk0 (sram_clk),
.csb0 (left_csb0[1]),
@@ -308,12 +308,12 @@
.addr1 (left_addr1),
.dout1 (sram1_dout1)
);
-
+
sky130_sram_2kbyte_1rw1r_32x512_8 SRAM2
(
`ifdef USE_POWER_PINS
.vccd1(vccd1),
- .vssd1(vssd1),
+ .vssd1(vssd1),
`endif
.clk0 (sram_clk),
.csb0 (left_csb0[2]),
@@ -332,7 +332,7 @@
(
`ifdef USE_POWER_PINS
.vccd1(vccd1),
- .vssd1(vssd1),
+ .vssd1(vssd1),
`endif
.clk0 (sram_clk),
.csb0 (left_csb0[3]),
@@ -346,12 +346,12 @@
.addr1 (left_addr1),
.dout1 (sram3_dout1)
);
-
+
sky130_sram_8kbyte_1rw1r_32x2048_8 SRAM4
(
`ifdef USE_POWER_PINS
.vccd1(vccd1),
- .vssd1(vssd1),
+ .vssd1(vssd1),
`endif
.clk0 (sram_clk),
.csb0 (left_csb0[4]),
@@ -371,7 +371,7 @@
// (
// `ifdef USE_POWER_PINS
// .vccd1(vccd1),
-// .vssd1(vssd1),
+// .vssd1(vssd1),
// `endif
// .clk0 (sram_clk),
// .csb0 (csb0[6]),
@@ -385,15 +385,15 @@
// .addr1 (addr1),
// .dout1 (sram6_dout1)
// );
-
-
+
+
// Single port memories
sram_1rw0r0w_32_256_sky130 SRAM8
(
`ifdef USE_POWER_PINS
.vccd1(vccd1),
- .vssd1(vssd1),
+ .vssd1(vssd1),
`endif
.clk0 (sram_clk),
.csb0 (right_csb0[8]),
@@ -409,7 +409,7 @@
(
`ifdef USE_POWER_PINS
.vccd1(vccd1),
- .vssd1(vssd1),
+ .vssd1(vssd1),
`endif
.clk0 (sram_clk),
.csb0 (right_csb0[9]),
@@ -425,7 +425,7 @@
(
`ifdef USE_POWER_PINS
.vccd1(vccd1),
- .vssd1(vssd1),
+ .vssd1(vssd1),
`endif
.clk0 (sram_clk),
.csb0 (right_csb0[10]),
@@ -442,7 +442,7 @@
(
`ifdef USE_POWER_PINS
.vccd1(vccd1),
- .vssd1(vssd1),
+ .vssd1(vssd1),
`endif
.clk0 (sram_clk),
.csb0 (right_csb0[11]),
@@ -457,7 +457,7 @@
-
+
// Hold dout from SRAM
// clocked by SRAM clk
reg [`DATA_SIZE-1:0] sram0_data0;
@@ -492,9 +492,9 @@
reg [`DATA_SIZE-1:0] sram14_data1;
reg [`DATA_SIZE-1:0] sram15_data0;
reg [`DATA_SIZE-1:0] sram15_data1;
-
+
always @(posedge sram_clk) begin
- if (in_reset) begin
+ if (!resetn) begin
sram0_data0 <= 0;
sram0_data1 <= 0;
sram1_data0 <= 0;
@@ -563,7 +563,7 @@
// sram15_data1 <= sram15_dout1;
end // else: !if(in_reset)
end
-
+
assign sram5_data0 = 0;
assign sram5_data1 = 0;
assign sram6_data0 = 0;
@@ -578,7 +578,7 @@
assign sram14_data1 = 0;
assign sram15_data0 = 0;
assign sram15_data1 = 0;
-
+
endmodule // user_project_wrapper
