remove extra folders

openlane/openram_testchip/config.tcl

diff --git a/openlane/openram_testchip/config.tcl b/openlane/openram_testchip/config.tcl
deleted file mode 100644
index 04304b9..0000000
--- a/openlane/openram_testchip/config.tcl
+++ /dev/null
@@ -1,35 +0,0 @@
-set script_dir [file dirname [file normalize [info script]]]
-
-set ::env(DESIGN_NAME) openram_testchip
-
-set ::env(DESIGN_IS_CORE) 0
-set ::env(FP_PDN_CORE_RING) 0
-set ::env(GLB_RT_MAXLAYER) 5
-
-set ::env(VERILOG_FILES) "$script_dir/../../verilog/rtl/testchip/openram_testchip.v"
-
-set ::env(CLOCK_PORT) "clock"
-set ::env(CLOCK_PERIOD) "10"
-
-# Fill this
-set ::env(DESIGN_IS_CORE) 0
-set ::env(FP_PDN_CORE_RING) 0
-set ::env(GLB_RT_MAXLAYER) 5
-
-set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 1200 1200"
-
-set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 0
-set ::env(PL_RANDOM_GLB_PLACEMENT) 1
-set ::env(PL_BASIC_PLACEMENT) 1
-set ::env(PL_TARGET_DENSITY) 0.99
-
-# Power config
-set ::env(PDN_CFG) $script_dir/pdn.tcl
-
-set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
-if { [file exists $filename] == 1} {
-	source $filename
-}
-
-

openlane/openram_testchip/pdn.tcl

diff --git a/openlane/openram_testchip/pdn.tcl b/openlane/openram_testchip/pdn.tcl
deleted file mode 100644
index 4ce71c4..0000000
--- a/openlane/openram_testchip/pdn.tcl
+++ /dev/null
@@ -1,34 +0,0 @@
-# Power nets

-set ::power_nets $::env(VDD_PIN)

-set ::ground_nets $::env(GND_PIN)

-

-set ::macro_blockage_layer_list "li1 met1 met2 met3 met4 met5"

-

-pdngen::specify_grid stdcell {

-    name grid

-    rails {

-	    met1 {width 0.48 pitch $::env(PLACE_SITE_HEIGHT) offset 0}

-    }

-    straps {

-	    met4 {width 1.6 pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)}

-	    met5 {width 1.6 pitch $::env(FP_PDN_HPITCH) offset $::env(FP_PDN_HOFFSET)}

-    }

-    connect {{met1 met4} {met4 met5}}

-}

-

-pdngen::specify_grid macro {

-    power_pins "VPWR VDD vdd"

-    ground_pins "VGND VSS gnd"

-    blockages "li1 met1 met2 met3 met4"

-    straps { 

-    } 

-    connect {{met4_PIN_ver met5} {met3_PIN_hor met5}}

-}

-

-set ::halo $::env(FP_HORIZONTAL_HALO)

-

-# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area

-set ::rails_start_with "POWER" ;

-

-# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area

-set ::stripes_start_with "POWER" ;
\ No newline at end of file

openlane/user_proj_example/config.tcl

diff --git a/openlane/user_proj_example/config.tcl b/openlane/user_proj_example/config.tcl
deleted file mode 100755
index 4ea25c6..0000000
--- a/openlane/user_proj_example/config.tcl
+++ /dev/null
@@ -1,41 +0,0 @@
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-
-set script_dir [file dirname [file normalize [info script]]]
-
-set ::env(DESIGN_NAME) user_proj_example
-
-set ::env(VERILOG_FILES) "\
-	$script_dir/../../caravel/verilog/rtl/defines.v \
-	$script_dir/../../verilog/rtl/user_proj_example.v"
-
-set ::env(CLOCK_PORT) ""
-set ::env(CLOCK_NET) "counter.clk"
-set ::env(CLOCK_PERIOD) "10"
-
-set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 900 600"
-set ::env(DESIGN_IS_CORE) 0
-
-set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}]
-set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}]
-
-set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
-
-set ::env(PL_BASIC_PLACEMENT) 1
-set ::env(PL_TARGET_DENSITY) 0.05
-
-# If you're going to use multiple power domains, then keep this disabled.
-set ::env(RUN_CVC) 0

openlane/user_proj_example/pin_order.cfg

diff --git a/openlane/user_proj_example/pin_order.cfg b/openlane/user_proj_example/pin_order.cfg
deleted file mode 100644
index 8128f78..0000000
--- a/openlane/user_proj_example/pin_order.cfg
+++ /dev/null
@@ -1,9 +0,0 @@
-#BUS_SORT
-
-#S
-wb_.*
-wbs_.*
-la_.*
-
-#N
-io_.*