Single port for gpio scanning, connected out_data to MSB
diff --git a/verilog/rtl/openram_testchip.v b/verilog/rtl/openram_testchip.v
index 2f1b930..db1b1e5 100644
--- a/verilog/rtl/openram_testchip.v
+++ b/verilog/rtl/openram_testchip.v
@@ -15,10 +15,9 @@
input gpio_sram_clk,
input reset,
input la_in_load,
- input gpio_in_scan,
+ input gpio_scan,
input la_sram_load,
input gpio_sram_load,
- input gpio_out_scan,
input [111:0] la_bits,
input gpio_bit,
input in_select,
@@ -89,8 +88,8 @@
if(reset) begin
sram_register <= 112'd1;
end
- //GPIO scanning for input transfer
- else if(gpio_in_scan) begin
+ //GPIO scanning for transfer
+ else if(gpio_scan) begin
sram_register <= {sram_register[110:0], gpio_bit};
end
else if(la_in_load) begin
@@ -100,10 +99,6 @@
sram_register <= {sram_register[111:92], read_data0, sram_register[59:38], read_data1, sram_register[5:0]};
//sram_register <= sram_register;
end
- //GPIO scanning for output transfer
- else if(gpio_out_scan) begin
- sram_register <= sram_register >> 1;
- end
end
// Splitting register bits into fields
@@ -206,8 +201,8 @@
// Output transfer
always @ (*) begin
if(in_select) begin
- gpio_data0 = sram_register[60];
- gpio_data1 = sram_register[6];
+ gpio_data0 = sram_register[91];
+ gpio_data1 = sram_register[37];
end
else begin
la_data0 = sram_register[91:60];
diff --git a/verilog/rtl/openram_testchip_tb.v b/verilog/rtl/openram_testchip_tb.v
index d39a2d2..a6ce1d4 100644
--- a/verilog/rtl/openram_testchip_tb.v
+++ b/verilog/rtl/openram_testchip_tb.v
@@ -21,10 +21,9 @@
reg gpio_sram_clk;
reg reset;
reg la_in_load;
- reg gpio_in_scan;
+ reg gpio_scan;
reg la_sram_load;
reg gpio_sram_load;
- reg gpio_out_scan;
reg [111:0] la_bits;
reg gpio_bit;
reg in_select;
@@ -54,10 +53,9 @@
.gpio_sram_clk(gpio_sram_clk),
.reset(reset),
.la_in_load(la_in_load),
- .gpio_in_scan(gpio_in_scan),
+ .gpio_scan(gpio_scan),
.la_sram_load(la_sram_load),
.gpio_sram_load(gpio_sram_load),
- .gpio_out_scan(gpio_out_scan),
.la_bits(la_bits),
.gpio_bit(gpio_bit),
.in_select(in_select),
@@ -158,9 +156,8 @@
gpio_clk = 0;
la_sram_clk = 0;
gpio_sram_clk = 0;
- gpio_in_scan = 0;
+ gpio_scan = 0;
gpio_bit = 0;
- gpio_out_scan = 0;
reset = 0;
//Send bits using logic analyzer