commit: 6ec2acd52533e01d1b516e86a93b466b9a0fe2e4
[log] [tgz]
author: AmoghLonkar <alonkar@ucsc.edu>
Wed Jun 16 09:45:16 2021 -0700
committer: AmoghLonkar <alonkar@ucsc.edu>
Wed Jun 16 09:45:16 2021 -0700
tree: c7d99b0ddd0aba02d7e97687af513296a00145c4
parent: af01516d9ad272c99ee91001710fa1411d1eeee9 [diff]

Switched from index to explicitly declared shift

verilog/rtl/openram_testchip.v[diff]

1 file changed

tree: c7d99b0ddd0aba02d7e97687af513296a00145c4

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for this sample project documentation.