Delete chisel directory
diff --git a/chisel/control_logic-main.zip:Zone.Identifier b/chisel/control_logic-main.zip:Zone.Identifier
deleted file mode 100644
index 3cac1a1..0000000
--- a/chisel/control_logic-main.zip:Zone.Identifier
+++ /dev/null
@@ -1,4 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
-ReferrerUrl=https://github.com/AmoghLonkar/control_logic
-HostUrl=https://codeload.github.com/AmoghLonkar/control_logic/zip/refs/heads/main
diff --git a/chisel/control_logic-main/control_logic-main/.github/workflows/test.yml b/chisel/control_logic-main/control_logic-main/.github/workflows/test.yml
deleted file mode 100644
index 75dfeef..0000000
--- a/chisel/control_logic-main/control_logic-main/.github/workflows/test.yml
+++ /dev/null
@@ -1,19 +0,0 @@
-name: Continuous Integration
-
-on: [push, pull_request]
-
-jobs:
- ci:
- name: ci
- runs-on: ubuntu-latest
- steps:
- - name: Checkout
- uses: actions/checkout@v2
- - name: Setup Scala
- uses: olafurpg/setup-scala@v10
- with:
- java-version: adopt@1.8
- - name: Cache Scala
- uses: coursier/cache-action@v5
- - name: Test
- run: sbt test
diff --git a/chisel/control_logic-main/control_logic-main/.gitignore b/chisel/control_logic-main/control_logic-main/.gitignore
deleted file mode 100644
index 12033d3..0000000
--- a/chisel/control_logic-main/control_logic-main/.gitignore
+++ /dev/null
@@ -1,341 +0,0 @@
-### Project Specific stuff
-test_run_dir/*
-### XilinxISE template
-# intermediate build files
-*.bgn
-*.bit
-*.bld
-*.cmd_log
-*.drc
-*.ll
-*.lso
-*.msd
-*.msk
-*.ncd
-*.ngc
-*.ngd
-*.ngr
-*.pad
-*.par
-*.pcf
-*.prj
-*.ptwx
-*.rbb
-*.rbd
-*.stx
-*.syr
-*.twr
-*.twx
-*.unroutes
-*.ut
-*.xpi
-*.xst
-*_bitgen.xwbt
-*_envsettings.html
-*_map.map
-*_map.mrp
-*_map.ngm
-*_map.xrpt
-*_ngdbuild.xrpt
-*_pad.csv
-*_pad.txt
-*_par.xrpt
-*_summary.html
-*_summary.xml
-*_usage.xml
-*_xst.xrpt
-
-# project-wide generated files
-*.gise
-par_usage_statistics.html
-usage_statistics_webtalk.html
-webtalk.log
-webtalk_pn.xml
-
-# generated folders
-iseconfig/
-xlnx_auto_0_xdb/
-xst/
-_ngo/
-_xmsgs/
-### Eclipse template
-*.pydevproject
-.metadata
-.gradle
-bin/
-tmp/
-*.tmp
-*.bak
-*.swp
-*~.nib
-local.properties
-.settings/
-.loadpath
-
-# Eclipse Core
-.project
-
-# External tool builders
-.externalToolBuilders/
-
-# Locally stored "Eclipse launch configurations"
-*.launch
-
-# CDT-specific
-.cproject
-
-# JDT-specific (Eclipse Java Development Tools)
-.classpath
-
-# Java annotation processor (APT)
-.factorypath
-
-# PDT-specific
-.buildpath
-
-# sbteclipse plugin
-.target
-
-# TeXlipse plugin
-.texlipse
-### C template
-# Object files
-*.o
-*.ko
-*.obj
-*.elf
-
-# Precompiled Headers
-*.gch
-*.pch
-
-# Libraries
-*.lib
-*.a
-*.la
-*.lo
-
-# Shared objects (inc. Windows DLLs)
-*.dll
-*.so
-*.so.*
-*.dylib
-
-# Executables
-*.exe
-*.out
-*.app
-*.i*86
-*.x86_64
-*.hex
-
-# Debug files
-*.dSYM/
-### SBT template
-# Simple Build Tool
-# http://www.scala-sbt.org/release/docs/Getting-Started/Directories.html#configuring-version-control
-
-target/
-lib_managed/
-src_managed/
-project/boot/
-.history
-.cache
-### Emacs template
-# -*- mode: gitignore; -*-
-*~
-\#*\#
-/.emacs.desktop
-/.emacs.desktop.lock
-*.elc
-auto-save-list
-tramp
-.\#*
-
-# Org-mode
-.org-id-locations
-*_archive
-
-# flymake-mode
-*_flymake.*
-
-# eshell files
-/eshell/history
-/eshell/lastdir
-
-# elpa packages
-/elpa/
-
-# reftex files
-*.rel
-
-# AUCTeX auto folder
-/auto/
-
-# cask packages
-.cask/
-### Vim template
-[._]*.s[a-w][a-z]
-[._]s[a-w][a-z]
-*.un~
-Session.vim
-.netrwhist
-*~
-### JetBrains template
-# Covers JetBrains IDEs: IntelliJ, RubyMine, PhpStorm, AppCode, PyCharm, CLion, Android Studio
-
-*.iml
-
-## Directory-based project format:
-.idea/
-# if you remove the above rule, at least ignore the following:
-
-# User-specific stuff:
-# .idea/workspace.xml
-# .idea/tasks.xml
-# .idea/dictionaries
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-# Sensitive or high-churn files:
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-# Mongo Explorer plugin:
-# .idea/mongoSettings.xml
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-# IntelliJ
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-.idea_modules/
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-
-# Crashlytics plugin (for Android Studio and IntelliJ)
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-crashlytics-build.properties
-### C++ template
-# Compiled Object files
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-*.obj
-
-# Precompiled Headers
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-*.pch
-
-# Compiled Dynamic libraries
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-# Fortran module files
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-
-# Compiled Static libraries
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-*.la
-*.a
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-
-# Executables
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-*.out
-*.app
-### OSX template
-.DS_Store
-.AppleDouble
-.LSOverride
-
-# Icon must end with two \r
-Icon
-
-# Thumbnails
-._*
-
-# Files that might appear in the root of a volume
-.DocumentRevisions-V100
-.fseventsd
-.Spotlight-V100
-.TemporaryItems
-.Trashes
-.VolumeIcon.icns
-
-# Directories potentially created on remote AFP share
-.AppleDB
-.AppleDesktop
-Network Trash Folder
-Temporary Items
-.apdisk
-### Xcode template
-# Xcode
-#
-# gitignore contributors: remember to update Global/Xcode.gitignore, Objective-C.gitignore & Swift.gitignore
-
-## Build generated
-build/
-DerivedData
-
-## Various settings
-*.pbxuser
-!default.pbxuser
-*.mode1v3
-!default.mode1v3
-*.mode2v3
-!default.mode2v3
-*.perspectivev3
-!default.perspectivev3
-xcuserdata
-
-## Other
-*.xccheckout
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-# sbt specific
-.cache
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-project/plugins/project/
-
-# Scala-IDE specific
-.scala_dependencies
-.worksheet
-### Java template
-*.class
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-# Mobile Tools for Java (J2ME)
-.mtj.tmp/
-
-# Package Files #
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-
-# virtual machine crash logs, see http://www.java.com/en/download/help/error_hotspot.xml
-hs_err_pid*
-
diff --git a/chisel/control_logic-main/control_logic-main/README.md b/chisel/control_logic-main/control_logic-main/README.md
deleted file mode 100644
index b40418d..0000000
--- a/chisel/control_logic-main/control_logic-main/README.md
+++ /dev/null
@@ -1,12 +0,0 @@
-Control Logic Generator for OpenRAM Test Chip
-=======================
-This repo contains an implementation of a hardware generator for the control logic required for the OpenRAM Test Chip.
-It is designed to receive an input packet from either the logic analyzer or GPIO pins and forward it to the desired SRAM module.
-For a read operation, the logic will read back data from the SRAM and send it to the CPU via the interface.
-
-### Steps to Run
-Once cloned and entered the top level directory, we can run the provided tests and generate synthesizable verilog.
-
-1.) To generate verilog, type and enter `sbt run` in the terminal.
-
-2.) To run the tests, type and enter `sbt test` in the terminal.
diff --git a/chisel/control_logic-main/control_logic-main/build.sbt b/chisel/control_logic-main/control_logic-main/build.sbt
deleted file mode 100644
index cf21897..0000000
--- a/chisel/control_logic-main/control_logic-main/build.sbt
+++ /dev/null
@@ -1,26 +0,0 @@
-// See README.md for license details.
-
-ThisBuild / scalaVersion := "2.12.13"
-ThisBuild / version := "0.1.0"
-ThisBuild / organization := "com.github.amoghlonkar"
-
-lazy val root = (project in file("."))
- .settings(
- name := "control_logic",
- libraryDependencies ++= Seq(
- "edu.berkeley.cs" %% "chisel3" % "3.4.3",
- "edu.berkeley.cs" %% "chiseltest" % "0.3.3" % "test"
- ),
- scalacOptions ++= Seq(
- "-Xsource:2.11",
- "-language:reflectiveCalls",
- "-deprecation",
- "-feature",
- "-Xcheckinit",
- // Enables autoclonetype2 in 3.4.x (on by default in 3.5)
- "-P:chiselplugin:useBundlePlugin"
- ),
- addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % "3.4.3" cross CrossVersion.full),
- addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.1" cross CrossVersion.full)
- )
-
diff --git a/chisel/control_logic-main/control_logic-main/openram_testchip.v b/chisel/control_logic-main/control_logic-main/openram_testchip.v
deleted file mode 100644
index e9c7e29..0000000
--- a/chisel/control_logic-main/control_logic-main/openram_testchip.v
+++ /dev/null
@@ -1,239 +0,0 @@
-module openram_testchip(
- input clock,
- input reset,
- input [85:0] io_logical_analyzer_packet,
- input [31:0] io_gpio_packet,
- input io_in_select,
- input [31:0] io_sram0_rw_in,
- input [31:0] io_sram0_r0_in,
- input [31:0] io_sram1_rw_in,
- input [31:0] io_sram1_ro_in,
- input [31:0] io_sram2_rw_in,
- input [31:0] io_sram3_rw_in,
- input [31:0] io_sram4_rw_in,
- input [63:0] io_sram5_rw_in,
- output [54:0] io_sram0_connections,
- output [54:0] io_sram1_connections,
- output [47:0] io_sram2_connections,
- output [45:0] io_sram3_connections,
- output [46:0] io_sram4_connections,
- output [82:0] io_sram5_connections,
- output [63:0] io_la_data,
- output [31:0] io_gpio_data
-);
-`ifdef RANDOMIZE_REG_INIT
- reg [95:0] _RAND_0;
- reg [63:0] _RAND_1;
- reg [31:0] _RAND_2;
- reg [31:0] _RAND_3;
- reg [31:0] _RAND_4;
- reg [31:0] _RAND_5;
- reg [31:0] _RAND_6;
- reg [31:0] _RAND_7;
- reg [31:0] _RAND_8;
- reg [31:0] _RAND_9;
- reg [31:0] _RAND_10;
- reg [31:0] _RAND_11;
- reg [31:0] _RAND_12;
-`endif // RANDOMIZE_REG_INIT
- reg [85:0] input_; // @[openram_testchip.scala 33:20]
- reg [63:0] output_; // @[openram_testchip.scala 34:21]
- reg in_sel; // @[openram_testchip.scala 35:25]
- reg gpio_sel; // @[openram_testchip.scala 37:27]
- reg la_sel; // @[openram_testchip.scala 38:25]
- reg SRAMDataReceived; // @[openram_testchip.scala 47:35]
- wire _T = ~gpio_sel; // @[openram_testchip.scala 48:68]
- reg [1:0] loadingCount; // @[Counter.scala 60:40]
- wire wrap_wrap = loadingCount == 2'h2; // @[Counter.scala 72:24]
- wire [1:0] _wrap_value_T_1 = loadingCount + 2'h1; // @[Counter.scala 76:24]
- wire _GEN_2 = gpio_sel & wrap_wrap; // @[Counter.scala 137:24 Counter.scala 138:12]
- reg REG; // @[openram_testchip.scala 49:67]
- reg transferCount; // @[Counter.scala 60:40]
- reg wrap; // @[openram_testchip.scala 51:23]
- reg [31:0] packetSeq_0; // @[openram_testchip.scala 52:24]
- reg [31:0] packetSeq_1; // @[openram_testchip.scala 52:24]
- reg [31:0] packetSeq_2; // @[openram_testchip.scala 52:24]
- wire [95:0] _input_T = {packetSeq_2,packetSeq_1,packetSeq_0}; // @[Cat.scala 30:58]
- wire [95:0] _GEN_9 = wrap & gpio_sel ? _input_T : {{10'd0}, io_logical_analyzer_packet}; // @[openram_testchip.scala 60:27 openram_testchip.scala 61:15 openram_testchip.scala 55:11]
- wire [95:0] _GEN_10 = _T ? {{10'd0}, input_} : _GEN_9; // @[openram_testchip.scala 64:20 openram_testchip.scala 65:15]
- wire [2:0] chip_select = input_[85:83]; // @[openram_testchip.scala 67:34]
- wire csb0 = input_[54]; // @[openram_testchip.scala 76:21]
- wire web = input_[53]; // @[openram_testchip.scala 77:20]
- wire _T_5 = _T | ~la_sel; // @[openram_testchip.scala 79:20]
- wire _T_6 = 3'h0 == chip_select; // @[Conditional.scala 37:30]
- wire _T_7 = 3'h1 == chip_select; // @[Conditional.scala 37:30]
- wire _T_8 = 3'h2 == chip_select; // @[Conditional.scala 37:30]
- wire _T_9 = 3'h3 == chip_select; // @[Conditional.scala 37:30]
- wire _T_10 = 3'h4 == chip_select; // @[Conditional.scala 37:30]
- wire _T_11 = 3'h5 == chip_select; // @[Conditional.scala 37:30]
- wire [82:0] _GEN_11 = _T_11 ? input_[82:0] : 83'h7ffffffffffffffffffff; // @[Conditional.scala 39:67 openram_testchip.scala 103:38 openram_testchip.scala 74:26]
- wire [46:0] _GEN_12 = _T_10 ? input_[46:0] : 47'h7fffffffffff; // @[Conditional.scala 39:67 openram_testchip.scala 99:38 openram_testchip.scala 73:26]
- wire [82:0] _GEN_13 = _T_10 ? 83'h7ffffffffffffffffffff : _GEN_11; // @[Conditional.scala 39:67 openram_testchip.scala 74:26]
- wire [45:0] _GEN_14 = _T_9 ? input_[45:0] : 46'h3fffffffffff; // @[Conditional.scala 39:67 openram_testchip.scala 95:38 openram_testchip.scala 72:26]
- wire [46:0] _GEN_15 = _T_9 ? 47'h7fffffffffff : _GEN_12; // @[Conditional.scala 39:67 openram_testchip.scala 73:26]
- wire [82:0] _GEN_16 = _T_9 ? 83'h7ffffffffffffffffffff : _GEN_13; // @[Conditional.scala 39:67 openram_testchip.scala 74:26]
- wire [47:0] _GEN_17 = _T_8 ? input_[47:0] : 48'hffffffffffff; // @[Conditional.scala 39:67 openram_testchip.scala 91:38 openram_testchip.scala 71:26]
- wire [45:0] _GEN_18 = _T_8 ? 46'h3fffffffffff : _GEN_14; // @[Conditional.scala 39:67 openram_testchip.scala 72:26]
- wire [46:0] _GEN_19 = _T_8 ? 47'h7fffffffffff : _GEN_15; // @[Conditional.scala 39:67 openram_testchip.scala 73:26]
- wire [82:0] _GEN_20 = _T_8 ? 83'h7ffffffffffffffffffff : _GEN_16; // @[Conditional.scala 39:67 openram_testchip.scala 74:26]
- wire [54:0] _GEN_21 = _T_7 ? input_[54:0] : 55'h7fffffffffffff; // @[Conditional.scala 39:67 openram_testchip.scala 87:38 openram_testchip.scala 70:26]
- wire [47:0] _GEN_22 = _T_7 ? 48'hffffffffffff : _GEN_17; // @[Conditional.scala 39:67 openram_testchip.scala 71:26]
- wire [45:0] _GEN_23 = _T_7 ? 46'h3fffffffffff : _GEN_18; // @[Conditional.scala 39:67 openram_testchip.scala 72:26]
- wire [46:0] _GEN_24 = _T_7 ? 47'h7fffffffffff : _GEN_19; // @[Conditional.scala 39:67 openram_testchip.scala 73:26]
- wire [82:0] _GEN_25 = _T_7 ? 83'h7ffffffffffffffffffff : _GEN_20; // @[Conditional.scala 39:67 openram_testchip.scala 74:26]
- wire [54:0] _GEN_26 = _T_6 ? input_[54:0] : 55'h7fffffffffffff; // @[Conditional.scala 40:58 openram_testchip.scala 83:38 openram_testchip.scala 69:26]
- wire [54:0] _GEN_27 = _T_6 ? 55'h7fffffffffffff : _GEN_21; // @[Conditional.scala 40:58 openram_testchip.scala 70:26]
- wire [47:0] _GEN_28 = _T_6 ? 48'hffffffffffff : _GEN_22; // @[Conditional.scala 40:58 openram_testchip.scala 71:26]
- wire [45:0] _GEN_29 = _T_6 ? 46'h3fffffffffff : _GEN_23; // @[Conditional.scala 40:58 openram_testchip.scala 72:26]
- wire [46:0] _GEN_30 = _T_6 ? 47'h7fffffffffff : _GEN_24; // @[Conditional.scala 40:58 openram_testchip.scala 73:26]
- wire [82:0] _GEN_31 = _T_6 ? 83'h7ffffffffffffffffffff : _GEN_25; // @[Conditional.scala 40:58 openram_testchip.scala 74:26]
- wire [31:0] _output_T = csb0 ? io_sram0_r0_in : io_sram0_rw_in; // @[openram_testchip.scala 114:30]
- wire [31:0] _output_T_1 = csb0 ? io_sram1_ro_in : io_sram1_rw_in; // @[openram_testchip.scala 118:31]
- wire [63:0] _GEN_38 = _T_11 ? io_sram5_rw_in : 64'h0; // @[Conditional.scala 39:67 openram_testchip.scala 134:24 openram_testchip.scala 108:12]
- wire [63:0] _GEN_39 = _T_10 ? {{32'd0}, io_sram4_rw_in} : _GEN_38; // @[Conditional.scala 39:67 openram_testchip.scala 130:24]
- wire [63:0] _GEN_40 = _T_9 ? {{32'd0}, io_sram3_rw_in} : _GEN_39; // @[Conditional.scala 39:67 openram_testchip.scala 126:24]
- wire _GEN_44 = in_sel | SRAMDataReceived; // @[openram_testchip.scala 138:29 openram_testchip.scala 139:30 openram_testchip.scala 47:35]
- wire _GEN_46 = web ? _GEN_44 : SRAMDataReceived; // @[openram_testchip.scala 110:14 openram_testchip.scala 47:35]
- wire [31:0] _GEN_47 = transferCount ? output_[63:32] : 32'h0; // @[openram_testchip.scala 148:42 openram_testchip.scala 149:26 openram_testchip.scala 144:18]
- wire [31:0] _GEN_49 = ~transferCount ? output_[31:0] : _GEN_47; // @[openram_testchip.scala 146:36 openram_testchip.scala 147:26]
- assign io_sram0_connections = _T_5 ? _GEN_26 : 55'h7fffffffffffff; // @[openram_testchip.scala 80:5 openram_testchip.scala 69:26]
- assign io_sram1_connections = _T_5 ? _GEN_27 : 55'h7fffffffffffff; // @[openram_testchip.scala 80:5 openram_testchip.scala 70:26]
- assign io_sram2_connections = _T_5 ? _GEN_28 : 48'hffffffffffff; // @[openram_testchip.scala 80:5 openram_testchip.scala 71:26]
- assign io_sram3_connections = _T_5 ? _GEN_29 : 46'h3fffffffffff; // @[openram_testchip.scala 80:5 openram_testchip.scala 72:26]
- assign io_sram4_connections = _T_5 ? _GEN_30 : 47'h7fffffffffff; // @[openram_testchip.scala 80:5 openram_testchip.scala 73:26]
- assign io_sram5_connections = _T_5 ? _GEN_31 : 83'h7ffffffffffffffffffff; // @[openram_testchip.scala 80:5 openram_testchip.scala 74:26]
- assign io_la_data = in_sel ? 64'h0 : output_; // @[openram_testchip.scala 145:25 openram_testchip.scala 143:16 openram_testchip.scala 153:20]
- assign io_gpio_data = in_sel ? _GEN_49 : 32'h0; // @[openram_testchip.scala 145:25 openram_testchip.scala 144:18]
- always @(posedge clock) begin
- input_ <= _GEN_10[85:0];
- if (web) begin // @[openram_testchip.scala 110:14]
- if (_T_6) begin // @[Conditional.scala 40:58]
- output_ <= {{32'd0}, _output_T}; // @[openram_testchip.scala 114:24]
- end else if (_T_7) begin // @[Conditional.scala 39:67]
- output_ <= {{32'd0}, _output_T_1}; // @[openram_testchip.scala 118:24]
- end else if (_T_8) begin // @[Conditional.scala 39:67]
- output_ <= {{32'd0}, io_sram2_rw_in}; // @[openram_testchip.scala 122:24]
- end else begin
- output_ <= _GEN_40;
- end
- end else begin
- output_ <= 64'h0; // @[openram_testchip.scala 108:12]
- end
- in_sel <= io_in_select; // @[openram_testchip.scala 35:25]
- gpio_sel <= reset | ~wrap & gpio_sel; // @[openram_testchip.scala 37:27 openram_testchip.scala 37:27 openram_testchip.scala 57:14]
- la_sel <= io_in_select; // @[openram_testchip.scala 38:25]
- if (reset) begin // @[openram_testchip.scala 47:35]
- SRAMDataReceived <= 1'h0; // @[openram_testchip.scala 47:35]
- end else if (in_sel) begin // @[openram_testchip.scala 145:25]
- if (~transferCount) begin // @[openram_testchip.scala 146:36]
- SRAMDataReceived <= _GEN_46;
- end else if (transferCount) begin // @[openram_testchip.scala 148:42]
- SRAMDataReceived <= 1'h0; // @[openram_testchip.scala 150:30]
- end else begin
- SRAMDataReceived <= _GEN_46;
- end
- end else begin
- SRAMDataReceived <= _GEN_46;
- end
- if (reset) begin // @[Counter.scala 60:40]
- loadingCount <= 2'h0; // @[Counter.scala 60:40]
- end else if (_T) begin // @[Counter.scala 135:17]
- loadingCount <= 2'h0; // @[Counter.scala 97:11]
- end else if (gpio_sel) begin // @[Counter.scala 137:24]
- if (wrap_wrap) begin // @[Counter.scala 86:20]
- loadingCount <= 2'h0; // @[Counter.scala 86:28]
- end else begin
- loadingCount <= _wrap_value_T_1; // @[Counter.scala 76:15]
- end
- end
- REG <= SRAMDataReceived; // @[openram_testchip.scala 49:67]
- if (reset) begin // @[Counter.scala 60:40]
- transferCount <= 1'h0; // @[Counter.scala 60:40]
- end else if (REG) begin // @[Counter.scala 137:24]
- transferCount <= transferCount + 1'h1; // @[Counter.scala 76:15]
- end
- if (_T) begin // @[Counter.scala 135:17]
- wrap <= 1'h0;
- end else begin
- wrap <= _GEN_2;
- end
- if (loadingCount == 2'h0) begin // @[openram_testchip.scala 58:49]
- packetSeq_0 <= io_gpio_packet;
- end
- if (loadingCount == 2'h1) begin // @[openram_testchip.scala 58:49]
- packetSeq_1 <= io_gpio_packet;
- end
- if (wrap_wrap) begin // @[openram_testchip.scala 58:49]
- packetSeq_2 <= io_gpio_packet;
- end
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {3{`RANDOM}};
- input_ = _RAND_0[85:0];
- _RAND_1 = {2{`RANDOM}};
- output_ = _RAND_1[63:0];
- _RAND_2 = {1{`RANDOM}};
- in_sel = _RAND_2[0:0];
- _RAND_3 = {1{`RANDOM}};
- gpio_sel = _RAND_3[0:0];
- _RAND_4 = {1{`RANDOM}};
- la_sel = _RAND_4[0:0];
- _RAND_5 = {1{`RANDOM}};
- SRAMDataReceived = _RAND_5[0:0];
- _RAND_6 = {1{`RANDOM}};
- loadingCount = _RAND_6[1:0];
- _RAND_7 = {1{`RANDOM}};
- REG = _RAND_7[0:0];
- _RAND_8 = {1{`RANDOM}};
- transferCount = _RAND_8[0:0];
- _RAND_9 = {1{`RANDOM}};
- wrap = _RAND_9[0:0];
- _RAND_10 = {1{`RANDOM}};
- packetSeq_0 = _RAND_10[31:0];
- _RAND_11 = {1{`RANDOM}};
- packetSeq_1 = _RAND_11[31:0];
- _RAND_12 = {1{`RANDOM}};
- packetSeq_2 = _RAND_12[31:0];
-`endif // RANDOMIZE_REG_INIT
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
diff --git a/chisel/control_logic-main/control_logic-main/project/build.properties b/chisel/control_logic-main/control_logic-main/project/build.properties
deleted file mode 100644
index ddffd37..0000000
--- a/chisel/control_logic-main/control_logic-main/project/build.properties
+++ /dev/null
@@ -1 +0,0 @@
-sbt.version = 1.4.9
diff --git a/chisel/control_logic-main/control_logic-main/project/plugins.sbt b/chisel/control_logic-main/control_logic-main/project/plugins.sbt
deleted file mode 100644
index 5708f81..0000000
--- a/chisel/control_logic-main/control_logic-main/project/plugins.sbt
+++ /dev/null
@@ -1 +0,0 @@
-logLevel := Level.Warn
diff --git a/chisel/control_logic-main/control_logic-main/src/main/scala/control_logic/openram_testchip.scala b/chisel/control_logic-main/control_logic-main/src/main/scala/control_logic/openram_testchip.scala
deleted file mode 100644
index 9018a72..0000000
--- a/chisel/control_logic-main/control_logic-main/src/main/scala/control_logic/openram_testchip.scala
+++ /dev/null
@@ -1,161 +0,0 @@
-// See README.md for license details.
-
-package openram_testchip
-
-import chisel3._
-import chisel3.util._
-
-import scala.collection.mutable.ArrayBuffer
-
-class openram_testchip extends Module {
- val io = IO(new Bundle{
- val logical_analyzer_packet = Input(UInt(86.W))
- val gpio_packet = Input(UInt(32.W))
- val in_select = Input(Bool())
- val sram0_rw_in = Input(UInt(32.W))
- val sram0_r0_in = Input(UInt(32.W))
- val sram1_rw_in = Input(UInt(32.W))
- val sram1_ro_in = Input(UInt(32.W))
- val sram2_rw_in = Input(UInt(32.W))
- val sram3_rw_in = Input(UInt(32.W))
- val sram4_rw_in = Input(UInt(32.W))
- val sram5_rw_in = Input(UInt(64.W))
- val sram0_connections = Output(UInt(55.W))
- val sram1_connections = Output(UInt(55.W))
- val sram2_connections = Output(UInt(48.W))
- val sram3_connections = Output(UInt(46.W))
- val sram4_connections = Output(UInt(47.W))
- val sram5_connections = Output(UInt(83.W))
- val la_data = Output(UInt(64.W))
- val gpio_data = Output(UInt(32.W))
- })
-
- val input = Reg(UInt(86.W))
- val output = Reg(UInt(64.W))
- val in_sel = RegNext(io.in_select)
-
- val gpio_sel = RegInit(true.B)
- val la_sel = RegNext(io.in_select)
- gpio_sel := io.in_select
-
- def getMask(bitWidth: Int): UInt = {
- val MOD = BigInt(1) << bitWidth
- val MASK = MOD - BigInt(1)
- MASK.U
- }
-
- val SRAMDataReceived = RegInit(false.B)
- val (loadingCount, loadingDone) = Counter(0 until 3, gpio_sel, !gpio_sel)
- val (transferCount, transferDone) = Counter(0 until 2, RegNext(SRAMDataReceived))
-
- val wrap = RegNext(loadingDone)
- val packetSeq = Reg(Vec(3, UInt(32.W)))
- packetSeq := VecInit(Seq.fill(3)(0.U))
-
- input := io.logical_analyzer_packet
-
- gpio_sel := Mux((!wrap && gpio_sel), true.B, false.B)
- (0 until 3).foreach(i => packetSeq(i) := Mux(loadingCount === i.U, io.gpio_packet, packetSeq(i)))
-
- when(wrap && gpio_sel){
- input := Cat(packetSeq(2), packetSeq(1), packetSeq(0))
- }
-
- when(!gpio_sel){
- input := input
- }
- val chip_select: UInt = input(85, 83)
-
- io.sram0_connections := getMask(55)
- io.sram1_connections := getMask(55)
- io.sram2_connections := getMask(48)
- io.sram3_connections := getMask(46)
- io.sram4_connections := getMask(47)
- io.sram5_connections := getMask(83)
-
- val csb0 = input(54)
- val web = input(53)
-
- when(!gpio_sel || !la_sel)
- {
- switch(chip_select){
- is(0.U){
- io.sram0_connections := input.tail(31)
- }
-
- is(1.U){
- io.sram1_connections := input.tail(31)
- }
-
- is(2.U){
- io.sram2_connections := input.tail(38)
- }
-
- is(3.U){
- io.sram3_connections := input.tail(40)
- }
-
- is(4.U){
- io.sram4_connections := input.tail(39)
- }
-
- is(5.U){
- io.sram5_connections := input.tail(3)
- }
- }
- }
-
- output := 0.U
- //If operation is read
- when(web){
- switch(chip_select){
-
- is(0.U){
- output := Mux(csb0, io.sram0_r0_in, io.sram0_rw_in)
- }
-
- is(1.U){
- output := Mux(csb0, io.sram1_ro_in, io.sram1_rw_in)
- }
-
- is(2.U){
- output := io.sram2_rw_in
- }
-
- is(3.U){
- output := io.sram3_rw_in
- }
-
- is(4.U){
- output := io.sram4_rw_in
- }
-
- is(5.U){
- output := io.sram5_rw_in
- }
- }
-
- when(in_sel === 1.U){
- SRAMDataReceived := true.B
- }
- }
-
- io.la_data := 0.U
- io.gpio_data := 0.U
- when(in_sel === 1.U){
- when(transferCount === 0.U){
- io.gpio_data := output(31, 0)
- }.elsewhen(transferCount === 1.U){
- io.gpio_data := output(63, 32)
- SRAMDataReceived := false.B
- }
- }.otherwise{
- io.la_data := output
- }
-}
-
-import chisel3.stage.ChiselStage
-
-object openram_testchipDriver extends App {
- (new ChiselStage).emitVerilog(new openram_testchip)
-}
\ No newline at end of file
diff --git a/chisel/control_logic-main/control_logic-main/src/test/scala/control_logic/openramTestSuite.scala b/chisel/control_logic-main/control_logic-main/src/test/scala/control_logic/openramTestSuite.scala
deleted file mode 100644
index 4213883..0000000
--- a/chisel/control_logic-main/control_logic-main/src/test/scala/control_logic/openramTestSuite.scala
+++ /dev/null
@@ -1,120 +0,0 @@
-package openram_testchip
-
-import chisel3._
-import chisel3.tester._
-import org.scalatest.FreeSpec
-
-import treadle._
-import chisel3.tester.experimental.TestOptionBuilder._
-
-class OpenramTestChipTester extends FreeSpec with ChiselScalatestTester {
-
- "OpenramTestChip should write to SRAM 0" in {
- test(new openram_testchip).withAnnotations(Seq(WriteVcdAnnotation)) { dut =>
- //Writing 1 to address 1 in SRAM 0
- val packet = BigInt("1E020000000200", 16)
- val MOD = (Seq.fill(54)(BigInt(2)).reduce(_*_) )
- val MASK = (Seq.fill(55)(BigInt(2)).reduce(_*_) - 1)
- dut.io.logical_analyzer_packet.poke(packet.U)
- dut.io.gpio_packet.poke(0.U)
- dut.io.in_select.poke(false.B)
- dut.clock.step()
- dut.io.sram0_connections.expect((packet % MOD).U)
- dut.io.sram1_connections.expect(MASK.U)
- }
- }
-
- "OpenramTestChip should accept data from GPIO" in {
- test(new openram_testchip).withAnnotations(Seq(WriteVcdAnnotation)) { dut =>
- //Writing 1 to address 1 in SRAM 0
- val packet = BigInt("1E020000000200", 16)
- val MOD = (Seq.fill(54)(BigInt(2)).reduce(_*_) )
- val MASK = (Seq.fill(55)(BigInt(2)).reduce(_*_) - 1)
- dut.io.logical_analyzer_packet.poke(0.U)
- dut.io.gpio_packet.poke(BigInt("00000200", 16).U)
- dut.io.in_select.poke(true.B)
- dut.clock.step()
- dut.io.gpio_packet.poke(BigInt("001E0200", 16).U)
- dut.clock.step()
- dut.io.gpio_packet.poke(BigInt("00000000", 16).U)
- dut.clock.step(2)
- dut.io.sram0_connections.expect((packet % MOD).U)
- dut.io.sram1_connections.expect(MASK.U)
- dut.clock.step(5)
- dut.io.sram0_connections.expect((packet % MOD).U)
- }
- }
-
- "OpenramTestChip should write to SRAM 1" in {
- test(new openram_testchip).withAnnotations(Seq(WriteVcdAnnotation)) { dut =>
- //Writing 1 to address 1 in SRAM 1
- val packet = BigInt("080000000E020000000200", 16)
- val MOD = (Seq.fill(54)(BigInt(2)).reduce(_*_) )
- val MASK = (Seq.fill(55)(BigInt(2)).reduce(_*_) - 1)
- dut.io.logical_analyzer_packet.poke(packet.U)
- dut.io.gpio_packet.poke(0.U)
- dut.io.in_select.poke(false.B)
- dut.clock.step()
- dut.io.sram0_connections.expect(MASK.U)
- dut.io.sram1_connections.expect((packet % MOD).U)
- }
- }
-
- "OpenramTestChip should read from R/W Port in SRAM 0" in {
- test(new openram_testchip).withAnnotations(Seq(WriteVcdAnnotation)) { dut =>
- //Reading from address 1 in SRAM 0
- val packet = BigInt("20020000000100", 16)
- val MOD = (Seq.fill(54)(BigInt(2)).reduce(_*_) )
- val MASK = (Seq.fill(55)(BigInt(2)).reduce(_*_) - 1)
- dut.io.logical_analyzer_packet.poke(packet.U)
- dut.io.gpio_packet.poke(0.U)
- dut.io.in_select.poke(false.B)
- dut.clock.step()
- dut.io.sram0_connections.expect((packet % MOD).U)
- dut.io.sram1_connections.expect(MASK.U)
- dut.clock.step()
- dut.io.sram0_rw_in.poke(1.U)
- dut.clock.step()
- dut.io.la_data.expect(1.U)
- }
- }
-
- "OpenramTestChip should read from R/W Port in SRAM 0 (GPIO)" in {
- test(new openram_testchip).withAnnotations(Seq(WriteVcdAnnotation)) { dut =>
- //Reading from address 1 in SRAM 0
- val packet = BigInt("20020000000100", 16)
- val MOD = (Seq.fill(54)(BigInt(2)).reduce(_*_) )
- val MASK = (Seq.fill(55)(BigInt(2)).reduce(_*_) - 1)
- dut.io.logical_analyzer_packet.poke(0.U)
- dut.io.gpio_packet.poke(BigInt("00000100", 16).U)
- dut.io.in_select.poke(true.B)
- dut.clock.step()
- dut.io.gpio_packet.poke(BigInt("00200200", 16).U)
- dut.clock.step()
- dut.io.gpio_packet.poke(BigInt("00000000", 16).U)
- dut.clock.step(2)
- dut.io.sram0_connections.expect((packet % MOD).U)
- dut.io.sram1_connections.expect(MASK.U)
- dut.clock.step()
- dut.io.sram0_rw_in.poke(1.U)
- dut.clock.step()
- dut.io.gpio_data.expect(1.U)
- dut.clock.step()
- dut.io.gpio_data.expect(0.U)
- }
- }
-
- "OpenramTestChip should write to shared R/W Port in SRAM 2" in {
- test(new openram_testchip).withAnnotations(Seq(WriteVcdAnnotation)) { dut =>
- //Writing 1 to address 1 in SRAM 1
- val packet = BigInt("100000000E020000000200", 16)
- val MOD = (Seq.fill(47)(BigInt(2)).reduce(_*_) )
- val MASK = (Seq.fill(48)(BigInt(2)).reduce(_*_) - 1)
- dut.io.logical_analyzer_packet.poke(packet.U)
- dut.io.gpio_packet.poke(0.U)
- dut.io.in_select.poke(false.B)
- dut.clock.step()
- dut.io.sram2_connections.expect((packet % MOD).U)
- }
- }
-}
