Proper timing for single cycle input transfer

verilog/rtl/openram_testchip.v

diff --git a/verilog/rtl/openram_testchip.v b/verilog/rtl/openram_testchip.v
index 61b1cea..79a8a70 100644
--- a/verilog/rtl/openram_testchip.v
+++ b/verilog/rtl/openram_testchip.v
@@ -63,17 +63,13 @@
 end

 

 always @(posedge clk) begin

-    toggle_clk <= toggle_clk;

+    sram_clk <= toggle_clk;

     if(toggle_clk) begin

             toggle_clk <= 0;

     end

 end

 

 always @(posedge clk) begin

-    sram_clk <= toggle_clk;   

-end

-

-always @(posedge clk) begin

     if(reset) begin

         csb0 <= 1;

         web <= 1;

@@ -101,12 +97,12 @@
 end

 

 always @ (posedge clk) begin

-    sram0_connections <= (chip_select == 0) ? {sram_clk || toggle_clk, input_connection[54:0]} : {56{1'b0}};

-    sram1_connections <= (chip_select == 1) ? {sram_clk || toggle_clk, input_connection[54:0]} : {56{1'b0}};

-    sram2_connections <= (chip_select == 2) ? {sram_clk || toggle_clk, input_connection[47:0]} : {48{1'b0}};

-    sram3_connections <= (chip_select == 3) ? {sram_clk || toggle_clk, input_connection[45:0]} : {46{1'b0}};

-    sram4_connections <= (chip_select == 4) ? {sram_clk || toggle_clk, input_connection[46:0]} : {47{1'b0}};

-    sram5_connections <= (chip_select == 5) ? {sram_clk || toggle_clk, input_connection[82:0]} : {83{1'b0}};

+    sram0_connections <= (chip_select == 0) ? {sram_clk, input_connection[54:0]} : {56{1'b0}};

+    sram1_connections <= (chip_select == 1) ? {sram_clk, input_connection[54:0]} : {56{1'b0}};

+    sram2_connections <= (chip_select == 2) ? {sram_clk, input_connection[47:0]} : {48{1'b0}};

+    sram3_connections <= (chip_select == 3) ? {sram_clk, input_connection[45:0]} : {46{1'b0}};

+    sram4_connections <= (chip_select == 4) ? {sram_clk, input_connection[46:0]} : {47{1'b0}};

+    sram5_connections <= (chip_select == 5) ? {sram_clk, input_connection[82:0]} : {83{1'b0}};

 end

 

 always @ (posedge clk) begin