commit: 3488ee5eda8e07cb648a47a8c074ab59f6d74280
[log] [tgz]
author: AmoghLonkar <alonkar@ucsc.edu>
Sun May 09 17:12:14 2021 -0700
committer: AmoghLonkar <alonkar@ucsc.edu>
Sun May 09 17:12:14 2021 -0700
tree: a7624f531682f8f85c0a38718a96a2631f558c1f
parent: d286473d5b802e5a07b7461d7c75740274df2374 [diff]

Added new module to receive read data from SRAMs, getting 'not valid l-value error'

verilog/rtl/testchip/control_logic.v[diff]

1 file changed

tree: a7624f531682f8f85c0a38718a96a2631f558c1f

README.md

Caravel User Project

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