Set correct indices for storing read out, inefficient csb0 port assignment

verilog/rtl/openram_testchip.v

diff --git a/verilog/rtl/openram_testchip.v b/verilog/rtl/openram_testchip.v
index d5380f2..85d3dce 100644
--- a/verilog/rtl/openram_testchip.v
+++ b/verilog/rtl/openram_testchip.v
@@ -128,11 +128,12 @@
    end
    // Store results for read out
    else if(gpio_sram_load || la_sram_load) begin
-      sram_register <= {sram_register[`TOTAL_SIZE-1:`TOTAL_SIZE-`SELECT_SIZE-`ADDR_SIZE-1], 
+      
+      sram_register <= {sram_register[`TOTAL_SIZE-1:`TOTAL_SIZE-`SELECT_SIZE-`ADDR_SIZE], 
 			read_data0, 
-			sram_register[`ADDR_SIZE+`DATA_SIZE+2*`WMASK_SIZE+5:`DATA_SIZE+`WMASK_SIZE+3], 
+			sram_register[`ADDR_SIZE+`DATA_SIZE+2*`WMASK_SIZE+3:`DATA_SIZE+`WMASK_SIZE+2], 
 			read_data1, 
-			sram_register[`WMASK_SIZE+3:0]};
+			sram_register[`WMASK_SIZE+1:0]};
    end
 end
 
@@ -157,8 +158,12 @@
    
 // Apply the correct CSB
 always @(*) begin
-   left_csb0 = csb0_temp << chip_select;
-   left_csb1 = csb1_temp << chip_select;
+   left_csb0 = {`MAX_CHIPS{1'b1}};
+   left_csb0[chip_select] = csb0_temp;
+   //left_csb0 = csb0_temp << chip_select;
+   left_csb1 = {`MAX_CHIPS{1'b1}};
+   left_csb1[chip_select] = csb1_temp;
+   //left_csb1 = csb1_temp << chip_select;
 end
    
 // Mux value of correct SRAM data input to feed into 
@@ -235,7 +240,7 @@
 // Output logic
 always @ (*) begin
    gpio_out = sram_register[`TOTAL_SIZE-1];
-   la_data_out = {16'd0, sram_register};
+   la_data_out = sram_register;
 end
 
 endmodule