commit: 4b706b12d28b77a8325e97dca20fc4ec9055cf41
[log] [tgz]
author: AmoghLonkar <alonkar@ucsc.edu>
Tue Jun 15 12:40:41 2021 -0700
committer: AmoghLonkar <alonkar@ucsc.edu>
Tue Jun 15 12:40:41 2021 -0700
tree: 737e3d33e15472f5059b34f54336050779555cdb
parent: 138855579e6a9719c6f161c8a57f7934dd19e852 [diff]

Set correct indices for storing read out, inefficient csb0 port assignment

verilog/rtl/openram_testchip.v[diff]

1 file changed

tree: 737e3d33e15472f5059b34f54336050779555cdb

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for this sample project documentation.