Don't route clocks until debugged
diff --git a/openlane/openram_testchip/config.tcl b/openlane/openram_testchip/config.tcl
index 1e74a48..20be68e 100644
--- a/openlane/openram_testchip/config.tcl
+++ b/openlane/openram_testchip/config.tcl
@@ -10,12 +10,13 @@
$script_dir/../../verilog/rtl/openram_testchip.v"
#set ::env(BASE_SDC_FILE) "$script_dir/clks.sdc"
-set ::env(CLOCK_PORT) "clk"
-set ::env(CLOCK_NET) "clk sram_clk"
+set ::env(CLOCK_PORT) "la_clk"
+#set ::env(CLOCK_NET) "clk sram_clk"
+set ::env(CLOCK_NET) ""
set ::env(CLOCK_PERIOD) "10"
set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 800 2900"
+set ::env(DIE_AREA) "0 0 400 2900"
set ::env(DESIGN_IS_CORE) 0
set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}]
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index fde5bc5..dcfff1a 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -34,18 +34,18 @@
# sram_1rw0r0w_32_256_sky130
# 473 x 220
-SRAM11 2000 800 N
+SRAM11 1300 800 N
# sram_1rw0r0w_32_512_sky130
# 476 x 320
-SRAM10 2000 1200
+SRAM10 1300 1200
# sram_1rw0r0w_32_1024_sky130
# 801 x 348
-SRAM9 2000 1500
+SRAM9 1300 1500
# sram_1rw0r0w_64_512_sky130
# 823 x 335
-SRAM8 2000 2300
+SRAM8 1300 2300
-CONTROL_LOGIC 1000 200 N
+CONTROL_LOGIC 1300 100 N
