Correct setup, debug incorrect byte value
diff --git a/verilog/dv/la_test/la_test.c b/verilog/dv/la_test/la_test.c
index 4928060..a11e1a4 100644
--- a/verilog/dv/la_test/la_test.c
+++ b/verilog/dv/la_test/la_test.c
@@ -75,6 +75,14 @@
// This is to signal when the code is ready to the test bench
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_2 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_3 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_4 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_5 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_7 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT;
/* Apply configuration */
reg_mprj_xfer = 1;
@@ -164,7 +172,7 @@
reg_la1_oenb = reg_la1_iena = 0x00000000; // [63:32]
reg_la2_oenb = reg_la2_iena = 0x00000000; // [95:64]
reg_la3_oenb = reg_la3_iena = 0x00000000; // [127:96]
-
+
//SRAM 1
// Write 1 to address 1
// Send input packet
@@ -230,7 +238,7 @@
reg_la_sample = 1;
// Now read them
if(reg_la0_data != 0x00000050){
- reg_mprj_datal = 0x00000001;
+ reg_mprj_datal = 0x00000005;
}
// Configure LA as CPU output
@@ -304,7 +312,7 @@
reg_la_sample = 1;
// Now read them
if(reg_la0_data != 0x00000050){
- reg_mprj_datal = 0x00000003;
+ reg_mprj_datal = 0x00000009;
}
// Configure LA as CPU output
@@ -378,7 +386,7 @@
reg_la_sample = 1;
// Now read them
if(reg_la0_data != 0x00000050){
- reg_mprj_datal = 0x00000001;
+ reg_mprj_datal = 0x00000011;
}
// Configure LA as CPU output
@@ -452,7 +460,7 @@
reg_la_sample = 1;
// Now read them
if(reg_la0_data != 0x00000050){
- reg_mprj_datal = 0x00000003;
+ reg_mprj_datal = 0x000000021;
}
// Configure LA as CPU output
@@ -460,7 +468,7 @@
reg_la1_oenb = reg_la1_iena = 0x00000000; // [63:32]
reg_la2_oenb = reg_la2_iena = 0x00000000; // [95:64]
reg_la3_oenb = reg_la3_iena = 0x00000000; // [127:96]
-
+
/* SINGLE PORT MEMORIES */
// SRAM 8
// Write DEADBEEF to address 1
@@ -512,7 +520,7 @@
reg_la_sample = 1;
// Now read them
if(reg_la2_data != 0x1DEADBEE){
- reg_mprj_datal = 0x00000001;
+ reg_mprj_datal = 0x00000041;
}
// Configure LA as CPU output
@@ -571,7 +579,7 @@
reg_la_sample = 1;
// Now read them
if(reg_la2_data != 0x1DEADBEE){
- reg_mprj_datal = 0x00000003;
+ reg_mprj_datal = 0x00000081;
}
// Configure LA as CPU output
@@ -630,7 +638,7 @@
reg_la_sample = 1;
// Now read them
if(reg_la2_data != 0x1DEADBEE){
- reg_mprj_datal = 0x00000001;
+ reg_mprj_datal = 0x00000101;
}
// Configure LA as CPU output
@@ -689,7 +697,7 @@
reg_la_sample = 1;
// Now read them
if(reg_la2_data != 0x1DEADBEE){
- reg_mprj_datal = 0x00000003;
+ reg_mprj_datal = 0x00000201;
}
// Configure LA as CPU output
@@ -697,7 +705,7 @@
reg_la1_oenb = reg_la1_iena = 0x00000000; // [63:32]
reg_la2_oenb = reg_la2_iena = 0x00000000; // [95:64]
reg_la3_oenb = reg_la3_iena = 0x00000000; // [127:96]
-
+
// On end, set pin 0 to 0
reg_mprj_datal = 0x00000000;
}
diff --git a/verilog/dv/la_test/la_test_tb.v b/verilog/dv/la_test/la_test_tb.v
index b402295..a4ab56e 100644
--- a/verilog/dv/la_test/la_test_tb.v
+++ b/verilog/dv/la_test/la_test_tb.v
@@ -32,6 +32,14 @@
wire [37:0] mprj_io;
wire mprj_io_0 = mprj_io[0];
wire mprj_io_1 = mprj_io[1];
+ wire mprj_io_2 = mprj_io[2];
+ wire mprj_io_3 = mprj_io[3];
+ wire mprj_io_4 = mprj_io[4];
+ wire mprj_io_5 = mprj_io[5];
+ wire mprj_io_6 = mprj_io[6];
+ wire mprj_io_7 = mprj_io[7];
+ wire mprj_io_8 = mprj_io[8];
+ wire mprj_io_9 = mprj_io[9];
// External clock is used by default. Make this artificially fast for the
// simulation. Normally this would be a slow clock and the digital PLL
@@ -75,32 +83,49 @@
initial begin
wait (mprj_io_1 == 1'b1);
- $display($time, " Data mismatch while reading byte from SRAM 0!");
-
- wait (mprj_io_1 == 1'b0);
- $display($time, " Data mismatch while reading byte from SRAM 1!");
-
- wait (mprj_io_1 == 1'b1);
- $display($time, " Data mismatch while reading byte from SRAM 2!");
-
- wait (mprj_io_1 == 1'b0);
- $display($time, " Data mismatch while reading byte from SRAM 3!");
-
- wait (mprj_io_1 == 1'b1);
- $display($time, " Data mismatch while reading byte from SRAM 4!");
-
- wait (mprj_io_1 == 1'b0);
- $display($time, " Data mismatch while reading byte from SRAM 8!");
-
- wait (mprj_io_1 == 1'b1);
- $display($time, " Data mismatch while reading byte from SRAM 9!");
-
- wait (mprj_io_1 == 1'b0);
- $display($time, " Data mismatch while reading byte from SRAM 10!");
-
- wait (mprj_io_1 == 1'b1);
- $display($time, " Data mismatch while reading byte from SRAM 11!");
+ $display($time, " Data mismatch while reading byte from SRAM 0!"); $finish;
end
+
+ initial begin
+ wait (mprj_io_2 == 1'b1);
+ $display($time, " Data mismatch while reading byte from SRAM 1!"); $finish;
+ end
+
+ initial begin
+ wait (mprj_io_3 == 1'b1);
+ $display($time, " Data mismatch while reading byte from SRAM 2!"); $finish;
+ end
+
+ initial begin
+ wait (mprj_io_4 == 1'b1);
+ $display($time, " Data mismatch while reading byte from SRAM 3!"); $finish;
+ end
+
+ initial begin
+ wait (mprj_io_5 == 1'b1);
+ $display($time, " Data mismatch while reading byte from SRAM 4!"); $finish;
+ end
+
+ initial begin
+ wait (mprj_io_6 == 1'b1);
+ $display($time, " Data mismatch while reading byte from SRAM 8!"); $finish;
+ end
+
+ initial begin
+ wait (mprj_io_7 == 1'b1);
+ $display($time, " Data mismatch while reading byte from SRAM 9!"); $finish;
+ end
+
+ initial begin
+ wait (mprj_io_8 == 1'b1);
+ $display($time, " Data mismatch while reading byte from SRAM 10!"); $finish;
+ end
+
+ initial begin
+ wait (mprj_io_9 == 1'b1);
+ $display($time, " Data mismatch while reading byte from SRAM 11!"); $finish;
+ end
+
initial begin
//$dumpfile("foo.vcd");
//$dumpvars(0, la_test_tb);
