commit 3ff7d0762ac4b96e46cf6fdad8509ef539a41cbf
author AmoghLonkar <alonkar@ucsc.edu> Thu Jun 17 10:20:32 2021 -0700
committer AmoghLonkar <alonkar@ucsc.edu> Thu Jun 17 10:20:32 2021 -0700
tree 0e0fda9792b01764214415d4a3f3b257eae48cf2
parent 9ccd2e3fd21d747e8440b5994af3cccac51a5f5f

Add clock_mux

verilog/rtl/uprj_netlists.v

diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index d678690..25fa95d 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v
@@ -34,4 +34,5 @@
     `include "sram_1rw0r0w_32_512_sky130.v"
     `include "sram_1rw0r0w_32_1024_sky130.v"
     `include "sram_1rw0r0w_64_512_sky130.v"
+    `include "clock_mux.v"
 `endif
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